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13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20#include <asm/war.h>
21
22
23
24
25
26#ifndef __STR
27#define __STR(x) #x
28#endif
29#ifndef STR
30#define STR(x) __STR(x)
31#endif
32
33
34
35
36#ifdef __ASSEMBLY__
37#define _ULCAST_
38#define _U64CAST_
39#else
40#define _ULCAST_ (unsigned long)
41#define _U64CAST_ (u64)
42#endif
43
44
45
46
47#define CP0_INDEX $0
48#define CP0_RANDOM $1
49#define CP0_ENTRYLO0 $2
50#define CP0_ENTRYLO1 $3
51#define CP0_CONF $3
52#define CP0_GLOBALNUMBER $3, 1
53#define CP0_CONTEXT $4
54#define CP0_PAGEMASK $5
55#define CP0_PAGEGRAIN $5, 1
56#define CP0_SEGCTL0 $5, 2
57#define CP0_SEGCTL1 $5, 3
58#define CP0_SEGCTL2 $5, 4
59#define CP0_WIRED $6
60#define CP0_INFO $7
61#define CP0_HWRENA $7
62#define CP0_BADVADDR $8
63#define CP0_BADINSTR $8, 1
64#define CP0_COUNT $9
65#define CP0_ENTRYHI $10
66#define CP0_GUESTCTL1 $10, 4
67#define CP0_GUESTCTL2 $10, 5
68#define CP0_GUESTCTL3 $10, 6
69#define CP0_COMPARE $11
70#define CP0_GUESTCTL0EXT $11, 4
71#define CP0_STATUS $12
72#define CP0_GUESTCTL0 $12, 6
73#define CP0_GTOFFSET $12, 7
74#define CP0_CAUSE $13
75#define CP0_EPC $14
76#define CP0_PRID $15
77#define CP0_EBASE $15, 1
78#define CP0_CMGCRBASE $15, 3
79#define CP0_CONFIG $16
80#define CP0_CONFIG3 $16, 3
81#define CP0_CONFIG5 $16, 5
82#define CP0_CONFIG6 $16, 6
83#define CP0_LLADDR $17
84#define CP0_WATCHLO $18
85#define CP0_WATCHHI $19
86#define CP0_XCONTEXT $20
87#define CP0_FRAMEMASK $21
88#define CP0_DIAGNOSTIC $22
89#define CP0_DEBUG $23
90#define CP0_DEPC $24
91#define CP0_PERFORMANCE $25
92#define CP0_ECC $26
93#define CP0_CACHEERR $27
94#define CP0_TAGLO $28
95#define CP0_TAGHI $29
96#define CP0_ERROREPC $30
97#define CP0_DESAVE $31
98
99
100
101
102
103
104
105#define CP0_IBASE $0
106#define CP0_IBOUND $1
107#define CP0_DBASE $2
108#define CP0_DBOUND $3
109#define CP0_CALG $17
110#define CP0_IWATCH $18
111#define CP0_DWATCH $19
112
113
114
115
116#define CP0_S1_DERRADDR0 $26
117#define CP0_S1_DERRADDR1 $27
118#define CP0_S1_INTCONTROL $20
119
120
121
122
123#define CP0_S2_SRSCTL $12
124
125
126
127
128#define CP0_S3_SRSMAP $12
129
130
131
132
133#define CP0_TX39_CACHE $7
134
135
136
137#define ENTRYLO_G (_ULCAST_(1) << 0)
138#define ENTRYLO_V (_ULCAST_(1) << 1)
139#define ENTRYLO_D (_ULCAST_(1) << 2)
140#define ENTRYLO_C_SHIFT 3
141#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
142
143
144#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
145#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
146#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
147#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
148
149
150#define MIPS_ENTRYLO_PFN_SHIFT 6
151#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
153
154
155
156
157#define MIPS_GLOBALNUMBER_VP_SHF 0
158#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
159#define MIPS_GLOBALNUMBER_CORE_SHF 8
160#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
161#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
162#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
163
164
165
166
167#ifdef CONFIG_CPU_VR41XX
168
169
170
171#define PM_1K 0x00000000
172#define PM_4K 0x00001800
173#define PM_16K 0x00007800
174#define PM_64K 0x0001f800
175#define PM_256K 0x0007f800
176
177#else
178
179#define PM_4K 0x00000000
180#define PM_8K 0x00002000
181#define PM_16K 0x00006000
182#define PM_32K 0x0000e000
183#define PM_64K 0x0001e000
184#define PM_128K 0x0003e000
185#define PM_256K 0x0007e000
186#define PM_512K 0x000fe000
187#define PM_1M 0x001fe000
188#define PM_2M 0x003fe000
189#define PM_4M 0x007fe000
190#define PM_8M 0x00ffe000
191#define PM_16M 0x01ffe000
192#define PM_32M 0x03ffe000
193#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000
195#define PM_1G 0x7fffe000
196
197#endif
198
199
200
201
202#ifdef CONFIG_PAGE_SIZE_4KB
203#define PM_DEFAULT_MASK PM_4K
204#elif defined(CONFIG_PAGE_SIZE_8KB)
205#define PM_DEFAULT_MASK PM_8K
206#elif defined(CONFIG_PAGE_SIZE_16KB)
207#define PM_DEFAULT_MASK PM_16K
208#elif defined(CONFIG_PAGE_SIZE_32KB)
209#define PM_DEFAULT_MASK PM_32K
210#elif defined(CONFIG_PAGE_SIZE_64KB)
211#define PM_DEFAULT_MASK PM_64K
212#else
213#error Bad page size configuration!
214#endif
215
216
217
218
219#ifdef CONFIG_PAGE_SIZE_4KB
220#define PM_HUGE_MASK PM_1M
221#elif defined(CONFIG_PAGE_SIZE_8KB)
222#define PM_HUGE_MASK PM_4M
223#elif defined(CONFIG_PAGE_SIZE_16KB)
224#define PM_HUGE_MASK PM_16M
225#elif defined(CONFIG_PAGE_SIZE_32KB)
226#define PM_HUGE_MASK PM_64M
227#elif defined(CONFIG_PAGE_SIZE_64KB)
228#define PM_HUGE_MASK PM_256M
229#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
230#error Bad page size configuration for hugetlbfs!
231#endif
232
233
234
235
236#define MIPSR6_WIRED_LIMIT_SHIFT 16
237#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
238#define MIPSR6_WIRED_WIRED_SHIFT 0
239#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
240
241
242
243
244#define PL_4K 12
245#define PL_16K 14
246#define PL_64K 16
247#define PL_256K 18
248#define PL_1M 20
249#define PL_4M 22
250#define PL_16M 24
251#define PL_64M 26
252#define PL_256M 28
253
254
255
256
257#define PG_RIE (_ULCAST_(1) << 31)
258#define PG_XIE (_ULCAST_(1) << 30)
259#define PG_ELPA (_ULCAST_(1) << 29)
260#define PG_ESP (_ULCAST_(1) << 28)
261#define PG_IEC (_ULCAST_(1) << 27)
262
263
264#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
265#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
266#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
267
268
269
270
271#define IE_SW0 (_ULCAST_(1) << 8)
272#define IE_SW1 (_ULCAST_(1) << 9)
273#define IE_IRQ0 (_ULCAST_(1) << 10)
274#define IE_IRQ1 (_ULCAST_(1) << 11)
275#define IE_IRQ2 (_ULCAST_(1) << 12)
276#define IE_IRQ3 (_ULCAST_(1) << 13)
277#define IE_IRQ4 (_ULCAST_(1) << 14)
278#define IE_IRQ5 (_ULCAST_(1) << 15)
279
280
281
282
283#define C_SW0 (_ULCAST_(1) << 8)
284#define C_SW1 (_ULCAST_(1) << 9)
285#define C_IRQ0 (_ULCAST_(1) << 10)
286#define C_IRQ1 (_ULCAST_(1) << 11)
287#define C_IRQ2 (_ULCAST_(1) << 12)
288#define C_IRQ3 (_ULCAST_(1) << 13)
289#define C_IRQ4 (_ULCAST_(1) << 14)
290#define C_IRQ5 (_ULCAST_(1) << 15)
291
292
293
294
295#define ST0_IE 0x00000001
296#define ST0_EXL 0x00000002
297#define ST0_ERL 0x00000004
298#define ST0_KSU 0x00000018
299# define KSU_USER 0x00000010
300# define KSU_SUPERVISOR 0x00000008
301# define KSU_KERNEL 0x00000000
302#define ST0_UX 0x00000020
303#define ST0_SX 0x00000040
304#define ST0_KX 0x00000080
305#define ST0_DE 0x00010000
306#define ST0_CE 0x00020000
307
308
309
310
311
312
313#define ST0_CO 0x08000000
314
315
316
317
318#define ST0_IEC 0x00000001
319#define ST0_KUC 0x00000002
320#define ST0_IEP 0x00000004
321#define ST0_KUP 0x00000008
322#define ST0_IEO 0x00000010
323#define ST0_KUO 0x00000020
324
325#define ST0_ISC 0x00010000
326#define ST0_SWC 0x00020000
327#define ST0_CM 0x00080000
328
329
330
331
332#define ST0_UM (_ULCAST_(1) << 4)
333#define ST0_IL (_ULCAST_(1) << 23)
334#define ST0_DL (_ULCAST_(1) << 24)
335
336
337
338
339#define ST0_MX 0x01000000
340
341
342
343
344#define ST0_IM 0x0000ff00
345#define STATUSB_IP0 8
346#define STATUSF_IP0 (_ULCAST_(1) << 8)
347#define STATUSB_IP1 9
348#define STATUSF_IP1 (_ULCAST_(1) << 9)
349#define STATUSB_IP2 10
350#define STATUSF_IP2 (_ULCAST_(1) << 10)
351#define STATUSB_IP3 11
352#define STATUSF_IP3 (_ULCAST_(1) << 11)
353#define STATUSB_IP4 12
354#define STATUSF_IP4 (_ULCAST_(1) << 12)
355#define STATUSB_IP5 13
356#define STATUSF_IP5 (_ULCAST_(1) << 13)
357#define STATUSB_IP6 14
358#define STATUSF_IP6 (_ULCAST_(1) << 14)
359#define STATUSB_IP7 15
360#define STATUSF_IP7 (_ULCAST_(1) << 15)
361#define STATUSB_IP8 0
362#define STATUSF_IP8 (_ULCAST_(1) << 0)
363#define STATUSB_IP9 1
364#define STATUSF_IP9 (_ULCAST_(1) << 1)
365#define STATUSB_IP10 2
366#define STATUSF_IP10 (_ULCAST_(1) << 2)
367#define STATUSB_IP11 3
368#define STATUSF_IP11 (_ULCAST_(1) << 3)
369#define STATUSB_IP12 4
370#define STATUSF_IP12 (_ULCAST_(1) << 4)
371#define STATUSB_IP13 5
372#define STATUSF_IP13 (_ULCAST_(1) << 5)
373#define STATUSB_IP14 6
374#define STATUSF_IP14 (_ULCAST_(1) << 6)
375#define STATUSB_IP15 7
376#define STATUSF_IP15 (_ULCAST_(1) << 7)
377#define ST0_CH 0x00040000
378#define ST0_NMI 0x00080000
379#define ST0_SR 0x00100000
380#define ST0_TS 0x00200000
381#define ST0_BEV 0x00400000
382#define ST0_RE 0x02000000
383#define ST0_FR 0x04000000
384#define ST0_CU 0xf0000000
385#define ST0_CU0 0x10000000
386#define ST0_CU1 0x20000000
387#define ST0_CU2 0x40000000
388#define ST0_CU3 0x80000000
389#define ST0_XX 0x80000000
390
391
392
393
394#define INTCTLB_IPFDC 23
395#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
396#define INTCTLB_IPPCI 26
397#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
398#define INTCTLB_IPTI 29
399#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
400
401
402
403
404
405
406#define CAUSEB_EXCCODE 2
407#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
408#define CAUSEB_IP 8
409#define CAUSEF_IP (_ULCAST_(255) << 8)
410#define CAUSEB_IP0 8
411#define CAUSEF_IP0 (_ULCAST_(1) << 8)
412#define CAUSEB_IP1 9
413#define CAUSEF_IP1 (_ULCAST_(1) << 9)
414#define CAUSEB_IP2 10
415#define CAUSEF_IP2 (_ULCAST_(1) << 10)
416#define CAUSEB_IP3 11
417#define CAUSEF_IP3 (_ULCAST_(1) << 11)
418#define CAUSEB_IP4 12
419#define CAUSEF_IP4 (_ULCAST_(1) << 12)
420#define CAUSEB_IP5 13
421#define CAUSEF_IP5 (_ULCAST_(1) << 13)
422#define CAUSEB_IP6 14
423#define CAUSEF_IP6 (_ULCAST_(1) << 14)
424#define CAUSEB_IP7 15
425#define CAUSEF_IP7 (_ULCAST_(1) << 15)
426#define CAUSEB_FDCI 21
427#define CAUSEF_FDCI (_ULCAST_(1) << 21)
428#define CAUSEB_WP 22
429#define CAUSEF_WP (_ULCAST_(1) << 22)
430#define CAUSEB_IV 23
431#define CAUSEF_IV (_ULCAST_(1) << 23)
432#define CAUSEB_PCI 26
433#define CAUSEF_PCI (_ULCAST_(1) << 26)
434#define CAUSEB_DC 27
435#define CAUSEF_DC (_ULCAST_(1) << 27)
436#define CAUSEB_CE 28
437#define CAUSEF_CE (_ULCAST_(3) << 28)
438#define CAUSEB_TI 30
439#define CAUSEF_TI (_ULCAST_(1) << 30)
440#define CAUSEB_BD 31
441#define CAUSEF_BD (_ULCAST_(1) << 31)
442
443
444
445
446#define EXCCODE_INT 0
447#define EXCCODE_MOD 1
448#define EXCCODE_TLBL 2
449#define EXCCODE_TLBS 3
450#define EXCCODE_ADEL 4
451#define EXCCODE_ADES 5
452#define EXCCODE_IBE 6
453#define EXCCODE_DBE 7
454#define EXCCODE_SYS 8
455#define EXCCODE_BP 9
456#define EXCCODE_RI 10
457#define EXCCODE_CPU 11
458#define EXCCODE_OV 12
459#define EXCCODE_TR 13
460#define EXCCODE_MSAFPE 14
461#define EXCCODE_FPE 15
462#define EXCCODE_TLBRI 19
463#define EXCCODE_TLBXI 20
464#define EXCCODE_MSADIS 21
465#define EXCCODE_MDMX 22
466#define EXCCODE_WATCH 23
467#define EXCCODE_MCHECK 24
468#define EXCCODE_THREAD 25
469#define EXCCODE_DSPDIS 26
470#define EXCCODE_GE 27
471
472
473#define MIPS_EXCCODE_TLBPAR 16
474
475
476
477
478
479#define CONF_CM_CACHABLE_NO_WA 0
480#define CONF_CM_CACHABLE_WA 1
481#define CONF_CM_UNCACHED 2
482#define CONF_CM_CACHABLE_NONCOHERENT 3
483#define CONF_CM_CACHABLE_CE 4
484#define CONF_CM_CACHABLE_COW 5
485#define CONF_CM_CACHABLE_CUW 6
486#define CONF_CM_CACHABLE_ACCELERATED 7
487#define CONF_CM_CMASK 7
488#define CONF_BE (_ULCAST_(1) << 15)
489
490
491#define CONF_CU (_ULCAST_(1) << 3)
492#define CONF_DB (_ULCAST_(1) << 4)
493#define CONF_IB (_ULCAST_(1) << 5)
494#define CONF_DC (_ULCAST_(7) << 6)
495#define CONF_IC (_ULCAST_(7) << 9)
496#define CONF_EB (_ULCAST_(1) << 13)
497#define CONF_EM (_ULCAST_(1) << 14)
498#define CONF_SM (_ULCAST_(1) << 16)
499#define CONF_SC (_ULCAST_(1) << 17)
500#define CONF_EW (_ULCAST_(3) << 18)
501#define CONF_EP (_ULCAST_(15)<< 24)
502#define CONF_EC (_ULCAST_(7) << 28)
503#define CONF_CM (_ULCAST_(1) << 31)
504
505
506#define R4K_CONF_SW (_ULCAST_(1) << 20)
507#define R4K_CONF_SS (_ULCAST_(1) << 21)
508#define R4K_CONF_SB (_ULCAST_(3) << 22)
509
510
511#define R5K_CONF_SE (_ULCAST_(1) << 12)
512#define R5K_CONF_SS (_ULCAST_(3) << 20)
513
514
515#define RM7K_CONF_SE (_ULCAST_(1) << 3)
516#define RM7K_CONF_TE (_ULCAST_(1) << 12)
517#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
518#define RM7K_CONF_TC (_ULCAST_(1) << 17)
519#define RM7K_CONF_SI (_ULCAST_(3) << 20)
520#define RM7K_CONF_SC (_ULCAST_(1) << 31)
521
522
523#define R10K_CONF_DN (_ULCAST_(3) << 3)
524#define R10K_CONF_CT (_ULCAST_(1) << 5)
525#define R10K_CONF_PE (_ULCAST_(1) << 6)
526#define R10K_CONF_PM (_ULCAST_(3) << 7)
527#define R10K_CONF_EC (_ULCAST_(15)<< 9)
528#define R10K_CONF_SB (_ULCAST_(1) << 13)
529#define R10K_CONF_SK (_ULCAST_(1) << 14)
530#define R10K_CONF_SS (_ULCAST_(7) << 16)
531#define R10K_CONF_SC (_ULCAST_(7) << 19)
532#define R10K_CONF_DC (_ULCAST_(7) << 26)
533#define R10K_CONF_IC (_ULCAST_(7) << 29)
534
535
536#define VR41_CONF_CS (_ULCAST_(1) << 12)
537#define VR41_CONF_P4K (_ULCAST_(1) << 13)
538#define VR41_CONF_BP (_ULCAST_(1) << 16)
539#define VR41_CONF_M16 (_ULCAST_(1) << 20)
540#define VR41_CONF_AD (_ULCAST_(1) << 23)
541
542
543#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
544#define R30XX_CONF_REV (_ULCAST_(1) << 22)
545#define R30XX_CONF_AC (_ULCAST_(1) << 23)
546#define R30XX_CONF_RF (_ULCAST_(1) << 24)
547#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
548#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
549#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
550#define R30XX_CONF_SB (_ULCAST_(1) << 30)
551#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
552
553
554#define TX49_CONF_DC (_ULCAST_(1) << 16)
555#define TX49_CONF_IC (_ULCAST_(1) << 17)
556#define TX49_CONF_HALT (_ULCAST_(1) << 18)
557#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
558
559
560#define MIPS_CONF_VI (_ULCAST_(1) << 3)
561#define MIPS_CONF_MT (_ULCAST_(7) << 7)
562#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
563#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
564#define MIPS_CONF_AR (_ULCAST_(7) << 10)
565#define MIPS_CONF_AT (_ULCAST_(3) << 13)
566#define MIPS_CONF_M (_ULCAST_(1) << 31)
567
568
569
570
571#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
572#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
573#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
574#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
575#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
576#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
577#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
578#define MIPS_CONF1_DA_SHF 7
579#define MIPS_CONF1_DA_SZ 3
580#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
581#define MIPS_CONF1_DL_SHF 10
582#define MIPS_CONF1_DL_SZ 3
583#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
584#define MIPS_CONF1_DS_SHF 13
585#define MIPS_CONF1_DS_SZ 3
586#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
587#define MIPS_CONF1_IA_SHF 16
588#define MIPS_CONF1_IA_SZ 3
589#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
590#define MIPS_CONF1_IL_SHF 19
591#define MIPS_CONF1_IL_SZ 3
592#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
593#define MIPS_CONF1_IS_SHF 22
594#define MIPS_CONF1_IS_SZ 3
595#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
596#define MIPS_CONF1_TLBS_SHIFT (25)
597#define MIPS_CONF1_TLBS_SIZE (6)
598#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
599
600#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
601#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
602#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
603#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
604#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
605#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
606#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
607#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
608
609#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
610#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
611#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
612#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
613#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
614#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
615#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
616#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
617#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
618#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
619#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
620#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
621#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
622#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
623#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
624#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
625#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
626#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
627#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
628#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
629#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
630#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
631#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
632#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
633#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
634#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
635#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
636
637#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
638#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
639#define MIPS_CONF4_FTLBSETS_SHIFT (0)
640#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
641#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
642#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
643#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
644
645#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
646
647#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
648#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
649#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
650#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
651#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
652#define MIPS_CONF4_KSCREXIST_SHIFT (16)
653#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
654#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
655#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
656#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
657#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
658#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
659
660#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
661#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
662#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
663#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
664#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
665#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
666#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
667#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
668#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
669#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
670#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
671#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
672#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
673#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
674#define MIPS_CONF5_K (_ULCAST_(1) << 30)
675
676#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
677
678#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
679
680#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
681
682#define MIPS_CONF6_FTLBP_SHIFT (16)
683
684#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
685
686#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
687
688#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
689#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
690
691
692
693
694#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
695
696
697#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
698
699
700#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
701#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
702#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
703#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
704#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
705#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
706#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
707#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
708#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
709#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
710#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
711#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
712#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
713
714
715#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
716#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
717#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
718#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
719#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
720#define MIPS_PERFCTRL_EVENT_S 5
721#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
722#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
723#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
724#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
725#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
726#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
727#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
728#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
729#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
730
731
732#define MIPS_PERFCTRL_VPEID_S 16
733#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
734#define MIPS_PERFCTRL_TCID_S 22
735#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
736#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
737#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
738#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
739#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
740
741
742#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
743
744
745#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
746
747
748#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
749#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
750#define MIPS_MAAR_ADDR_SHIFT 12
751#define MIPS_MAAR_S (_ULCAST_(1) << 1)
752#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
753
754
755#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
756
757
758#define MIPS_EBASE_CPUNUM_SHIFT 0
759#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
760#define MIPS_EBASE_WG_SHIFT 11
761#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
762#define MIPS_EBASE_BASE_SHIFT 12
763#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
764
765
766#define MIPS_CMGCRB_BASE 11
767#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
768
769
770#define MIPS_LLADDR_LLB_SHIFT 0
771#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
772
773
774
775
776#define MIPS_SEGCFG_PA_SHIFT 9
777#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
778#define MIPS_SEGCFG_AM_SHIFT 4
779#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
780#define MIPS_SEGCFG_EU_SHIFT 3
781#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
782#define MIPS_SEGCFG_C_SHIFT 0
783#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
784
785#define MIPS_SEGCFG_UUSK _ULCAST_(7)
786#define MIPS_SEGCFG_USK _ULCAST_(5)
787#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
788#define MIPS_SEGCFG_MUSK _ULCAST_(3)
789#define MIPS_SEGCFG_MSK _ULCAST_(2)
790#define MIPS_SEGCFG_MK _ULCAST_(1)
791#define MIPS_SEGCFG_UK _ULCAST_(0)
792
793#define MIPS_PWFIELD_GDI_SHIFT 24
794#define MIPS_PWFIELD_GDI_MASK 0x3f000000
795#define MIPS_PWFIELD_UDI_SHIFT 18
796#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
797#define MIPS_PWFIELD_MDI_SHIFT 12
798#define MIPS_PWFIELD_MDI_MASK 0x0003f000
799#define MIPS_PWFIELD_PTI_SHIFT 6
800#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
801#define MIPS_PWFIELD_PTEI_SHIFT 0
802#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
803
804#define MIPS_PWSIZE_PS_SHIFT 30
805#define MIPS_PWSIZE_PS_MASK 0x40000000
806#define MIPS_PWSIZE_GDW_SHIFT 24
807#define MIPS_PWSIZE_GDW_MASK 0x3f000000
808#define MIPS_PWSIZE_UDW_SHIFT 18
809#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
810#define MIPS_PWSIZE_MDW_SHIFT 12
811#define MIPS_PWSIZE_MDW_MASK 0x0003f000
812#define MIPS_PWSIZE_PTW_SHIFT 6
813#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
814#define MIPS_PWSIZE_PTEW_SHIFT 0
815#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
816
817#define MIPS_PWCTL_PWEN_SHIFT 31
818#define MIPS_PWCTL_PWEN_MASK 0x80000000
819#define MIPS_PWCTL_XK_SHIFT 28
820#define MIPS_PWCTL_XK_MASK 0x10000000
821#define MIPS_PWCTL_XS_SHIFT 27
822#define MIPS_PWCTL_XS_MASK 0x08000000
823#define MIPS_PWCTL_XU_SHIFT 26
824#define MIPS_PWCTL_XU_MASK 0x04000000
825#define MIPS_PWCTL_DPH_SHIFT 7
826#define MIPS_PWCTL_DPH_MASK 0x00000080
827#define MIPS_PWCTL_HUGEPG_SHIFT 6
828#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
829#define MIPS_PWCTL_PSN_SHIFT 0
830#define MIPS_PWCTL_PSN_MASK 0x0000003f
831
832
833#define MIPS_GCTL0_GM_SHIFT 31
834#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
835#define MIPS_GCTL0_RI_SHIFT 30
836#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
837#define MIPS_GCTL0_MC_SHIFT 29
838#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
839#define MIPS_GCTL0_CP0_SHIFT 28
840#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
841#define MIPS_GCTL0_AT_SHIFT 26
842#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
843#define MIPS_GCTL0_GT_SHIFT 25
844#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
845#define MIPS_GCTL0_CG_SHIFT 24
846#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
847#define MIPS_GCTL0_CF_SHIFT 23
848#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
849#define MIPS_GCTL0_G1_SHIFT 22
850#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
851#define MIPS_GCTL0_G0E_SHIFT 19
852#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
853#define MIPS_GCTL0_PT_SHIFT 18
854#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
855#define MIPS_GCTL0_RAD_SHIFT 9
856#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
857#define MIPS_GCTL0_DRG_SHIFT 8
858#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
859#define MIPS_GCTL0_G2_SHIFT 7
860#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
861#define MIPS_GCTL0_GEXC_SHIFT 2
862#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
863#define MIPS_GCTL0_SFC2_SHIFT 1
864#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
865#define MIPS_GCTL0_SFC1_SHIFT 0
866#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
867
868
869#define MIPS_GCTL0_AT_ROOT 1
870#define MIPS_GCTL0_AT_GUEST 3
871
872
873#define MIPS_GCTL0_GEXC_GPSI 0
874#define MIPS_GCTL0_GEXC_GSFC 1
875#define MIPS_GCTL0_GEXC_HC 2
876#define MIPS_GCTL0_GEXC_GRR 3
877#define MIPS_GCTL0_GEXC_GVA 8
878#define MIPS_GCTL0_GEXC_GHFC 9
879#define MIPS_GCTL0_GEXC_GPA 10
880
881
882#define MIPS_GCTL0EXT_RPW_SHIFT 8
883#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
884#define MIPS_GCTL0EXT_NCC_SHIFT 6
885#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
886#define MIPS_GCTL0EXT_CGI_SHIFT 4
887#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
888#define MIPS_GCTL0EXT_FCD_SHIFT 3
889#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
890#define MIPS_GCTL0EXT_OG_SHIFT 2
891#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
892#define MIPS_GCTL0EXT_BG_SHIFT 1
893#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
894#define MIPS_GCTL0EXT_MG_SHIFT 0
895#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
896
897
898#define MIPS_GCTL0EXT_RPW_BOTH 0
899#define MIPS_GCTL0EXT_RPW_GPA 2
900#define MIPS_GCTL0EXT_RPW_RVA 3
901
902
903#define MIPS_GCTL0EXT_NCC_IND 0
904#define MIPS_GCTL0EXT_NCC_MOD 1
905
906
907#define MIPS_GCTL1_ID_SHIFT 0
908#define MIPS_GCTL1_ID_WIDTH 8
909#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
910#define MIPS_GCTL1_RID_SHIFT 16
911#define MIPS_GCTL1_RID_WIDTH 8
912#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
913#define MIPS_GCTL1_EID_SHIFT 24
914#define MIPS_GCTL1_EID_WIDTH 8
915#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
916
917
918#define MIPS_GCTL1_ROOT_GUESTID 0
919
920
921#define MIPS_CDMMBASE_SIZE_SHIFT 0
922#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
923#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
924#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
925#define MIPS_CDMMBASE_ADDR_SHIFT 11
926#define MIPS_CDMMBASE_ADDR_START 15
927
928
929#define MIPS_HWR_CPUNUM 0
930#define MIPS_HWR_SYNCISTEP 1
931#define MIPS_HWR_CC 2
932#define MIPS_HWR_CCRES 3
933#define MIPS_HWR_ULR 29
934#define MIPS_HWR_IMPL1 30
935#define MIPS_HWR_IMPL2 31
936
937
938#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
939#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
940#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
941#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
942#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
943#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
944#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
945
946
947
948
949#define TX39_CONF_ICS_SHIFT 19
950#define TX39_CONF_ICS_MASK 0x00380000
951#define TX39_CONF_ICS_1KB 0x00000000
952#define TX39_CONF_ICS_2KB 0x00080000
953#define TX39_CONF_ICS_4KB 0x00100000
954#define TX39_CONF_ICS_8KB 0x00180000
955#define TX39_CONF_ICS_16KB 0x00200000
956
957#define TX39_CONF_DCS_SHIFT 16
958#define TX39_CONF_DCS_MASK 0x00070000
959#define TX39_CONF_DCS_1KB 0x00000000
960#define TX39_CONF_DCS_2KB 0x00010000
961#define TX39_CONF_DCS_4KB 0x00020000
962#define TX39_CONF_DCS_8KB 0x00030000
963#define TX39_CONF_DCS_16KB 0x00040000
964
965#define TX39_CONF_CWFON 0x00004000
966#define TX39_CONF_WBON 0x00002000
967#define TX39_CONF_RF_SHIFT 10
968#define TX39_CONF_RF_MASK 0x00000c00
969#define TX39_CONF_DOZE 0x00000200
970#define TX39_CONF_HALT 0x00000100
971#define TX39_CONF_LOCK 0x00000080
972#define TX39_CONF_ICE 0x00000020
973#define TX39_CONF_DCE 0x00000010
974#define TX39_CONF_IRSIZE_SHIFT 2
975#define TX39_CONF_IRSIZE_MASK 0x0000000c
976#define TX39_CONF_DRSIZE_SHIFT 0
977#define TX39_CONF_DRSIZE_MASK 0x00000003
978
979
980
981
982
983#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
984
985#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
986
987#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
988
989
990#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
991
992#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
993
994#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
995
996#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
997
998
999#define CVMCTL_IPPCI_SHIFT 7
1000#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1001#define CVMCTL_IPTI_SHIFT 4
1002#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1003
1004
1005#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1006
1007
1008#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1009#define CVMVMCONF_MMUSIZEM1_S 12
1010#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1011#define CVMVMCONF_RMMUSIZEM1_S 0
1012#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1013
1014
1015
1016
1017#define CP1_REVISION $0
1018#define CP1_UFR $1
1019#define CP1_UNFR $4
1020#define CP1_FCCR $25
1021#define CP1_FEXR $26
1022#define CP1_FENR $28
1023#define CP1_STATUS $31
1024
1025
1026
1027
1028
1029#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1030#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1031#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1032#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1033#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1034#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1035#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1036#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1037#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1038#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1039
1040
1041
1042
1043#define MIPS_FCCR_CONDX_S 0
1044#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1045#define MIPS_FCCR_COND0_S 0
1046#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1047#define MIPS_FCCR_COND1_S 1
1048#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1049#define MIPS_FCCR_COND2_S 2
1050#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1051#define MIPS_FCCR_COND3_S 3
1052#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1053#define MIPS_FCCR_COND4_S 4
1054#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1055#define MIPS_FCCR_COND5_S 5
1056#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1057#define MIPS_FCCR_COND6_S 6
1058#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1059#define MIPS_FCCR_COND7_S 7
1060#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1061
1062
1063
1064
1065#define MIPS_FENR_FS_S 2
1066#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1067
1068
1069
1070
1071#define FPU_CSR_COND_S 23
1072#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1073
1074#define FPU_CSR_FS_S 24
1075#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1076
1077#define FPU_CSR_CONDX_S 25
1078#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1079#define FPU_CSR_COND1_S 25
1080#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1081#define FPU_CSR_COND2_S 26
1082#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1083#define FPU_CSR_COND3_S 27
1084#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1085#define FPU_CSR_COND4_S 28
1086#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1087#define FPU_CSR_COND5_S 29
1088#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1089#define FPU_CSR_COND6_S 30
1090#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1091#define FPU_CSR_COND7_S 31
1092#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1093
1094
1095
1096
1097
1098#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1099
1100#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1101#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1102
1103
1104
1105
1106
1107
1108#define FPU_CSR_ALL_X 0x0003f000
1109#define FPU_CSR_UNI_X 0x00020000
1110#define FPU_CSR_INV_X 0x00010000
1111#define FPU_CSR_DIV_X 0x00008000
1112#define FPU_CSR_OVF_X 0x00004000
1113#define FPU_CSR_UDF_X 0x00002000
1114#define FPU_CSR_INE_X 0x00001000
1115
1116#define FPU_CSR_ALL_E 0x00000f80
1117#define FPU_CSR_INV_E 0x00000800
1118#define FPU_CSR_DIV_E 0x00000400
1119#define FPU_CSR_OVF_E 0x00000200
1120#define FPU_CSR_UDF_E 0x00000100
1121#define FPU_CSR_INE_E 0x00000080
1122
1123#define FPU_CSR_ALL_S 0x0000007c
1124#define FPU_CSR_INV_S 0x00000040
1125#define FPU_CSR_DIV_S 0x00000020
1126#define FPU_CSR_OVF_S 0x00000010
1127#define FPU_CSR_UDF_S 0x00000008
1128#define FPU_CSR_INE_S 0x00000004
1129
1130
1131#define FPU_CSR_RM 0x00000003
1132#define FPU_CSR_RN 0x0
1133#define FPU_CSR_RZ 0x1
1134#define FPU_CSR_RU 0x2
1135#define FPU_CSR_RD 0x3
1136
1137
1138#ifndef __ASSEMBLY__
1139
1140
1141
1142
1143#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1144 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1145#define get_isa16_mode(x) ((x) & 0x1)
1146#define msk_isa16_mode(x) ((x) & ~0x1)
1147#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1148#else
1149#define get_isa16_mode(x) 0
1150#define msk_isa16_mode(x) (x)
1151#define set_isa16_mode(x) do { } while(0)
1152#endif
1153
1154
1155
1156
1157
1158static inline int mm_insn_16bit(u16 insn)
1159{
1160 u16 opcode = (insn >> 10) & 0x7;
1161
1162 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1163}
1164
1165
1166
1167
1168#ifdef CONFIG_CPU_MICROMIPS
1169#define _ASM_INSN16_IF_MM(_enc) \
1170 ".insn\n\t" \
1171 ".hword (" #_enc ")\n\t"
1172#define _ASM_INSN32_IF_MM(_enc) \
1173 ".insn\n\t" \
1174 ".hword ((" #_enc ") >> 16)\n\t" \
1175 ".hword ((" #_enc ") & 0xffff)\n\t"
1176#else
1177#define _ASM_INSN_IF_MIPS(_enc) \
1178 ".insn\n\t" \
1179 ".word (" #_enc ")\n\t"
1180#endif
1181
1182#ifndef _ASM_INSN16_IF_MM
1183#define _ASM_INSN16_IF_MM(_enc)
1184#endif
1185#ifndef _ASM_INSN32_IF_MM
1186#define _ASM_INSN32_IF_MM(_enc)
1187#endif
1188#ifndef _ASM_INSN_IF_MIPS
1189#define _ASM_INSN_IF_MIPS(_enc)
1190#endif
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214#define _IFC_REG(n) \
1215 ".ifc \\r, $" #n "\n\t" \
1216 "\\var = " #n "\n\t" \
1217 ".endif\n\t"
1218
1219__asm__(".macro parse_r var r\n\t"
1220 "\\var = -1\n\t"
1221 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1222 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1223 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1224 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1225 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1226 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1227 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1228 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1229 ".iflt \\var\n\t"
1230 ".error \"Unable to parse register name \\r\"\n\t"
1231 ".endif\n\t"
1232 ".endm");
1233
1234#undef _IFC_REG
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245#define _ASM_MACRO_0(OP, ENC) \
1246 __asm__(".macro " #OP "\n\t" \
1247 ENC \
1248 ".endm")
1249
1250
1251#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1252 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1253 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1254 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1255 ENC \
1256 ".endm")
1257
1258
1259#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1260 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1261 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1262 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1263 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1264 ENC \
1265 ".endm")
1266
1267
1268#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1269 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1270 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1271 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1272 ENC \
1273 ".endm")
1274
1275
1276
1277
1278static inline void tlbinvf(void)
1279{
1280 __asm__ __volatile__(
1281 ".set push\n\t"
1282 ".set noreorder\n\t"
1283 "# tlbinvf\n\t"
1284 _ASM_INSN_IF_MIPS(0x42000004)
1285 _ASM_INSN32_IF_MM(0x0000537c)
1286 ".set pop");
1287}
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297#define read_r10k_perf_cntr(counter) \
1298({ \
1299 unsigned int __res; \
1300 __asm__ __volatile__( \
1301 "mfpc\t%0, %1" \
1302 : "=r" (__res) \
1303 : "i" (counter)); \
1304 \
1305 __res; \
1306})
1307
1308#define write_r10k_perf_cntr(counter,val) \
1309do { \
1310 __asm__ __volatile__( \
1311 "mtpc\t%0, %1" \
1312 : \
1313 : "r" (val), "i" (counter)); \
1314} while (0)
1315
1316#define read_r10k_perf_event(counter) \
1317({ \
1318 unsigned int __res; \
1319 __asm__ __volatile__( \
1320 "mfps\t%0, %1" \
1321 : "=r" (__res) \
1322 : "i" (counter)); \
1323 \
1324 __res; \
1325})
1326
1327#define write_r10k_perf_cntl(counter,val) \
1328do { \
1329 __asm__ __volatile__( \
1330 "mtps\t%0, %1" \
1331 : \
1332 : "r" (val), "i" (counter)); \
1333} while (0)
1334
1335
1336
1337
1338
1339
1340#define ___read_32bit_c0_register(source, sel, vol) \
1341({ unsigned int __res; \
1342 if (sel == 0) \
1343 __asm__ vol( \
1344 "mfc0\t%0, " #source "\n\t" \
1345 : "=r" (__res)); \
1346 else \
1347 __asm__ vol( \
1348 ".set\tmips32\n\t" \
1349 "mfc0\t%0, " #source ", " #sel "\n\t" \
1350 ".set\tmips0\n\t" \
1351 : "=r" (__res)); \
1352 __res; \
1353})
1354
1355#define ___read_64bit_c0_register(source, sel, vol) \
1356({ unsigned long long __res; \
1357 if (sizeof(unsigned long) == 4) \
1358 __res = __read_64bit_c0_split(source, sel, vol); \
1359 else if (sel == 0) \
1360 __asm__ vol( \
1361 ".set\tmips3\n\t" \
1362 "dmfc0\t%0, " #source "\n\t" \
1363 ".set\tmips0" \
1364 : "=r" (__res)); \
1365 else \
1366 __asm__ vol( \
1367 ".set\tmips64\n\t" \
1368 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1369 ".set\tmips0" \
1370 : "=r" (__res)); \
1371 __res; \
1372})
1373
1374#define __read_32bit_c0_register(source, sel) \
1375 ___read_32bit_c0_register(source, sel, __volatile__)
1376
1377#define __read_const_32bit_c0_register(source, sel) \
1378 ___read_32bit_c0_register(source, sel,)
1379
1380#define __read_64bit_c0_register(source, sel) \
1381 ___read_64bit_c0_register(source, sel, __volatile__)
1382
1383#define __read_const_64bit_c0_register(source, sel) \
1384 ___read_64bit_c0_register(source, sel,)
1385
1386#define __write_32bit_c0_register(register, sel, value) \
1387do { \
1388 if (sel == 0) \
1389 __asm__ __volatile__( \
1390 "mtc0\t%z0, " #register "\n\t" \
1391 : : "Jr" ((unsigned int)(value))); \
1392 else \
1393 __asm__ __volatile__( \
1394 ".set\tmips32\n\t" \
1395 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1396 ".set\tmips0" \
1397 : : "Jr" ((unsigned int)(value))); \
1398} while (0)
1399
1400#define __write_64bit_c0_register(register, sel, value) \
1401do { \
1402 if (sizeof(unsigned long) == 4) \
1403 __write_64bit_c0_split(register, sel, value); \
1404 else if (sel == 0) \
1405 __asm__ __volatile__( \
1406 ".set\tmips3\n\t" \
1407 "dmtc0\t%z0, " #register "\n\t" \
1408 ".set\tmips0" \
1409 : : "Jr" (value)); \
1410 else \
1411 __asm__ __volatile__( \
1412 ".set\tmips64\n\t" \
1413 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1414 ".set\tmips0" \
1415 : : "Jr" (value)); \
1416} while (0)
1417
1418#define __read_ulong_c0_register(reg, sel) \
1419 ((sizeof(unsigned long) == 4) ? \
1420 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1421 (unsigned long) __read_64bit_c0_register(reg, sel))
1422
1423#define __read_const_ulong_c0_register(reg, sel) \
1424 ((sizeof(unsigned long) == 4) ? \
1425 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1426 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1427
1428#define __write_ulong_c0_register(reg, sel, val) \
1429do { \
1430 if (sizeof(unsigned long) == 4) \
1431 __write_32bit_c0_register(reg, sel, val); \
1432 else \
1433 __write_64bit_c0_register(reg, sel, val); \
1434} while (0)
1435
1436
1437
1438
1439#define __read_32bit_c0_ctrl_register(source) \
1440({ unsigned int __res; \
1441 __asm__ __volatile__( \
1442 "cfc0\t%0, " #source "\n\t" \
1443 : "=r" (__res)); \
1444 __res; \
1445})
1446
1447#define __write_32bit_c0_ctrl_register(register, value) \
1448do { \
1449 __asm__ __volatile__( \
1450 "ctc0\t%z0, " #register "\n\t" \
1451 : : "Jr" ((unsigned int)(value))); \
1452} while (0)
1453
1454
1455
1456
1457
1458#define __read_64bit_c0_split(source, sel, vol) \
1459({ \
1460 unsigned long long __val; \
1461 unsigned long __flags; \
1462 \
1463 local_irq_save(__flags); \
1464 if (sel == 0) \
1465 __asm__ vol( \
1466 ".set\tmips64\n\t" \
1467 "dmfc0\t%L0, " #source "\n\t" \
1468 "dsra\t%M0, %L0, 32\n\t" \
1469 "sll\t%L0, %L0, 0\n\t" \
1470 ".set\tmips0" \
1471 : "=r" (__val)); \
1472 else \
1473 __asm__ vol( \
1474 ".set\tmips64\n\t" \
1475 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1476 "dsra\t%M0, %L0, 32\n\t" \
1477 "sll\t%L0, %L0, 0\n\t" \
1478 ".set\tmips0" \
1479 : "=r" (__val)); \
1480 local_irq_restore(__flags); \
1481 \
1482 __val; \
1483})
1484
1485#define __write_64bit_c0_split(source, sel, val) \
1486do { \
1487 unsigned long long __tmp = (val); \
1488 unsigned long __flags; \
1489 \
1490 local_irq_save(__flags); \
1491 if (MIPS_ISA_REV >= 2) \
1492 __asm__ __volatile__( \
1493 ".set\tpush\n\t" \
1494 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1495 "dins\t%L0, %M0, 32, 32\n\t" \
1496 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1497 ".set\tpop" \
1498 : "+r" (__tmp)); \
1499 else if (sel == 0) \
1500 __asm__ __volatile__( \
1501 ".set\tmips64\n\t" \
1502 "dsll\t%L0, %L0, 32\n\t" \
1503 "dsrl\t%L0, %L0, 32\n\t" \
1504 "dsll\t%M0, %M0, 32\n\t" \
1505 "or\t%L0, %L0, %M0\n\t" \
1506 "dmtc0\t%L0, " #source "\n\t" \
1507 ".set\tmips0" \
1508 : "+r" (__tmp)); \
1509 else \
1510 __asm__ __volatile__( \
1511 ".set\tmips64\n\t" \
1512 "dsll\t%L0, %L0, 32\n\t" \
1513 "dsrl\t%L0, %L0, 32\n\t" \
1514 "dsll\t%M0, %M0, 32\n\t" \
1515 "or\t%L0, %L0, %M0\n\t" \
1516 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1517 ".set\tmips0" \
1518 : "+r" (__tmp)); \
1519 local_irq_restore(__flags); \
1520} while (0)
1521
1522#ifndef TOOLCHAIN_SUPPORTS_XPA
1523_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1524 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1525 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1526_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1527 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1528 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1529#define _ASM_SET_XPA ""
1530#else
1531#define _ASM_SET_XPA ".set\txpa\n\t"
1532#endif
1533
1534#define __readx_32bit_c0_register(source, sel) \
1535({ \
1536 unsigned int __res; \
1537 \
1538 __asm__ __volatile__( \
1539 " .set push \n" \
1540 " .set mips32r2 \n" \
1541 _ASM_SET_XPA \
1542 " mfhc0 %0, " #source ", %1 \n" \
1543 " .set pop \n" \
1544 : "=r" (__res) \
1545 : "i" (sel)); \
1546 __res; \
1547})
1548
1549#define __writex_32bit_c0_register(register, sel, value) \
1550do { \
1551 __asm__ __volatile__( \
1552 " .set push \n" \
1553 " .set mips32r2 \n" \
1554 _ASM_SET_XPA \
1555 " mthc0 %z0, " #register ", %1 \n" \
1556 " .set pop \n" \
1557 : \
1558 : "Jr" (value), "i" (sel)); \
1559} while (0)
1560
1561#define read_c0_index() __read_32bit_c0_register($0, 0)
1562#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1563
1564#define read_c0_random() __read_32bit_c0_register($1, 0)
1565#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1566
1567#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1568#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1569
1570#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1571#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1572
1573#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1574#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1575
1576#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1577#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1578
1579#define read_c0_conf() __read_32bit_c0_register($3, 0)
1580#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1581
1582#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1583
1584#define read_c0_context() __read_ulong_c0_register($4, 0)
1585#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1586
1587#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1588#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1589
1590#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1591#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1592
1593#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1594#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1595
1596#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1597#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1598
1599#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1600#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1601
1602#define read_c0_wired() __read_32bit_c0_register($6, 0)
1603#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1604
1605#define read_c0_info() __read_32bit_c0_register($7, 0)
1606
1607#define read_c0_cache() __read_32bit_c0_register($7, 0)
1608#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1609
1610#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1611#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1612
1613#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1614#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1615
1616#define read_c0_count() __read_32bit_c0_register($9, 0)
1617#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1618
1619#define read_c0_count2() __read_32bit_c0_register($9, 6)
1620#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1621
1622#define read_c0_count3() __read_32bit_c0_register($9, 7)
1623#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1624
1625#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1626#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1627
1628#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1629#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1630
1631#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1632#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1633
1634#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1635#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1636
1637#define read_c0_compare() __read_32bit_c0_register($11, 0)
1638#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1639
1640#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1641#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1642
1643#define read_c0_compare2() __read_32bit_c0_register($11, 6)
1644#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1645
1646#define read_c0_compare3() __read_32bit_c0_register($11, 7)
1647#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1648
1649#define read_c0_status() __read_32bit_c0_register($12, 0)
1650
1651#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1652
1653#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1654#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1655
1656#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1657#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1658
1659#define read_c0_cause() __read_32bit_c0_register($13, 0)
1660#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1661
1662#define read_c0_epc() __read_ulong_c0_register($14, 0)
1663#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1664
1665#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1666
1667#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1668
1669#define read_c0_config() __read_32bit_c0_register($16, 0)
1670#define read_c0_config1() __read_32bit_c0_register($16, 1)
1671#define read_c0_config2() __read_32bit_c0_register($16, 2)
1672#define read_c0_config3() __read_32bit_c0_register($16, 3)
1673#define read_c0_config4() __read_32bit_c0_register($16, 4)
1674#define read_c0_config5() __read_32bit_c0_register($16, 5)
1675#define read_c0_config6() __read_32bit_c0_register($16, 6)
1676#define read_c0_config7() __read_32bit_c0_register($16, 7)
1677#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1678#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1679#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1680#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1681#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1682#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1683#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1684#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1685
1686#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1687#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1688#define read_c0_maar() __read_ulong_c0_register($17, 1)
1689#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1690#define read_c0_maari() __read_32bit_c0_register($17, 2)
1691#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1692
1693
1694
1695
1696#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1697#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1698#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1699#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1700#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1701#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1702#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1703#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1704#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1705#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1706#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1707#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1708#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1709#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1710#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1711#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1712
1713
1714
1715
1716#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1717#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1718#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1719#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1720#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1721#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1722#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1723#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1724
1725#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1726#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1727#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1728#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1729#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1730#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1731#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1732#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1733
1734#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1735#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1736
1737#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1738#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1739
1740#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1741#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1742
1743#define read_c0_diag() __read_32bit_c0_register($22, 0)
1744#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1745
1746
1747#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1748#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1749
1750#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1751#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1752
1753#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1754#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1755
1756#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1757#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1758
1759#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1760#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1761
1762#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1763#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1764
1765#define read_c0_debug() __read_32bit_c0_register($23, 0)
1766#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1767
1768#define read_c0_depc() __read_ulong_c0_register($24, 0)
1769#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1770
1771
1772
1773
1774#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1775#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1776#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1777#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1778#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1779#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1780#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1781#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1782#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1783#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1784#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1785#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1786#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1787#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1788#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1789#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1790#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1791#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1792#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1793#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1794#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1795#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1796#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1797#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1798
1799#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1800#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1801
1802#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1803#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1804
1805#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1806
1807#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1808#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1809
1810#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1811#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1812
1813#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1814#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1815
1816#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1817#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1818
1819#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1820#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1821
1822#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1823#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1824
1825#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1826#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1827
1828
1829#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1830#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1831
1832#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1833#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1834
1835#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1836#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1837
1838#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1839#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1840
1841#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1842#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1843
1844#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1845#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1846
1847#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1848#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1849
1850
1851#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1852#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1853
1854#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1855#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1856
1857#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1858#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1859
1860
1861#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1862#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1863
1864#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1865#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1866
1867#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1868#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1869
1870#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1871#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1872
1873#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1874#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1875
1876#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1877#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1878
1879
1880#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1881#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1882
1883#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1884#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1885
1886#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1887#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1888
1889#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1890#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1891
1892#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1893#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1894
1895
1896
1897
1898
1899#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1900#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1901
1902#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1903#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1904
1905
1906#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1907#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1908
1909#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1910#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1911
1912#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1913#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1914
1915
1916#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1917#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1918
1919#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1920#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1921
1922#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1923#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1924
1925#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1926#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1927
1928#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1929#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1930
1931
1932#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1933#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1934
1935#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1936#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1937
1938#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1939#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1940
1941#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1942#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1943
1944#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1945#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1946
1947#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1948#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1949
1950
1951
1952
1953
1954#ifndef TOOLCHAIN_SUPPORTS_VIRT
1955_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1956 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1957 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1958_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1959 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1960 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1961_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1962 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1963 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1964_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1965 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1966 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1967_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
1968 _ASM_INSN32_IF_MM(0x0000017c));
1969_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
1970 _ASM_INSN32_IF_MM(0x0000117c));
1971_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
1972 _ASM_INSN32_IF_MM(0x0000217c));
1973_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
1974 _ASM_INSN32_IF_MM(0x0000317c));
1975_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1976 _ASM_INSN32_IF_MM(0x0000517c));
1977#define _ASM_SET_VIRT ""
1978#else
1979#define _ASM_SET_VIRT ".set\tvirt\n\t"
1980#endif
1981
1982#define __read_32bit_gc0_register(source, sel) \
1983({ int __res; \
1984 __asm__ __volatile__( \
1985 ".set\tpush\n\t" \
1986 ".set\tmips32r2\n\t" \
1987 _ASM_SET_VIRT \
1988 "mfgc0\t%0, " #source ", %1\n\t" \
1989 ".set\tpop" \
1990 : "=r" (__res) \
1991 : "i" (sel)); \
1992 __res; \
1993})
1994
1995#define __read_64bit_gc0_register(source, sel) \
1996({ unsigned long long __res; \
1997 __asm__ __volatile__( \
1998 ".set\tpush\n\t" \
1999 ".set\tmips64r2\n\t" \
2000 _ASM_SET_VIRT \
2001 "dmfgc0\t%0, " #source ", %1\n\t" \
2002 ".set\tpop" \
2003 : "=r" (__res) \
2004 : "i" (sel)); \
2005 __res; \
2006})
2007
2008#define __write_32bit_gc0_register(register, sel, value) \
2009do { \
2010 __asm__ __volatile__( \
2011 ".set\tpush\n\t" \
2012 ".set\tmips32r2\n\t" \
2013 _ASM_SET_VIRT \
2014 "mtgc0\t%z0, " #register ", %1\n\t" \
2015 ".set\tpop" \
2016 : : "Jr" ((unsigned int)(value)), \
2017 "i" (sel)); \
2018} while (0)
2019
2020#define __write_64bit_gc0_register(register, sel, value) \
2021do { \
2022 __asm__ __volatile__( \
2023 ".set\tpush\n\t" \
2024 ".set\tmips64r2\n\t" \
2025 _ASM_SET_VIRT \
2026 "dmtgc0\t%z0, " #register ", %1\n\t" \
2027 ".set\tpop" \
2028 : : "Jr" (value), \
2029 "i" (sel)); \
2030} while (0)
2031
2032#define __read_ulong_gc0_register(reg, sel) \
2033 ((sizeof(unsigned long) == 4) ? \
2034 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2035 (unsigned long) __read_64bit_gc0_register(reg, sel))
2036
2037#define __write_ulong_gc0_register(reg, sel, val) \
2038do { \
2039 if (sizeof(unsigned long) == 4) \
2040 __write_32bit_gc0_register(reg, sel, val); \
2041 else \
2042 __write_64bit_gc0_register(reg, sel, val); \
2043} while (0)
2044
2045#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2046#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2047
2048#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2049#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2050
2051#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2052#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2053
2054#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2055#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2056
2057#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2058#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2059
2060#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2061#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2062
2063#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2064#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2065
2066#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2067#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2068
2069#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2070#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2071
2072#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2073#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2074
2075#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2076#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2077
2078#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2079#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2080
2081#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2082#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2083
2084#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2085#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2086
2087#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2088#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2089
2090#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2091#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2092
2093#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2094#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2095
2096#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2097#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2098
2099#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2100#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2101
2102#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2103#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2104
2105#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2106#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2107
2108#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2109
2110#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2111#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2112
2113#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2114#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2115
2116#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2117#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2118
2119#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2120#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2121
2122#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2123#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2124
2125#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2126#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2127
2128#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2129
2130#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2131#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2132
2133#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2134#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2135
2136#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2137#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2138#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2139#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2140#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2141#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2142#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2143#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2144#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2145#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2146#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2147#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2148#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2149#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2150#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2151#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2152
2153#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2154#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2155
2156#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2157#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2158#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2159#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2160#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2161#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2162#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2163#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2164#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2165#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2166#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2167#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2168#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2169#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2170#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2171#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2172
2173#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2174#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2175#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2176#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2177#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2178#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2179#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2180#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2181#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2182#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2183#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2184#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2185#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2186#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2187#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2188#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2189
2190#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2191#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2192
2193#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2194#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2195#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2196#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2197#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2198#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2199#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2200#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2201#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2202#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2203#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2204#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2205#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2206#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2207#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2208#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2209#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2210#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2211#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2212#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2213#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2214#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2215#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2216#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2217
2218#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2219#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2220
2221#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2222#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2223#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2224#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2225#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2226#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2227#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2228#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2229#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2230#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2231#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2232#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2233
2234
2235#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2236#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2237
2238#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2239#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2240
2241#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2242#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2243
2244#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2245#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2246
2247
2248
2249
2250#define _read_32bit_cp1_register(source, gas_hardfloat) \
2251({ \
2252 unsigned int __res; \
2253 \
2254 __asm__ __volatile__( \
2255 " .set push \n" \
2256 " .set reorder \n" \
2257 " # gas fails to assemble cfc1 for some archs, \n" \
2258 " # like Octeon. \n" \
2259 " .set mips1 \n" \
2260 " "STR(gas_hardfloat)" \n" \
2261 " cfc1 %0,"STR(source)" \n" \
2262 " .set pop \n" \
2263 : "=r" (__res)); \
2264 __res; \
2265})
2266
2267#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2268do { \
2269 __asm__ __volatile__( \
2270 " .set push \n" \
2271 " .set reorder \n" \
2272 " "STR(gas_hardfloat)" \n" \
2273 " ctc1 %0,"STR(dest)" \n" \
2274 " .set pop \n" \
2275 : : "r" (val)); \
2276} while (0)
2277
2278#ifdef GAS_HAS_SET_HARDFLOAT
2279#define read_32bit_cp1_register(source) \
2280 _read_32bit_cp1_register(source, .set hardfloat)
2281#define write_32bit_cp1_register(dest, val) \
2282 _write_32bit_cp1_register(dest, val, .set hardfloat)
2283#else
2284#define read_32bit_cp1_register(source) \
2285 _read_32bit_cp1_register(source, )
2286#define write_32bit_cp1_register(dest, val) \
2287 _write_32bit_cp1_register(dest, val, )
2288#endif
2289
2290#ifdef HAVE_AS_DSP
2291#define rddsp(mask) \
2292({ \
2293 unsigned int __dspctl; \
2294 \
2295 __asm__ __volatile__( \
2296 " .set push \n" \
2297 " .set dsp \n" \
2298 " rddsp %0, %x1 \n" \
2299 " .set pop \n" \
2300 : "=r" (__dspctl) \
2301 : "i" (mask)); \
2302 __dspctl; \
2303})
2304
2305#define wrdsp(val, mask) \
2306do { \
2307 __asm__ __volatile__( \
2308 " .set push \n" \
2309 " .set dsp \n" \
2310 " wrdsp %0, %x1 \n" \
2311 " .set pop \n" \
2312 : \
2313 : "r" (val), "i" (mask)); \
2314} while (0)
2315
2316#define mflo0() \
2317({ \
2318 long mflo0; \
2319 __asm__( \
2320 " .set push \n" \
2321 " .set dsp \n" \
2322 " mflo %0, $ac0 \n" \
2323 " .set pop \n" \
2324 : "=r" (mflo0)); \
2325 mflo0; \
2326})
2327
2328#define mflo1() \
2329({ \
2330 long mflo1; \
2331 __asm__( \
2332 " .set push \n" \
2333 " .set dsp \n" \
2334 " mflo %0, $ac1 \n" \
2335 " .set pop \n" \
2336 : "=r" (mflo1)); \
2337 mflo1; \
2338})
2339
2340#define mflo2() \
2341({ \
2342 long mflo2; \
2343 __asm__( \
2344 " .set push \n" \
2345 " .set dsp \n" \
2346 " mflo %0, $ac2 \n" \
2347 " .set pop \n" \
2348 : "=r" (mflo2)); \
2349 mflo2; \
2350})
2351
2352#define mflo3() \
2353({ \
2354 long mflo3; \
2355 __asm__( \
2356 " .set push \n" \
2357 " .set dsp \n" \
2358 " mflo %0, $ac3 \n" \
2359 " .set pop \n" \
2360 : "=r" (mflo3)); \
2361 mflo3; \
2362})
2363
2364#define mfhi0() \
2365({ \
2366 long mfhi0; \
2367 __asm__( \
2368 " .set push \n" \
2369 " .set dsp \n" \
2370 " mfhi %0, $ac0 \n" \
2371 " .set pop \n" \
2372 : "=r" (mfhi0)); \
2373 mfhi0; \
2374})
2375
2376#define mfhi1() \
2377({ \
2378 long mfhi1; \
2379 __asm__( \
2380 " .set push \n" \
2381 " .set dsp \n" \
2382 " mfhi %0, $ac1 \n" \
2383 " .set pop \n" \
2384 : "=r" (mfhi1)); \
2385 mfhi1; \
2386})
2387
2388#define mfhi2() \
2389({ \
2390 long mfhi2; \
2391 __asm__( \
2392 " .set push \n" \
2393 " .set dsp \n" \
2394 " mfhi %0, $ac2 \n" \
2395 " .set pop \n" \
2396 : "=r" (mfhi2)); \
2397 mfhi2; \
2398})
2399
2400#define mfhi3() \
2401({ \
2402 long mfhi3; \
2403 __asm__( \
2404 " .set push \n" \
2405 " .set dsp \n" \
2406 " mfhi %0, $ac3 \n" \
2407 " .set pop \n" \
2408 : "=r" (mfhi3)); \
2409 mfhi3; \
2410})
2411
2412
2413#define mtlo0(x) \
2414({ \
2415 __asm__( \
2416 " .set push \n" \
2417 " .set dsp \n" \
2418 " mtlo %0, $ac0 \n" \
2419 " .set pop \n" \
2420 : \
2421 : "r" (x)); \
2422})
2423
2424#define mtlo1(x) \
2425({ \
2426 __asm__( \
2427 " .set push \n" \
2428 " .set dsp \n" \
2429 " mtlo %0, $ac1 \n" \
2430 " .set pop \n" \
2431 : \
2432 : "r" (x)); \
2433})
2434
2435#define mtlo2(x) \
2436({ \
2437 __asm__( \
2438 " .set push \n" \
2439 " .set dsp \n" \
2440 " mtlo %0, $ac2 \n" \
2441 " .set pop \n" \
2442 : \
2443 : "r" (x)); \
2444})
2445
2446#define mtlo3(x) \
2447({ \
2448 __asm__( \
2449 " .set push \n" \
2450 " .set dsp \n" \
2451 " mtlo %0, $ac3 \n" \
2452 " .set pop \n" \
2453 : \
2454 : "r" (x)); \
2455})
2456
2457#define mthi0(x) \
2458({ \
2459 __asm__( \
2460 " .set push \n" \
2461 " .set dsp \n" \
2462 " mthi %0, $ac0 \n" \
2463 " .set pop \n" \
2464 : \
2465 : "r" (x)); \
2466})
2467
2468#define mthi1(x) \
2469({ \
2470 __asm__( \
2471 " .set push \n" \
2472 " .set dsp \n" \
2473 " mthi %0, $ac1 \n" \
2474 " .set pop \n" \
2475 : \
2476 : "r" (x)); \
2477})
2478
2479#define mthi2(x) \
2480({ \
2481 __asm__( \
2482 " .set push \n" \
2483 " .set dsp \n" \
2484 " mthi %0, $ac2 \n" \
2485 " .set pop \n" \
2486 : \
2487 : "r" (x)); \
2488})
2489
2490#define mthi3(x) \
2491({ \
2492 __asm__( \
2493 " .set push \n" \
2494 " .set dsp \n" \
2495 " mthi %0, $ac3 \n" \
2496 " .set pop \n" \
2497 : \
2498 : "r" (x)); \
2499})
2500
2501#else
2502
2503#define rddsp(mask) \
2504({ \
2505 unsigned int __res; \
2506 \
2507 __asm__ __volatile__( \
2508 " .set push \n" \
2509 " .set noat \n" \
2510 " # rddsp $1, %x1 \n" \
2511 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2512 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2513 " move %0, $1 \n" \
2514 " .set pop \n" \
2515 : "=r" (__res) \
2516 : "i" (mask)); \
2517 __res; \
2518})
2519
2520#define wrdsp(val, mask) \
2521do { \
2522 __asm__ __volatile__( \
2523 " .set push \n" \
2524 " .set noat \n" \
2525 " move $1, %0 \n" \
2526 " # wrdsp $1, %x1 \n" \
2527 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2528 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2529 " .set pop \n" \
2530 : \
2531 : "r" (val), "i" (mask)); \
2532} while (0)
2533
2534#define _dsp_mfxxx(ins) \
2535({ \
2536 unsigned long __treg; \
2537 \
2538 __asm__ __volatile__( \
2539 " .set push \n" \
2540 " .set noat \n" \
2541 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2542 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2543 " move %0, $1 \n" \
2544 " .set pop \n" \
2545 : "=r" (__treg) \
2546 : "i" (ins)); \
2547 __treg; \
2548})
2549
2550#define _dsp_mtxxx(val, ins) \
2551do { \
2552 __asm__ __volatile__( \
2553 " .set push \n" \
2554 " .set noat \n" \
2555 " move $1, %0 \n" \
2556 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2557 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2558 " .set pop \n" \
2559 : \
2560 : "r" (val), "i" (ins)); \
2561} while (0)
2562
2563#ifdef CONFIG_CPU_MICROMIPS
2564
2565#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2566#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2567
2568#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2569#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2570
2571#else
2572
2573#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2574#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2575
2576#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2577#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2578
2579#endif
2580
2581#define mflo0() _dsp_mflo(0)
2582#define mflo1() _dsp_mflo(1)
2583#define mflo2() _dsp_mflo(2)
2584#define mflo3() _dsp_mflo(3)
2585
2586#define mfhi0() _dsp_mfhi(0)
2587#define mfhi1() _dsp_mfhi(1)
2588#define mfhi2() _dsp_mfhi(2)
2589#define mfhi3() _dsp_mfhi(3)
2590
2591#define mtlo0(x) _dsp_mtlo(x, 0)
2592#define mtlo1(x) _dsp_mtlo(x, 1)
2593#define mtlo2(x) _dsp_mtlo(x, 2)
2594#define mtlo3(x) _dsp_mtlo(x, 3)
2595
2596#define mthi0(x) _dsp_mthi(x, 0)
2597#define mthi1(x) _dsp_mthi(x, 1)
2598#define mthi2(x) _dsp_mthi(x, 2)
2599#define mthi3(x) _dsp_mthi(x, 3)
2600
2601#endif
2602
2603
2604
2605
2606
2607
2608static inline void tlb_probe(void)
2609{
2610 __asm__ __volatile__(
2611 ".set noreorder\n\t"
2612 "tlbp\n\t"
2613 ".set reorder");
2614}
2615
2616static inline void tlb_read(void)
2617{
2618#if MIPS34K_MISSED_ITLB_WAR
2619 int res = 0;
2620
2621 __asm__ __volatile__(
2622 " .set push \n"
2623 " .set noreorder \n"
2624 " .set noat \n"
2625 " .set mips32r2 \n"
2626 " .word 0x41610001 # dvpe $1 \n"
2627 " move %0, $1 \n"
2628 " ehb \n"
2629 " .set pop \n"
2630 : "=r" (res));
2631
2632 instruction_hazard();
2633#endif
2634
2635 __asm__ __volatile__(
2636 ".set noreorder\n\t"
2637 "tlbr\n\t"
2638 ".set reorder");
2639
2640#if MIPS34K_MISSED_ITLB_WAR
2641 if ((res & _ULCAST_(1)))
2642 __asm__ __volatile__(
2643 " .set push \n"
2644 " .set noreorder \n"
2645 " .set noat \n"
2646 " .set mips32r2 \n"
2647 " .word 0x41600021 # evpe \n"
2648 " ehb \n"
2649 " .set pop \n");
2650#endif
2651}
2652
2653static inline void tlb_write_indexed(void)
2654{
2655 __asm__ __volatile__(
2656 ".set noreorder\n\t"
2657 "tlbwi\n\t"
2658 ".set reorder");
2659}
2660
2661static inline void tlb_write_random(void)
2662{
2663 __asm__ __volatile__(
2664 ".set noreorder\n\t"
2665 "tlbwr\n\t"
2666 ".set reorder");
2667}
2668
2669
2670
2671
2672
2673
2674static inline void guest_tlb_probe(void)
2675{
2676 __asm__ __volatile__(
2677 ".set push\n\t"
2678 ".set noreorder\n\t"
2679 _ASM_SET_VIRT
2680 "tlbgp\n\t"
2681 ".set pop");
2682}
2683
2684static inline void guest_tlb_read(void)
2685{
2686 __asm__ __volatile__(
2687 ".set push\n\t"
2688 ".set noreorder\n\t"
2689 _ASM_SET_VIRT
2690 "tlbgr\n\t"
2691 ".set pop");
2692}
2693
2694static inline void guest_tlb_write_indexed(void)
2695{
2696 __asm__ __volatile__(
2697 ".set push\n\t"
2698 ".set noreorder\n\t"
2699 _ASM_SET_VIRT
2700 "tlbgwi\n\t"
2701 ".set pop");
2702}
2703
2704static inline void guest_tlb_write_random(void)
2705{
2706 __asm__ __volatile__(
2707 ".set push\n\t"
2708 ".set noreorder\n\t"
2709 _ASM_SET_VIRT
2710 "tlbgwr\n\t"
2711 ".set pop");
2712}
2713
2714
2715
2716
2717static inline void guest_tlbinvf(void)
2718{
2719 __asm__ __volatile__(
2720 ".set push\n\t"
2721 ".set noreorder\n\t"
2722 _ASM_SET_VIRT
2723 "tlbginvf\n\t"
2724 ".set pop");
2725}
2726
2727
2728
2729
2730#define __BUILD_SET_COMMON(name) \
2731static inline unsigned int \
2732set_##name(unsigned int set) \
2733{ \
2734 unsigned int res, new; \
2735 \
2736 res = read_##name(); \
2737 new = res | set; \
2738 write_##name(new); \
2739 \
2740 return res; \
2741} \
2742 \
2743static inline unsigned int \
2744clear_##name(unsigned int clear) \
2745{ \
2746 unsigned int res, new; \
2747 \
2748 res = read_##name(); \
2749 new = res & ~clear; \
2750 write_##name(new); \
2751 \
2752 return res; \
2753} \
2754 \
2755static inline unsigned int \
2756change_##name(unsigned int change, unsigned int val) \
2757{ \
2758 unsigned int res, new; \
2759 \
2760 res = read_##name(); \
2761 new = res & ~change; \
2762 new |= (val & change); \
2763 write_##name(new); \
2764 \
2765 return res; \
2766}
2767
2768
2769
2770
2771#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2772
2773__BUILD_SET_C0(status)
2774__BUILD_SET_C0(cause)
2775__BUILD_SET_C0(config)
2776__BUILD_SET_C0(config5)
2777__BUILD_SET_C0(intcontrol)
2778__BUILD_SET_C0(intctl)
2779__BUILD_SET_C0(srsmap)
2780__BUILD_SET_C0(pagegrain)
2781__BUILD_SET_C0(guestctl0)
2782__BUILD_SET_C0(guestctl0ext)
2783__BUILD_SET_C0(guestctl1)
2784__BUILD_SET_C0(guestctl2)
2785__BUILD_SET_C0(guestctl3)
2786__BUILD_SET_C0(brcm_config_0)
2787__BUILD_SET_C0(brcm_bus_pll)
2788__BUILD_SET_C0(brcm_reset)
2789__BUILD_SET_C0(brcm_cmt_intr)
2790__BUILD_SET_C0(brcm_cmt_ctrl)
2791__BUILD_SET_C0(brcm_config)
2792__BUILD_SET_C0(brcm_mode)
2793
2794
2795
2796
2797#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2798
2799__BUILD_SET_GC0(wired)
2800__BUILD_SET_GC0(status)
2801__BUILD_SET_GC0(cause)
2802__BUILD_SET_GC0(ebase)
2803__BUILD_SET_GC0(config1)
2804
2805
2806
2807
2808
2809static inline unsigned int get_ebase_cpunum(void)
2810{
2811 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2812}
2813
2814#endif
2815
2816#endif
2817