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22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/seq_file.h>
26#include <linux/string.h>
27#include <linux/of.h>
28#include <asm/cpuinfo.h>
29
30struct cpuinfo cpuinfo;
31
32#define err_cpu(x) \
33 pr_err("ERROR: Nios II " x " different for kernel and DTS\n")
34
35static inline u32 fcpu(struct device_node *cpu, const char *n)
36{
37 u32 val = 0;
38
39 of_property_read_u32(cpu, n, &val);
40
41 return val;
42}
43
44void __init setup_cpuinfo(void)
45{
46 struct device_node *cpu;
47 const char *str;
48 int len;
49
50 cpu = of_find_node_by_type(NULL, "cpu");
51 if (!cpu)
52 panic("%s: No CPU found in devicetree!\n", __func__);
53
54 if (!of_property_read_bool(cpu, "altr,has-initda"))
55 panic("initda instruction is unimplemented. Please update your "
56 "hardware system to have more than 4-byte line data "
57 "cache\n");
58
59 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency");
60
61 str = of_get_property(cpu, "altr,implementation", &len);
62 if (str)
63 strlcpy(cpuinfo.cpu_impl, str, sizeof(cpuinfo.cpu_impl));
64 else
65 strcpy(cpuinfo.cpu_impl, "<unknown>");
66
67 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div");
68 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul");
69 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx");
70 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx");
71 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx");
72 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu");
73
74 if (IS_ENABLED(CONFIG_NIOS2_HW_DIV_SUPPORT) && !cpuinfo.has_div)
75 err_cpu("DIV");
76
77 if (IS_ENABLED(CONFIG_NIOS2_HW_MUL_SUPPORT) && !cpuinfo.has_mul)
78 err_cpu("MUL");
79
80 if (IS_ENABLED(CONFIG_NIOS2_HW_MULX_SUPPORT) && !cpuinfo.has_mulx)
81 err_cpu("MULX");
82
83 if (IS_ENABLED(CONFIG_NIOS2_BMX_SUPPORT) && !cpuinfo.has_bmx)
84 err_cpu("BMX");
85
86 if (IS_ENABLED(CONFIG_NIOS2_CDX_SUPPORT) && !cpuinfo.has_cdx)
87 err_cpu("CDX");
88
89 cpuinfo.tlb_num_ways = fcpu(cpu, "altr,tlb-num-ways");
90 if (!cpuinfo.tlb_num_ways)
91 panic("altr,tlb-num-ways can't be 0. Please check your hardware "
92 "system\n");
93 cpuinfo.icache_line_size = fcpu(cpu, "icache-line-size");
94 cpuinfo.icache_size = fcpu(cpu, "icache-size");
95 if (CONFIG_NIOS2_ICACHE_SIZE != cpuinfo.icache_size)
96 pr_warn("Warning: icache size configuration mismatch "
97 "(0x%x vs 0x%x) of CONFIG_NIOS2_ICACHE_SIZE vs "
98 "device tree icache-size\n",
99 CONFIG_NIOS2_ICACHE_SIZE, cpuinfo.icache_size);
100
101 cpuinfo.dcache_line_size = fcpu(cpu, "dcache-line-size");
102 if (CONFIG_NIOS2_DCACHE_LINE_SIZE != cpuinfo.dcache_line_size)
103 pr_warn("Warning: dcache line size configuration mismatch "
104 "(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_LINE_SIZE vs "
105 "device tree dcache-line-size\n",
106 CONFIG_NIOS2_DCACHE_LINE_SIZE, cpuinfo.dcache_line_size);
107 cpuinfo.dcache_size = fcpu(cpu, "dcache-size");
108 if (CONFIG_NIOS2_DCACHE_SIZE != cpuinfo.dcache_size)
109 pr_warn("Warning: dcache size configuration mismatch "
110 "(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_SIZE vs "
111 "device tree dcache-size\n",
112 CONFIG_NIOS2_DCACHE_SIZE, cpuinfo.dcache_size);
113
114 cpuinfo.tlb_pid_num_bits = fcpu(cpu, "altr,pid-num-bits");
115 cpuinfo.tlb_num_ways_log2 = ilog2(cpuinfo.tlb_num_ways);
116 cpuinfo.tlb_num_entries = fcpu(cpu, "altr,tlb-num-entries");
117 cpuinfo.tlb_num_lines = cpuinfo.tlb_num_entries / cpuinfo.tlb_num_ways;
118 cpuinfo.tlb_ptr_sz = fcpu(cpu, "altr,tlb-ptr-sz");
119
120 cpuinfo.reset_addr = fcpu(cpu, "altr,reset-addr");
121 cpuinfo.exception_addr = fcpu(cpu, "altr,exception-addr");
122 cpuinfo.fast_tlb_miss_exc_addr = fcpu(cpu, "altr,fast-tlb-miss-addr");
123}
124
125#ifdef CONFIG_PROC_FS
126
127
128
129
130static int show_cpuinfo(struct seq_file *m, void *v)
131{
132 const u32 clockfreq = cpuinfo.cpu_clock_freq;
133
134 seq_printf(m,
135 "CPU:\t\tNios II/%s\n"
136 "REV:\t\t%i\n"
137 "MMU:\t\t%s\n"
138 "FPU:\t\tnone\n"
139 "Clocking:\t%u.%02u MHz\n"
140 "BogoMips:\t%lu.%02lu\n"
141 "Calibration:\t%lu loops\n",
142 cpuinfo.cpu_impl,
143 CONFIG_NIOS2_ARCH_REVISION,
144 cpuinfo.mmu ? "present" : "none",
145 clockfreq / 1000000, (clockfreq / 100000) % 10,
146 (loops_per_jiffy * HZ) / 500000,
147 ((loops_per_jiffy * HZ) / 5000) % 100,
148 (loops_per_jiffy * HZ));
149
150 seq_printf(m,
151 "HW:\n"
152 " MUL:\t\t%s\n"
153 " MULX:\t\t%s\n"
154 " DIV:\t\t%s\n"
155 " BMX:\t\t%s\n"
156 " CDX:\t\t%s\n",
157 cpuinfo.has_mul ? "yes" : "no",
158 cpuinfo.has_mulx ? "yes" : "no",
159 cpuinfo.has_div ? "yes" : "no",
160 cpuinfo.has_bmx ? "yes" : "no",
161 cpuinfo.has_cdx ? "yes" : "no");
162
163 seq_printf(m,
164 "Icache:\t\t%ukB, line length: %u\n",
165 cpuinfo.icache_size >> 10,
166 cpuinfo.icache_line_size);
167
168 seq_printf(m,
169 "Dcache:\t\t%ukB, line length: %u\n",
170 cpuinfo.dcache_size >> 10,
171 cpuinfo.dcache_line_size);
172
173 seq_printf(m,
174 "TLB:\t\t%u ways, %u entries, %u PID bits\n",
175 cpuinfo.tlb_num_ways,
176 cpuinfo.tlb_num_entries,
177 cpuinfo.tlb_pid_num_bits);
178
179 return 0;
180}
181
182static void *cpuinfo_start(struct seq_file *m, loff_t *pos)
183{
184 unsigned long i = *pos;
185
186 return i < num_possible_cpus() ? (void *) (i + 1) : NULL;
187}
188
189static void *cpuinfo_next(struct seq_file *m, void *v, loff_t *pos)
190{
191 ++*pos;
192 return cpuinfo_start(m, pos);
193}
194
195static void cpuinfo_stop(struct seq_file *m, void *v)
196{
197}
198
199const struct seq_operations cpuinfo_op = {
200 .start = cpuinfo_start,
201 .next = cpuinfo_next,
202 .stop = cpuinfo_stop,
203 .show = show_cpuinfo
204};
205
206#endif
207
