1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2#ifndef _ASM_POWERPC_SIGCONTEXT_H 3#define _ASM_POWERPC_SIGCONTEXT_H 4 5/* 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11#include <linux/compiler.h> 12#include <asm/ptrace.h> 13#ifdef __powerpc64__ 14#include <asm/elf.h> 15#endif 16 17struct sigcontext { 18 unsigned long _unused[4]; 19 int signal; 20#ifdef __powerpc64__ 21 int _pad0; 22#endif 23 unsigned long handler; 24 unsigned long oldmask; 25 struct pt_regs __user *regs; 26#ifdef __powerpc64__ 27 elf_gregset_t gp_regs; 28 elf_fpregset_t fp_regs; 29/* 30 * To maintain compatibility with current implementations the sigcontext is 31 * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) 32 * followed by an unstructured (vmx_reserve) field of 101 doublewords. This 33 * allows the array of vector registers to be quadword aligned independent of 34 * the alignment of the containing sigcontext or ucontext. It is the 35 * responsibility of the code setting the sigcontext to set this pointer to 36 * either NULL (if this processor does not support the VMX feature) or the 37 * address of the first quadword within the allocated (vmx_reserve) area. 38 * 39 * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with 40 * an array of 34 quadword entries (elf_vrregset_t). The entries with 41 * indexes 0-31 contain the corresponding vector registers. The entry with 42 * index 32 contains the vscr as the last word (offset 12) within the 43 * quadword. This allows the vscr to be stored as either a quadword (since 44 * it must be copied via a vector register to/from storage) or as a word. 45 * The entry with index 33 contains the vrsave as the first word (offset 0) 46 * within the quadword. 47 * 48 * Part of the VSX data is stored here also by extending vmx_restore 49 * by an additional 32 double words. Architecturally the layout of 50 * the VSR registers and how they overlap on top of the legacy FPR and 51 * VR registers is shown below: 52 * 53 * VSR doubleword 0 VSR doubleword 1 54 * ---------------------------------------------------------------- 55 * VSR[0] | FPR[0] | | 56 * ---------------------------------------------------------------- 57 * VSR[1] | FPR[1] | | 58 * ---------------------------------------------------------------- 59 * | ... | | 60 * | ... | | 61 * ---------------------------------------------------------------- 62 * VSR[30] | FPR[30] | | 63 * ---------------------------------------------------------------- 64 * VSR[31] | FPR[31] | | 65 * ---------------------------------------------------------------- 66 * VSR[32] | VR[0] | 67 * ---------------------------------------------------------------- 68 * VSR[33] | VR[1] | 69 * ---------------------------------------------------------------- 70 * | ... | 71 * | ... | 72 * ---------------------------------------------------------------- 73 * VSR[62] | VR[30] | 74 * ---------------------------------------------------------------- 75 * VSR[63] | VR[31] | 76 * ---------------------------------------------------------------- 77 * 78 * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63 79 * is stored at the start of vmx_reserve. vmx_reserve is extended for 80 * backwards compatility to store VSR 0-31 doubleword 1 after the VMX 81 * registers and vscr/vrsave. 82 */ 83 elf_vrreg_t __user *v_regs; 84 long vmx_reserve[ELF_NVRREG + ELF_NVRREG + 1 + 32]; 85#endif 86}; 87 88#endif /* _ASM_POWERPC_SIGCONTEXT_H */ 89