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18#include <linux/kernel.h>
19#include <linux/of_fdt.h>
20#include <asm/machdep.h>
21#include <asm/pgtable.h>
22#include <asm/time.h>
23#include <asm/udbg.h>
24#include <asm/mpic.h>
25#include <sysdev/fsl_soc.h>
26#include <sysdev/fsl_pci.h>
27#include "smp.h"
28#include "mpc85xx.h"
29
30void __init qemu_e500_pic_init(void)
31{
32 struct mpic *mpic;
33 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
34 MPIC_ENABLE_COREINT;
35
36 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
37
38 BUG_ON(mpic == NULL);
39 mpic_init(mpic);
40}
41
42static void __init qemu_e500_setup_arch(void)
43{
44 ppc_md.progress("qemu_e500_setup_arch()", 0);
45
46 fsl_pci_assign_primary();
47 swiotlb_detect_4g();
48#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
49
50
51
52
53
54
55 limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
56#endif
57 mpc85xx_smp_init();
58}
59
60
61
62
63static int __init qemu_e500_probe(void)
64{
65 return !!of_machine_is_compatible("fsl,qemu-e500");
66}
67
68machine_arch_initcall(qemu_e500, mpc85xx_common_publish_devices);
69
70define_machine(qemu_e500) {
71 .name = "QEMU e500",
72 .probe = qemu_e500_probe,
73 .setup_arch = qemu_e500_setup_arch,
74 .init_IRQ = qemu_e500_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
78#endif
79 .get_irq = mpic_get_coreint_irq,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82};
83