LXR linux/arch/sh/include/asm/watchdog.h

   1/*
   2 * include/asm-sh/watchdog.h
   3 *
   4 * Copyright (C) 2002, 2003 Paul Mundt
   5 * Copyright (C) 2009 Siemens AG
   6 * Copyright (C) 2009 Valentin Sitdikov
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms of the GNU General Public License as published by the
  10 * Free Software Foundation; either version 2 of the License, or (at your
  11 * option) any later version.
  12 */
  13#ifndef __ASM_SH_WATCHDOG_H
  14#define __ASM_SH_WATCHDOG_H
  15#ifdef __KERNEL__
  16
  17#include <linux/types.h>
  18#include <linux/io.h>
  19
  20#define WTCNT_HIGH      0x5a
  21#define WTCSR_HIGH      0xa5
  22
  23#define WTCSR_CKS2      0x04
  24#define WTCSR_CKS1      0x02
  25#define WTCSR_CKS0      0x01
  26
  27#include <cpu/watchdog.h>
  28
  29/*
  30 * See cpu-sh2/watchdog.h for explanation of this stupidity..
  31 */
  32#ifndef WTCNT_R
  33#  define WTCNT_R       WTCNT
  34#endif
  35
  36#ifndef WTCSR_R
  37#  define WTCSR_R       WTCSR
  38#endif
  39
  40/*
  41 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
  42 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
  43 * something a little more reasonable, and really can't deal with anything
  44 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
  45 *
  46 * Clock Division Ratio         Overflow Period
  47 * --------------------------------------------
  48 *     1/32 (initial value)       41 usecs
  49 *     1/64                       82 usecs
  50 *     1/128                     164 usecs
  51 *     1/256                     328 usecs
  52 *     1/512                     656 usecs
  53 *     1/1024                   1.31 msecs
  54 *     1/2048                   2.62 msecs
  55 *     1/4096                   5.25 msecs
  56 */
  57#define WTCSR_CKS_32    0x00
  58#define WTCSR_CKS_64    0x01
  59#define WTCSR_CKS_128   0x02
  60#define WTCSR_CKS_256   0x03
  61#define WTCSR_CKS_512   0x04
  62#define WTCSR_CKS_1024  0x05
  63#define WTCSR_CKS_2048  0x06
  64#define WTCSR_CKS_4096  0x07
  65
  66#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
  67/**
  68 *      sh_wdt_read_cnt - Read from Counter
  69 *      Reads back the WTCNT value.
  70 */
  71static inline __u32 sh_wdt_read_cnt(void)
  72{
  73        return __raw_readl(WTCNT_R);
  74}
  75
  76/**
  77 *      sh_wdt_write_cnt - Write to Counter
  78 *      @val: Value to write
  79 *
  80 *      Writes the given value @val to the lower byte of the timer counter.
  81 *      The upper byte is set manually on each write.
  82 */
  83static inline void sh_wdt_write_cnt(__u32 val)
  84{
  85        __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
  86}
  87
  88/**
  89 *      sh_wdt_write_bst - Write to Counter
  90 *      @val: Value to write
  91 *
  92 *      Writes the given value @val to the lower byte of the timer counter.
  93 *      The upper byte is set manually on each write.
  94 */
  95static inline void sh_wdt_write_bst(__u32 val)
  96{
  97        __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
  98}
  99/**
 100 *      sh_wdt_read_csr - Read from Control/Status Register
 101 *
 102 *      Reads back the WTCSR value.
 103 */
 104static inline __u32 sh_wdt_read_csr(void)
 105{
 106        return __raw_readl(WTCSR_R);
 107}
 108
 109/**
 110 *      sh_wdt_write_csr - Write to Control/Status Register
 111 *      @val: Value to write
 112 *
 113 *      Writes the given value @val to the lower byte of the control/status
 114 *      register. The upper byte is set manually on each write.
 115 */
 116static inline void sh_wdt_write_csr(__u32 val)
 117{
 118        __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
 119}
 120#else
 121/**
 122 *      sh_wdt_read_cnt - Read from Counter
 123 *      Reads back the WTCNT value.
 124 */
 125static inline __u8 sh_wdt_read_cnt(void)
 126{
 127        return __raw_readb(WTCNT_R);
 128}
 129
 130/**
 131 *      sh_wdt_write_cnt - Write to Counter
 132 *      @val: Value to write
 133 *
 134 *      Writes the given value @val to the lower byte of the timer counter.
 135 *      The upper byte is set manually on each write.
 136 */
 137static inline void sh_wdt_write_cnt(__u8 val)
 138{
 139        __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
 140}
 141
 142/**
 143 *      sh_wdt_read_csr - Read from Control/Status Register
 144 *
 145 *      Reads back the WTCSR value.
 146 */
 147static inline __u8 sh_wdt_read_csr(void)
 148{
 149        return __raw_readb(WTCSR_R);
 150}
 151
 152/**
 153 *      sh_wdt_write_csr - Write to Control/Status Register
 154 *      @val: Value to write
 155 *
 156 *      Writes the given value @val to the lower byte of the control/status
 157 *      register. The upper byte is set manually on each write.
 158 */
 159static inline void sh_wdt_write_csr(__u8 val)
 160{
 161        __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
 162}
 163#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
 164#endif /* __KERNEL__ */
 165#endif /* __ASM_SH_WATCHDOG_H */
 166