LXR linux/arch/x86/include/asm/pgtable

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_X86_PGTABLE_32_H
   3#define _ASM_X86_PGTABLE_32_H
   4
   5#include <asm/pgtable_32_types.h>
   6
   7/*
   8 * The Linux memory management assumes a three-level page table setup. On
   9 * the i386, we use that, but "fold" the mid level into the top-level page
  10 * table, so that we physically have the same two-level page table as the
  11 * i386 mmu expects.
  12 *
  13 * This file contains the functions and defines necessary to modify and use
  14 * the i386 page table tree.
  15 */
  16#ifndef __ASSEMBLY__
  17#include <asm/processor.h>
  18#include <linux/threads.h>
  19#include <asm/paravirt.h>
  20
  21#include <linux/bitops.h>
  22#include <linux/list.h>
  23#include <linux/spinlock.h>
  24
  25struct mm_struct;
  26struct vm_area_struct;
  27
  28extern pgd_t swapper_pg_dir[1024];
  29extern pgd_t initial_page_table[1024];
  30extern pmd_t initial_pg_pmd[];
  31
  32static inline void pgtable_cache_init(void) { }
  33static inline void check_pgt_cache(void) { }
  34void paging_init(void);
  35void sync_initial_page_table(void);
  36
  37/*
  38 * Define this if things work differently on an i386 and an i486:
  39 * it will (on an i486) warn about kernel memory accesses that are
  40 * done without a 'access_ok(VERIFY_WRITE,..)'
  41 */
  42#undef TEST_ACCESS_OK
  43
  44#ifdef CONFIG_X86_PAE
  45# include <asm/pgtable-3level.h>
  46#else
  47# include <asm/pgtable-2level.h>
  48#endif
  49
  50#if defined(CONFIG_HIGHPTE)
  51#define pte_offset_map(dir, address)                                    \
  52        ((pte_t *)kmap_atomic(pmd_page(*(dir))) +               \
  53         pte_index((address)))
  54#define pte_unmap(pte) kunmap_atomic((pte))
  55#else
  56#define pte_offset_map(dir, address)                                    \
  57        ((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
  58#define pte_unmap(pte) do { } while (0)
  59#endif
  60
  61/* Clear a kernel PTE and flush it from the TLB */
  62#define kpte_clear_flush(ptep, vaddr)           \
  63do {                                            \
  64        pte_clear(&init_mm, (vaddr), (ptep));   \
  65        __flush_tlb_one_kernel((vaddr));                \
  66} while (0)
  67
  68#endif /* !__ASSEMBLY__ */
  69
  70/*
  71 * kern_addr_valid() is (1) for FLATMEM and (0) for
  72 * SPARSEMEM and DISCONTIGMEM
  73 */
  74#ifdef CONFIG_FLATMEM
  75#define kern_addr_valid(addr)   (1)
  76#else
  77#define kern_addr_valid(kaddr)  (0)
  78#endif
  79
  80/*
  81 * This is how much memory in addition to the memory covered up to
  82 * and including _end we need mapped initially.
  83 * We need:
  84 *     (KERNEL_IMAGE_SIZE/4096) / 1024 pages (worst case, non PAE)
  85 *     (KERNEL_IMAGE_SIZE/4096) / 512 + 4 pages (worst case for PAE)
  86 *
  87 * Modulo rounding, each megabyte assigned here requires a kilobyte of
  88 * memory, which is currently unreclaimed.
  89 *
  90 * This should be a multiple of a page.
  91 *
  92 * KERNEL_IMAGE_SIZE should be greater than pa(_end)
  93 * and small than max_low_pfn, otherwise will waste some page table entries
  94 */
  95#if PTRS_PER_PMD > 1
  96#define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD)
  97#else
  98#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD)
  99#endif
 100
 101/*
 102 * Number of possible pages in the lowmem region.
 103 *
 104 * We shift 2 by 31 instead of 1 by 32 to the left in order to avoid a
 105 * gas warning about overflowing shift count when gas has been compiled
 106 * with only a host target support using a 32-bit type for internal
 107 * representation.
 108 */
 109#define LOWMEM_PAGES ((((2<<31) - __PAGE_OFFSET) >> PAGE_SHIFT))
 110
 111#endif /* _ASM_X86_PGTABLE_32_H */
 112