LXR linux/drivers/clk/tegra/clk-tegra-pmc.c

   1/*
   2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16
  17#include <linux/io.h>
  18#include <linux/clk-provider.h>
  19#include <linux/clkdev.h>
  20#include <linux/of.h>
  21#include <linux/of_address.h>
  22#include <linux/delay.h>
  23#include <linux/export.h>
  24#include <linux/clk/tegra.h>
  25
  26#include "clk.h"
  27#include "clk-id.h"
  28
  29#define PMC_CLK_OUT_CNTRL 0x1a8
  30#define PMC_DPD_PADS_ORIDE 0x1c
  31#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
  32#define PMC_CTRL 0
  33#define PMC_CTRL_BLINK_ENB 7
  34#define PMC_BLINK_TIMER 0x40
  35
  36struct pmc_clk_init_data {
  37        char *mux_name;
  38        char *gate_name;
  39        const char **parents;
  40        int num_parents;
  41        int mux_id;
  42        int gate_id;
  43        char *dev_name;
  44        u8 mux_shift;
  45        u8 gate_shift;
  46};
  47
  48#define PMC_CLK(_num, _mux_shift, _gate_shift)\
  49        {\
  50                .mux_name = "clk_out_" #_num "_mux",\
  51                .gate_name = "clk_out_" #_num,\
  52                .parents = clk_out ##_num ##_parents,\
  53                .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
  54                .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
  55                .gate_id = tegra_clk_clk_out_ ##_num,\
  56                .dev_name = "extern" #_num,\
  57                .mux_shift = _mux_shift,\
  58                .gate_shift = _gate_shift,\
  59        }
  60
  61static DEFINE_SPINLOCK(clk_out_lock);
  62
  63static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
  64        "clk_m_div4", "extern1",
  65};
  66
  67static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
  68        "clk_m_div4", "extern2",
  69};
  70
  71static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
  72        "clk_m_div4", "extern3",
  73};
  74
  75static struct pmc_clk_init_data pmc_clks[] = {
  76        PMC_CLK(1, 6, 2),
  77        PMC_CLK(2, 14, 10),
  78        PMC_CLK(3, 22, 18),
  79};
  80
  81void __init tegra_pmc_clk_init(void __iomem *pmc_base,
  82                                struct tegra_clk *tegra_clks)
  83{
  84        struct clk *clk;
  85        struct clk **dt_clk;
  86        int i;
  87
  88        for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
  89                struct pmc_clk_init_data *data;
  90
  91                data = pmc_clks + i;
  92
  93                dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
  94                if (!dt_clk)
  95                        continue;
  96
  97                clk = clk_register_mux(NULL, data->mux_name, data->parents,
  98                                data->num_parents,
  99                                CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
 100                                pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
 101                                3, 0, &clk_out_lock);
 102                *dt_clk = clk;
 103
 104
 105                dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
 106                if (!dt_clk)
 107                        continue;
 108
 109                clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
 110                                        CLK_SET_RATE_PARENT,
 111                                        pmc_base + PMC_CLK_OUT_CNTRL,
 112                                        data->gate_shift, 0, &clk_out_lock);
 113                *dt_clk = clk;
 114                clk_register_clkdev(clk, data->dev_name, data->gate_name);
 115        }
 116
 117        /* blink */
 118        writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
 119        clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
 120                                pmc_base + PMC_DPD_PADS_ORIDE,
 121                                PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
 122
 123        dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
 124        if (!dt_clk)
 125                return;
 126
 127        clk = clk_register_gate(NULL, "blink", "blink_override", 0,
 128                                pmc_base + PMC_CTRL,
 129                                PMC_CTRL_BLINK_ENB, 0, NULL);
 130        clk_register_clkdev(clk, "blink", NULL);
 131        *dt_clk = clk;
 132}
 133
 134