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8#ifndef __SAFEXCEL_H__
9#define __SAFEXCEL_H__
10
11#include <crypto/aead.h>
12#include <crypto/algapi.h>
13#include <crypto/internal/hash.h>
14#include <crypto/sha.h>
15#include <crypto/skcipher.h>
16
17#define EIP197_HIA_VERSION_LE 0xca35
18#define EIP197_HIA_VERSION_BE 0x35ca
19
20
21#define EIP197_DEFAULT_RING_SIZE 400
22#define EIP197_MAX_TOKENS 8
23#define EIP197_MAX_RINGS 4
24#define EIP197_FETCH_COUNT 1
25#define EIP197_MAX_BATCH_SZ 64
26
27#define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
28 GFP_KERNEL : GFP_ATOMIC)
29
30
31#define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
32 sizeof(struct safexcel_cipher_req)
33#define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
34 sizeof(struct safexcel_ahash_req)
35#define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
36 sizeof(struct safexcel_cipher_req)
37#define EIP197_REQUEST_ON_STACK(name, type, size) \
38 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
39 struct type##_request *name = (void *)__##name##_desc
40
41
42#define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
43#define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
44#define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
45#define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
46#define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
47#define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
48#define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
49#define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
50#define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
51#define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
52
53
54#define EIP197_HIA_AIC_BASE 0x90000
55#define EIP197_HIA_AIC_G_BASE 0x90000
56#define EIP197_HIA_AIC_R_BASE 0x90800
57#define EIP197_HIA_AIC_xDR_BASE 0x80000
58#define EIP197_HIA_DFE_BASE 0x8c000
59#define EIP197_HIA_DFE_THR_BASE 0x8c040
60#define EIP197_HIA_DSE_BASE 0x8d000
61#define EIP197_HIA_DSE_THR_BASE 0x8d040
62#define EIP197_HIA_GEN_CFG_BASE 0xf0000
63#define EIP197_PE_BASE 0xa0000
64
65
66#define EIP97_HIA_AIC_BASE 0x0
67#define EIP97_HIA_AIC_G_BASE 0x0
68#define EIP97_HIA_AIC_R_BASE 0x0
69#define EIP97_HIA_AIC_xDR_BASE 0x0
70#define EIP97_HIA_DFE_BASE 0xf000
71#define EIP97_HIA_DFE_THR_BASE 0xf200
72#define EIP97_HIA_DSE_BASE 0xf400
73#define EIP97_HIA_DSE_THR_BASE 0xf600
74#define EIP97_HIA_GEN_CFG_BASE 0x10000
75#define EIP97_PE_BASE 0x10000
76
77
78#define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
79#define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
80#define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
81#define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
82#define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
83#define EIP197_HIA_xDR_RING_SIZE 0x0018
84#define EIP197_HIA_xDR_DESC_SIZE 0x001c
85#define EIP197_HIA_xDR_CFG 0x0020
86#define EIP197_HIA_xDR_DMA_CFG 0x0024
87#define EIP197_HIA_xDR_THRESH 0x0028
88#define EIP197_HIA_xDR_PREP_COUNT 0x002c
89#define EIP197_HIA_xDR_PROC_COUNT 0x0030
90#define EIP197_HIA_xDR_PREP_PNTR 0x0034
91#define EIP197_HIA_xDR_PROC_PNTR 0x0038
92#define EIP197_HIA_xDR_STAT 0x003c
93
94
95#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
96#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
97#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
98#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
99#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
100#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
101#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
102#define EIP197_HIA_RA_PE_STAT 0x0014
103#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
104#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
105#define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
106#define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
107#define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
108#define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
109#define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
110#define EIP197_HIA_AIC_G_ACK 0xf810
111#define EIP197_HIA_MST_CTRL 0xfff4
112#define EIP197_HIA_OPTIONS 0xfff8
113#define EIP197_HIA_VERSION 0xfffc
114#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
115#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
116#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
117#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
118#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
119#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
120#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
121#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
122#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
123#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
124#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
125#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
126#define EIP197_MST_CTRL 0xfff4
127
128
129#define EIP197_CLASSIFICATION_RAMS 0xe0000
130#define EIP197_TRC_CTRL 0xf0800
131#define EIP197_TRC_LASTRES 0xf0804
132#define EIP197_TRC_REGINDEX 0xf0808
133#define EIP197_TRC_PARAMS 0xf0820
134#define EIP197_TRC_FREECHAIN 0xf0824
135#define EIP197_TRC_PARAMS2 0xf0828
136#define EIP197_TRC_ECCCTRL 0xf0830
137#define EIP197_TRC_ECCSTAT 0xf0834
138#define EIP197_TRC_ECCADMINSTAT 0xf0838
139#define EIP197_TRC_ECCDATASTAT 0xf083c
140#define EIP197_TRC_ECCDATA 0xf0840
141#define EIP197_CS_RAM_CTRL 0xf7ff0
142
143
144#define EIP197_xDR_DESC_MODE_64BIT BIT(31)
145
146
147#define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
148#define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
149#define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
150#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
151#define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
152
153
154#define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
155#define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
156#define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
157#define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24)
158
159
160#define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
161#define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
162#define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24)
163
164
165#define EIP197_xDR_PREP_CLR_COUNT BIT(31)
166
167
168#define EIP197_xDR_PROC_xD_PKT_OFFSET 24
169#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
170#define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2)
171#define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
172#define EIP197_xDR_PROC_CLR_COUNT BIT(31)
173
174
175#define EIP197_xDR_DMA_ERR BIT(0)
176#define EIP197_xDR_PREP_CMD_THRES BIT(1)
177#define EIP197_xDR_ERR BIT(2)
178#define EIP197_xDR_THRESH BIT(4)
179#define EIP197_xDR_TIMEOUT BIT(5)
180
181#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
182#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
183
184
185#define EIP197_N_PES_OFFSET 4
186#define EIP197_N_PES_MASK GENMASK(4, 0)
187#define EIP97_N_PES_MASK GENMASK(2, 0)
188
189
190#define EIP197_CDR_IRQ(n) BIT((n) * 2)
191#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
192
193
194#define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
195#define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
196#define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
197#define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
198#define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
199#define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
200#define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
201#define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29))
202#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
203#define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31)
204
205
206#define EIP197_DxE_THR_CTRL_EN BIT(30)
207#define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
208
209
210#define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
211#define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
212#define EIP197_G_IRQ_RING BIT(16)
213#define EIP197_G_IRQ_PE(n) BIT((n) + 20)
214
215
216#define RD_CACHE_3BITS 0x5
217#define WR_CACHE_3BITS 0x3
218#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
219#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
220#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
221#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
222#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
223#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
224#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
225
226
227#define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
228#define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
229
230
231#define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
232#define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
233
234
235#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
236#define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
237#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
238#define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
239
240
241#define EIP197_NUM_OF_SCRATCH_BLOCKS 32
242
243
244#define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
245#define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
246#define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
247
248
249#define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
250#define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
251
252
253#define EIP197_FUNCTION_RSVD (BIT(6) | BIT(15) | BIT(20) | BIT(23))
254#define EIP197_PROTOCOL_HASH_ONLY BIT(0)
255#define EIP197_PROTOCOL_ENCRYPT_ONLY BIT(1)
256#define EIP197_PROTOCOL_HASH_ENCRYPT BIT(2)
257#define EIP197_PROTOCOL_HASH_DECRYPT BIT(3)
258#define EIP197_PROTOCOL_ENCRYPT_HASH BIT(4)
259#define EIP197_PROTOCOL_DECRYPT_HASH BIT(5)
260#define EIP197_ALG_ARC4 BIT(7)
261#define EIP197_ALG_AES_ECB BIT(8)
262#define EIP197_ALG_AES_CBC BIT(9)
263#define EIP197_ALG_AES_CTR_ICM BIT(10)
264#define EIP197_ALG_AES_OFB BIT(11)
265#define EIP197_ALG_AES_CFB BIT(12)
266#define EIP197_ALG_DES_ECB BIT(13)
267#define EIP197_ALG_DES_CBC BIT(14)
268#define EIP197_ALG_DES_OFB BIT(16)
269#define EIP197_ALG_DES_CFB BIT(17)
270#define EIP197_ALG_3DES_ECB BIT(18)
271#define EIP197_ALG_3DES_CBC BIT(19)
272#define EIP197_ALG_3DES_OFB BIT(21)
273#define EIP197_ALG_3DES_CFB BIT(22)
274#define EIP197_ALG_MD5 BIT(24)
275#define EIP197_ALG_HMAC_MD5 BIT(25)
276#define EIP197_ALG_SHA1 BIT(26)
277#define EIP197_ALG_HMAC_SHA1 BIT(27)
278#define EIP197_ALG_SHA2 BIT(28)
279#define EIP197_ALG_HMAC_SHA2 BIT(29)
280#define EIP197_ALG_AES_XCBC_MAC BIT(30)
281#define EIP197_ALG_GCM_HASH BIT(31)
282
283
284#define EIP197_CONTEXT_SIZE(n) (n)
285#define EIP197_ADDRESS_MODE BIT(8)
286#define EIP197_CONTROL_MODE BIT(9)
287
288
289struct safexcel_context_record {
290 u32 control0;
291 u32 control1;
292
293 __le32 data[40];
294} __packed;
295
296
297#define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
298#define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
299#define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
300#define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
301#define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
302#define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
303#define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
304#define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
305#define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
306#define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
307#define CONTEXT_CONTROL_RESTART_HASH BIT(4)
308#define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
309#define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
310#define CONTEXT_CONTROL_KEY_EN BIT(16)
311#define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
312#define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
313#define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
314#define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
315#define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
316#define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
317#define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
318#define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
319#define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
320#define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
321#define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
322#define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
323#define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
324#define CONTEXT_CONTROL_INV_FR (0x5 << 24)
325#define CONTEXT_CONTROL_INV_TR (0x6 << 24)
326
327
328#define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
329#define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
330#define CONTEXT_CONTROL_IV0 BIT(5)
331#define CONTEXT_CONTROL_IV1 BIT(6)
332#define CONTEXT_CONTROL_IV2 BIT(7)
333#define CONTEXT_CONTROL_IV3 BIT(8)
334#define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
335#define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
336#define CONTEXT_CONTROL_HASH_STORE BIT(19)
337
338
339
340
341#define EIP197_COUNTER_BLOCK_SIZE 64
342
343
344#define EIP197_TRC_ENABLE_0 BIT(4)
345#define EIP197_TRC_ENABLE_1 BIT(5)
346#define EIP197_TRC_ENABLE_2 BIT(6)
347#define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
348
349
350#define EIP197_TRC_PARAMS_SW_RESET BIT(0)
351#define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
352#define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
353#define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
354#define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
355
356
357#define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
358#define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
359
360
361#define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
362#define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
363
364
365#define EIP197B_CS_RC_MAX 52
366#define EIP197D_CS_RC_MAX 96
367#define EIP197_CS_RC_SIZE (4 * sizeof(u32))
368#define EIP197_CS_RC_NEXT(x) (x)
369#define EIP197_CS_RC_PREV(x) ((x) << 10)
370#define EIP197_RC_NULL 0x3ff
371#define EIP197B_CS_TRC_REC_WC 59
372#define EIP197D_CS_TRC_REC_WC 64
373#define EIP197B_CS_TRC_LG_REC_WC 73
374#define EIP197D_CS_TRC_LG_REC_WC 80
375#define EIP197B_CS_HT_WC 64
376#define EIP197D_CS_HT_WC 256
377
378
379
380struct result_data_desc {
381 u32 packet_length:17;
382 u32 error_code:15;
383
384 u8 bypass_length:4;
385 u8 e15:1;
386 u16 rsvd0;
387 u8 hash_bytes:1;
388 u8 hash_length:6;
389 u8 generic_bytes:1;
390 u8 checksum:1;
391 u8 next_header:1;
392 u8 length:1;
393
394 u16 application_id;
395 u16 rsvd1;
396
397 u32 rsvd2;
398} __packed;
399
400
401
402struct safexcel_result_desc {
403 u32 particle_size:17;
404 u8 rsvd0:3;
405 u8 descriptor_overflow:1;
406 u8 buffer_overflow:1;
407 u8 last_seg:1;
408 u8 first_seg:1;
409 u16 result_size:8;
410
411 u32 rsvd1;
412
413 u32 data_lo;
414 u32 data_hi;
415
416 struct result_data_desc result_data;
417} __packed;
418
419struct safexcel_token {
420 u32 packet_length:17;
421 u8 stat:2;
422 u16 instructions:9;
423 u8 opcode:4;
424} __packed;
425
426#define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
427
428#define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
429#define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
430#define EIP197_TOKEN_OPCODE_DIRECTION 0x0
431#define EIP197_TOKEN_OPCODE_INSERT 0x2
432#define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
433#define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
434#define EIP197_TOKEN_OPCODE_VERIFY 0xd
435#define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
436
437static inline void eip197_noop_token(struct safexcel_token *token)
438{
439 token->opcode = EIP197_TOKEN_OPCODE_NOOP;
440 token->packet_length = BIT(2);
441}
442
443
444#define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
445#define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
446#define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
447#define EIP197_TOKEN_INS_TYPE_CRYTO BIT(7)
448#define EIP197_TOKEN_INS_LAST BIT(8)
449
450
451struct safexcel_control_data_desc {
452 u32 packet_length:17;
453 u16 options:13;
454 u8 type:2;
455
456 u16 application_id;
457 u16 rsvd;
458
459 u8 refresh:2;
460 u32 context_lo:30;
461 u32 context_hi;
462
463 u32 control0;
464 u32 control1;
465
466 u32 token[EIP197_MAX_TOKENS];
467} __packed;
468
469#define EIP197_OPTION_MAGIC_VALUE BIT(0)
470#define EIP197_OPTION_64BIT_CTX BIT(1)
471#define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
472#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
473#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
474
475#define EIP197_TYPE_EXTENDED 0x3
476
477
478struct safexcel_command_desc {
479 u32 particle_size:17;
480 u8 rsvd0:5;
481 u8 last_seg:1;
482 u8 first_seg:1;
483 u16 additional_cdata_size:8;
484
485 u32 rsvd1;
486
487 u32 data_lo;
488 u32 data_hi;
489
490 struct safexcel_control_data_desc control_data;
491} __packed;
492
493
494
495
496
497enum eip197_fw {
498 FW_IFPP = 0,
499 FW_IPUE,
500 FW_NB
501};
502
503struct safexcel_desc_ring {
504 void *base;
505 void *base_end;
506 dma_addr_t base_dma;
507
508
509 void *write;
510 void *read;
511
512
513 unsigned offset;
514};
515
516enum safexcel_alg_type {
517 SAFEXCEL_ALG_TYPE_SKCIPHER,
518 SAFEXCEL_ALG_TYPE_AEAD,
519 SAFEXCEL_ALG_TYPE_AHASH,
520};
521
522struct safexcel_config {
523 u32 pes;
524 u32 rings;
525
526 u32 cd_size;
527 u32 cd_offset;
528
529 u32 rd_size;
530 u32 rd_offset;
531};
532
533struct safexcel_work_data {
534 struct work_struct work;
535 struct safexcel_crypto_priv *priv;
536 int ring;
537};
538
539struct safexcel_ring {
540 spinlock_t lock;
541
542 struct workqueue_struct *workqueue;
543 struct safexcel_work_data work_data;
544
545
546 struct safexcel_desc_ring cdr;
547 struct safexcel_desc_ring rdr;
548
549
550 struct crypto_async_request **rdr_req;
551
552
553 struct crypto_queue queue;
554 spinlock_t queue_lock;
555
556
557 int requests;
558
559
560 bool busy;
561
562
563
564
565 struct crypto_async_request *req;
566 struct crypto_async_request *backlog;
567};
568
569enum safexcel_eip_version {
570 EIP97IES = BIT(0),
571 EIP197B = BIT(1),
572 EIP197D = BIT(2),
573};
574
575struct safexcel_register_offsets {
576 u32 hia_aic;
577 u32 hia_aic_g;
578 u32 hia_aic_r;
579 u32 hia_aic_xdr;
580 u32 hia_dfe;
581 u32 hia_dfe_thr;
582 u32 hia_dse;
583 u32 hia_dse_thr;
584 u32 hia_gen_cfg;
585 u32 pe;
586};
587
588enum safexcel_flags {
589 EIP197_TRC_CACHE = BIT(0),
590};
591
592struct safexcel_crypto_priv {
593 void __iomem *base;
594 struct device *dev;
595 struct clk *clk;
596 struct clk *reg_clk;
597 struct safexcel_config config;
598
599 enum safexcel_eip_version version;
600 struct safexcel_register_offsets offsets;
601 u32 flags;
602
603
604 struct dma_pool *context_pool;
605
606 atomic_t ring_used;
607
608 struct safexcel_ring *ring;
609};
610
611struct safexcel_context {
612 int (*send)(struct crypto_async_request *req, int ring,
613 int *commands, int *results);
614 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
615 struct crypto_async_request *req, bool *complete,
616 int *ret);
617 struct safexcel_context_record *ctxr;
618 dma_addr_t ctxr_dma;
619
620 int ring;
621 bool needs_inv;
622 bool exit_inv;
623};
624
625struct safexcel_ahash_export_state {
626 u64 len[2];
627 u64 processed[2];
628
629 u32 digest;
630
631 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
632 u8 cache[SHA512_BLOCK_SIZE];
633};
634
635
636
637
638
639
640struct safexcel_alg_template {
641 struct safexcel_crypto_priv *priv;
642 enum safexcel_alg_type type;
643 u32 engines;
644 union {
645 struct skcipher_alg skcipher;
646 struct aead_alg aead;
647 struct ahash_alg ahash;
648 } alg;
649};
650
651struct safexcel_inv_result {
652 struct completion completion;
653 int error;
654};
655
656void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
657int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
658 struct safexcel_result_desc *rdesc);
659void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
660int safexcel_invalidate_cache(struct crypto_async_request *async,
661 struct safexcel_crypto_priv *priv,
662 dma_addr_t ctxr_dma, int ring);
663int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
664 struct safexcel_desc_ring *cdr,
665 struct safexcel_desc_ring *rdr);
666int safexcel_select_ring(struct safexcel_crypto_priv *priv);
667void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
668 struct safexcel_desc_ring *ring);
669void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
670void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
671 struct safexcel_desc_ring *ring);
672struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
673 int ring_id,
674 bool first, bool last,
675 dma_addr_t data, u32 len,
676 u32 full_data_len,
677 dma_addr_t context);
678struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
679 int ring_id,
680 bool first, bool last,
681 dma_addr_t data, u32 len);
682int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
683 int ring);
684int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
685 int ring,
686 struct safexcel_result_desc *rdesc);
687void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
688 int ring,
689 struct safexcel_result_desc *rdesc,
690 struct crypto_async_request *req);
691inline struct crypto_async_request *
692safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
693void safexcel_inv_complete(struct crypto_async_request *req, int error);
694int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen,
695 void *istate, void *ostate);
696
697
698extern struct safexcel_alg_template safexcel_alg_ecb_des;
699extern struct safexcel_alg_template safexcel_alg_cbc_des;
700extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
701extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
702extern struct safexcel_alg_template safexcel_alg_ecb_aes;
703extern struct safexcel_alg_template safexcel_alg_cbc_aes;
704extern struct safexcel_alg_template safexcel_alg_md5;
705extern struct safexcel_alg_template safexcel_alg_sha1;
706extern struct safexcel_alg_template safexcel_alg_sha224;
707extern struct safexcel_alg_template safexcel_alg_sha256;
708extern struct safexcel_alg_template safexcel_alg_sha384;
709extern struct safexcel_alg_template safexcel_alg_sha512;
710extern struct safexcel_alg_template safexcel_alg_hmac_md5;
711extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
712extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
713extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
714extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
715extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
716extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
717extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
718extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
719extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
720extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
721
722#endif
723