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17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/gpio/driver.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24
25#define IOH_EDGE_FALLING 0
26#define IOH_EDGE_RISING BIT(0)
27#define IOH_LEVEL_L BIT(1)
28#define IOH_LEVEL_H (BIT(0) | BIT(1))
29#define IOH_EDGE_BOTH BIT(2)
30#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define IOH_IRQ_BASE 0
33
34#define PCI_VENDOR_ID_ROHM 0x10DB
35
36struct ioh_reg_comn {
37 u32 ien;
38 u32 istatus;
39 u32 idisp;
40 u32 iclr;
41 u32 imask;
42 u32 imaskclr;
43 u32 po;
44 u32 pi;
45 u32 pm;
46 u32 im_0;
47 u32 im_1;
48 u32 reserved;
49};
50
51struct ioh_regs {
52 struct ioh_reg_comn regs[8];
53 u32 reserve1[16];
54 u32 ioh_sel_reg[4];
55 u32 reserve2[11];
56 u32 srst;
57};
58
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67
68
69struct ioh_gpio_reg_data {
70 u32 ien_reg;
71 u32 imask_reg;
72 u32 po_reg;
73 u32 pm_reg;
74 u32 im0_reg;
75 u32 im1_reg;
76 u32 use_sel_reg;
77};
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91
92struct ioh_gpio {
93 void __iomem *base;
94 struct ioh_regs __iomem *reg;
95 struct device *dev;
96 struct gpio_chip gpio;
97 struct ioh_gpio_reg_data ioh_gpio_reg;
98 u32 gpio_use_sel;
99 int ch;
100 int irq_base;
101 spinlock_t spinlock;
102};
103
104static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
105
106static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
107{
108 u32 reg_val;
109 struct ioh_gpio *chip = gpiochip_get_data(gpio);
110 unsigned long flags;
111
112 spin_lock_irqsave(&chip->spinlock, flags);
113 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
114 if (val)
115 reg_val |= (1 << nr);
116 else
117 reg_val &= ~(1 << nr);
118
119 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
120 spin_unlock_irqrestore(&chip->spinlock, flags);
121}
122
123static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
124{
125 struct ioh_gpio *chip = gpiochip_get_data(gpio);
126
127 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
128}
129
130static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
131 int val)
132{
133 struct ioh_gpio *chip = gpiochip_get_data(gpio);
134 u32 pm;
135 u32 reg_val;
136 unsigned long flags;
137
138 spin_lock_irqsave(&chip->spinlock, flags);
139 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
140 ((1 << num_ports[chip->ch]) - 1);
141 pm |= (1 << nr);
142 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
143
144 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
145 if (val)
146 reg_val |= (1 << nr);
147 else
148 reg_val &= ~(1 << nr);
149 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
150
151 spin_unlock_irqrestore(&chip->spinlock, flags);
152
153 return 0;
154}
155
156static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
157{
158 struct ioh_gpio *chip = gpiochip_get_data(gpio);
159 u32 pm;
160 unsigned long flags;
161
162 spin_lock_irqsave(&chip->spinlock, flags);
163 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
164 ((1 << num_ports[chip->ch]) - 1);
165 pm &= ~(1 << nr);
166 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
167 spin_unlock_irqrestore(&chip->spinlock, flags);
168
169 return 0;
170}
171
172#ifdef CONFIG_PM
173
174
175
176static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
177{
178 int i;
179
180 for (i = 0; i < 8; i ++, chip++) {
181 chip->ioh_gpio_reg.po_reg =
182 ioread32(&chip->reg->regs[chip->ch].po);
183 chip->ioh_gpio_reg.pm_reg =
184 ioread32(&chip->reg->regs[chip->ch].pm);
185 chip->ioh_gpio_reg.ien_reg =
186 ioread32(&chip->reg->regs[chip->ch].ien);
187 chip->ioh_gpio_reg.imask_reg =
188 ioread32(&chip->reg->regs[chip->ch].imask);
189 chip->ioh_gpio_reg.im0_reg =
190 ioread32(&chip->reg->regs[chip->ch].im_0);
191 chip->ioh_gpio_reg.im1_reg =
192 ioread32(&chip->reg->regs[chip->ch].im_1);
193 if (i < 4)
194 chip->ioh_gpio_reg.use_sel_reg =
195 ioread32(&chip->reg->ioh_sel_reg[i]);
196 }
197}
198
199
200
201
202static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
203{
204 int i;
205
206 for (i = 0; i < 8; i ++, chip++) {
207 iowrite32(chip->ioh_gpio_reg.po_reg,
208 &chip->reg->regs[chip->ch].po);
209 iowrite32(chip->ioh_gpio_reg.pm_reg,
210 &chip->reg->regs[chip->ch].pm);
211 iowrite32(chip->ioh_gpio_reg.ien_reg,
212 &chip->reg->regs[chip->ch].ien);
213 iowrite32(chip->ioh_gpio_reg.imask_reg,
214 &chip->reg->regs[chip->ch].imask);
215 iowrite32(chip->ioh_gpio_reg.im0_reg,
216 &chip->reg->regs[chip->ch].im_0);
217 iowrite32(chip->ioh_gpio_reg.im1_reg,
218 &chip->reg->regs[chip->ch].im_1);
219 if (i < 4)
220 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
221 &chip->reg->ioh_sel_reg[i]);
222 }
223}
224#endif
225
226static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
227{
228 struct ioh_gpio *chip = gpiochip_get_data(gpio);
229 return chip->irq_base + offset;
230}
231
232static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
233{
234 struct gpio_chip *gpio = &chip->gpio;
235
236 gpio->label = dev_name(chip->dev);
237 gpio->owner = THIS_MODULE;
238 gpio->direction_input = ioh_gpio_direction_input;
239 gpio->get = ioh_gpio_get;
240 gpio->direction_output = ioh_gpio_direction_output;
241 gpio->set = ioh_gpio_set;
242 gpio->dbg_show = NULL;
243 gpio->base = -1;
244 gpio->ngpio = num_port;
245 gpio->can_sleep = false;
246 gpio->to_irq = ioh_gpio_to_irq;
247}
248
249static int ioh_irq_type(struct irq_data *d, unsigned int type)
250{
251 u32 im;
252 void __iomem *im_reg;
253 u32 ien;
254 u32 im_pos;
255 int ch;
256 unsigned long flags;
257 u32 val;
258 int irq = d->irq;
259 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
260 struct ioh_gpio *chip = gc->private;
261
262 ch = irq - chip->irq_base;
263 if (irq <= chip->irq_base + 7) {
264 im_reg = &chip->reg->regs[chip->ch].im_0;
265 im_pos = ch;
266 } else {
267 im_reg = &chip->reg->regs[chip->ch].im_1;
268 im_pos = ch - 8;
269 }
270 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
271 __func__, irq, type, ch, im_pos, type);
272
273 spin_lock_irqsave(&chip->spinlock, flags);
274
275 switch (type) {
276 case IRQ_TYPE_EDGE_RISING:
277 val = IOH_EDGE_RISING;
278 break;
279 case IRQ_TYPE_EDGE_FALLING:
280 val = IOH_EDGE_FALLING;
281 break;
282 case IRQ_TYPE_EDGE_BOTH:
283 val = IOH_EDGE_BOTH;
284 break;
285 case IRQ_TYPE_LEVEL_HIGH:
286 val = IOH_LEVEL_H;
287 break;
288 case IRQ_TYPE_LEVEL_LOW:
289 val = IOH_LEVEL_L;
290 break;
291 case IRQ_TYPE_PROBE:
292 goto end;
293 default:
294 dev_warn(chip->dev, "%s: unknown type(%dd)",
295 __func__, type);
296 goto end;
297 }
298
299
300 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
301 iowrite32(im | (val << (im_pos * 4)), im_reg);
302
303
304 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
305
306
307 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
308
309
310 ien = ioread32(&chip->reg->regs[chip->ch].ien);
311 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
312end:
313 spin_unlock_irqrestore(&chip->spinlock, flags);
314
315 return 0;
316}
317
318static void ioh_irq_unmask(struct irq_data *d)
319{
320 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
321 struct ioh_gpio *chip = gc->private;
322
323 iowrite32(1 << (d->irq - chip->irq_base),
324 &chip->reg->regs[chip->ch].imaskclr);
325}
326
327static void ioh_irq_mask(struct irq_data *d)
328{
329 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
330 struct ioh_gpio *chip = gc->private;
331
332 iowrite32(1 << (d->irq - chip->irq_base),
333 &chip->reg->regs[chip->ch].imask);
334}
335
336static void ioh_irq_disable(struct irq_data *d)
337{
338 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
339 struct ioh_gpio *chip = gc->private;
340 unsigned long flags;
341 u32 ien;
342
343 spin_lock_irqsave(&chip->spinlock, flags);
344 ien = ioread32(&chip->reg->regs[chip->ch].ien);
345 ien &= ~(1 << (d->irq - chip->irq_base));
346 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
347 spin_unlock_irqrestore(&chip->spinlock, flags);
348}
349
350static void ioh_irq_enable(struct irq_data *d)
351{
352 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
353 struct ioh_gpio *chip = gc->private;
354 unsigned long flags;
355 u32 ien;
356
357 spin_lock_irqsave(&chip->spinlock, flags);
358 ien = ioread32(&chip->reg->regs[chip->ch].ien);
359 ien |= 1 << (d->irq - chip->irq_base);
360 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
361 spin_unlock_irqrestore(&chip->spinlock, flags);
362}
363
364static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
365{
366 struct ioh_gpio *chip = dev_id;
367 u32 reg_val;
368 int i, j;
369 int ret = IRQ_NONE;
370
371 for (i = 0; i < 8; i++, chip++) {
372 reg_val = ioread32(&chip->reg->regs[i].istatus);
373 for (j = 0; j < num_ports[i]; j++) {
374 if (reg_val & BIT(j)) {
375 dev_dbg(chip->dev,
376 "%s:[%d]:irq=%d status=0x%x\n",
377 __func__, j, irq, reg_val);
378 iowrite32(BIT(j),
379 &chip->reg->regs[chip->ch].iclr);
380 generic_handle_irq(chip->irq_base + j);
381 ret = IRQ_HANDLED;
382 }
383 }
384 }
385 return ret;
386}
387
388static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
389 unsigned int irq_start,
390 unsigned int num)
391{
392 struct irq_chip_generic *gc;
393 struct irq_chip_type *ct;
394 int rv;
395
396 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
397 chip->base, handle_simple_irq);
398 if (!gc)
399 return -ENOMEM;
400
401 gc->private = chip;
402 ct = gc->chip_types;
403
404 ct->chip.irq_mask = ioh_irq_mask;
405 ct->chip.irq_unmask = ioh_irq_unmask;
406 ct->chip.irq_set_type = ioh_irq_type;
407 ct->chip.irq_disable = ioh_irq_disable;
408 ct->chip.irq_enable = ioh_irq_enable;
409
410 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
411 IRQ_GC_INIT_MASK_CACHE,
412 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
413
414 return rv;
415}
416
417static int ioh_gpio_probe(struct pci_dev *pdev,
418 const struct pci_device_id *id)
419{
420 int ret;
421 int i, j;
422 struct ioh_gpio *chip;
423 void __iomem *base;
424 void *chip_save;
425 int irq_base;
426
427 ret = pci_enable_device(pdev);
428 if (ret) {
429 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
430 goto err_pci_enable;
431 }
432
433 ret = pci_request_regions(pdev, KBUILD_MODNAME);
434 if (ret) {
435 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
436 goto err_request_regions;
437 }
438
439 base = pci_iomap(pdev, 1, 0);
440 if (!base) {
441 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
442 ret = -ENOMEM;
443 goto err_iomap;
444 }
445
446 chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
447 if (chip_save == NULL) {
448 ret = -ENOMEM;
449 goto err_kzalloc;
450 }
451
452 chip = chip_save;
453 for (i = 0; i < 8; i++, chip++) {
454 chip->dev = &pdev->dev;
455 chip->base = base;
456 chip->reg = chip->base;
457 chip->ch = i;
458 spin_lock_init(&chip->spinlock);
459 ioh_gpio_setup(chip, num_ports[i]);
460 ret = gpiochip_add_data(&chip->gpio, chip);
461 if (ret) {
462 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
463 goto err_gpiochip_add;
464 }
465 }
466
467 chip = chip_save;
468 for (j = 0; j < 8; j++, chip++) {
469 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
470 num_ports[j], NUMA_NO_NODE);
471 if (irq_base < 0) {
472 dev_warn(&pdev->dev,
473 "ml_ioh_gpio: Failed to get IRQ base num\n");
474 ret = irq_base;
475 goto err_gpiochip_add;
476 }
477 chip->irq_base = irq_base;
478
479 ret = ioh_gpio_alloc_generic_chip(chip,
480 irq_base, num_ports[j]);
481 if (ret)
482 goto err_gpiochip_add;
483 }
484
485 chip = chip_save;
486 ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
487 IRQF_SHARED, KBUILD_MODNAME, chip);
488 if (ret != 0) {
489 dev_err(&pdev->dev,
490 "%s request_irq failed\n", __func__);
491 goto err_gpiochip_add;
492 }
493
494 pci_set_drvdata(pdev, chip);
495
496 return 0;
497
498err_gpiochip_add:
499 chip = chip_save;
500 while (--i >= 0) {
501 gpiochip_remove(&chip->gpio);
502 chip++;
503 }
504 kfree(chip_save);
505
506err_kzalloc:
507 pci_iounmap(pdev, base);
508
509err_iomap:
510 pci_release_regions(pdev);
511
512err_request_regions:
513 pci_disable_device(pdev);
514
515err_pci_enable:
516
517 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
518 return ret;
519}
520
521static void ioh_gpio_remove(struct pci_dev *pdev)
522{
523 int i;
524 struct ioh_gpio *chip = pci_get_drvdata(pdev);
525 void *chip_save;
526
527 chip_save = chip;
528
529 for (i = 0; i < 8; i++, chip++)
530 gpiochip_remove(&chip->gpio);
531
532 chip = chip_save;
533 pci_iounmap(pdev, chip->base);
534 pci_release_regions(pdev);
535 pci_disable_device(pdev);
536 kfree(chip);
537}
538
539#ifdef CONFIG_PM
540static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
541{
542 s32 ret;
543 struct ioh_gpio *chip = pci_get_drvdata(pdev);
544 unsigned long flags;
545
546 spin_lock_irqsave(&chip->spinlock, flags);
547 ioh_gpio_save_reg_conf(chip);
548 spin_unlock_irqrestore(&chip->spinlock, flags);
549
550 ret = pci_save_state(pdev);
551 if (ret) {
552 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
553 return ret;
554 }
555 pci_disable_device(pdev);
556 pci_set_power_state(pdev, PCI_D0);
557 ret = pci_enable_wake(pdev, PCI_D0, 1);
558 if (ret)
559 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
560
561 return 0;
562}
563
564static int ioh_gpio_resume(struct pci_dev *pdev)
565{
566 s32 ret;
567 struct ioh_gpio *chip = pci_get_drvdata(pdev);
568 unsigned long flags;
569
570 ret = pci_enable_wake(pdev, PCI_D0, 0);
571
572 pci_set_power_state(pdev, PCI_D0);
573 ret = pci_enable_device(pdev);
574 if (ret) {
575 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
576 return ret;
577 }
578 pci_restore_state(pdev);
579
580 spin_lock_irqsave(&chip->spinlock, flags);
581 iowrite32(0x01, &chip->reg->srst);
582 iowrite32(0x00, &chip->reg->srst);
583 ioh_gpio_restore_reg_conf(chip);
584 spin_unlock_irqrestore(&chip->spinlock, flags);
585
586 return 0;
587}
588#else
589#define ioh_gpio_suspend NULL
590#define ioh_gpio_resume NULL
591#endif
592
593static const struct pci_device_id ioh_gpio_pcidev_id[] = {
594 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
595 { 0, }
596};
597MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
598
599static struct pci_driver ioh_gpio_driver = {
600 .name = "ml_ioh_gpio",
601 .id_table = ioh_gpio_pcidev_id,
602 .probe = ioh_gpio_probe,
603 .remove = ioh_gpio_remove,
604 .suspend = ioh_gpio_suspend,
605 .resume = ioh_gpio_resume
606};
607
608module_pci_driver(ioh_gpio_driver);
609
610MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
611MODULE_LICENSE("GPL");
612
