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17#include <linux/err.h>
18#include <linux/gpio/driver.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/spinlock.h>
31#include <linux/slab.h>
32
33struct gpio_rcar_bank_info {
34 u32 iointsel;
35 u32 inoutsel;
36 u32 outdt;
37 u32 posneg;
38 u32 edglevel;
39 u32 bothedge;
40 u32 intmsk;
41};
42
43struct gpio_rcar_priv {
44 void __iomem *base;
45 spinlock_t lock;
46 struct platform_device *pdev;
47 struct gpio_chip gpio_chip;
48 struct irq_chip irq_chip;
49 unsigned int irq_parent;
50 atomic_t wakeup_path;
51 bool has_both_edge_trigger;
52 struct gpio_rcar_bank_info bank_info;
53};
54
55#define IOINTSEL 0x00
56#define INOUTSEL 0x04
57#define OUTDT 0x08
58#define INDT 0x0c
59#define INTDT 0x10
60#define INTCLR 0x14
61#define INTMSK 0x18
62#define MSKCLR 0x1c
63#define POSNEG 0x20
64#define EDGLEVEL 0x24
65#define FILONOFF 0x28
66#define BOTHEDGE 0x4c
67
68#define RCAR_MAX_GPIO_PER_BANK 32
69
70static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
71{
72 return ioread32(p->base + offs);
73}
74
75static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
76 u32 value)
77{
78 iowrite32(value, p->base + offs);
79}
80
81static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
82 int bit, bool value)
83{
84 u32 tmp = gpio_rcar_read(p, offs);
85
86 if (value)
87 tmp |= BIT(bit);
88 else
89 tmp &= ~BIT(bit);
90
91 gpio_rcar_write(p, offs, tmp);
92}
93
94static void gpio_rcar_irq_disable(struct irq_data *d)
95{
96 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
97 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
98
99 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
100}
101
102static void gpio_rcar_irq_enable(struct irq_data *d)
103{
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
106
107 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
108}
109
110static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
111 unsigned int hwirq,
112 bool active_high_rising_edge,
113 bool level_trigger,
114 bool both)
115{
116 unsigned long flags;
117
118
119
120
121
122
123 spin_lock_irqsave(&p->lock, flags);
124
125
126 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
127
128
129 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
130
131
132 if (p->has_both_edge_trigger)
133 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
134
135
136 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
137
138
139 if (!level_trigger)
140 gpio_rcar_write(p, INTCLR, BIT(hwirq));
141
142 spin_unlock_irqrestore(&p->lock, flags);
143}
144
145static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
146{
147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
148 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
149 unsigned int hwirq = irqd_to_hwirq(d);
150
151 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
152
153 switch (type & IRQ_TYPE_SENSE_MASK) {
154 case IRQ_TYPE_LEVEL_HIGH:
155 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
156 false);
157 break;
158 case IRQ_TYPE_LEVEL_LOW:
159 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
160 false);
161 break;
162 case IRQ_TYPE_EDGE_RISING:
163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 false);
165 break;
166 case IRQ_TYPE_EDGE_FALLING:
167 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
168 false);
169 break;
170 case IRQ_TYPE_EDGE_BOTH:
171 if (!p->has_both_edge_trigger)
172 return -EINVAL;
173 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
174 true);
175 break;
176 default:
177 return -EINVAL;
178 }
179 return 0;
180}
181
182static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
183{
184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
185 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
186 int error;
187
188 if (p->irq_parent) {
189 error = irq_set_irq_wake(p->irq_parent, on);
190 if (error) {
191 dev_dbg(&p->pdev->dev,
192 "irq %u doesn't support irq_set_wake\n",
193 p->irq_parent);
194 p->irq_parent = 0;
195 }
196 }
197
198 if (on)
199 atomic_inc(&p->wakeup_path);
200 else
201 atomic_dec(&p->wakeup_path);
202
203 return 0;
204}
205
206static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
207{
208 struct gpio_rcar_priv *p = dev_id;
209 u32 pending;
210 unsigned int offset, irqs_handled = 0;
211
212 while ((pending = gpio_rcar_read(p, INTDT) &
213 gpio_rcar_read(p, INTMSK))) {
214 offset = __ffs(pending);
215 gpio_rcar_write(p, INTCLR, BIT(offset));
216 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
217 offset));
218 irqs_handled++;
219 }
220
221 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
222}
223
224static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
225 unsigned int gpio,
226 bool output)
227{
228 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
229 unsigned long flags;
230
231
232
233
234
235
236 spin_lock_irqsave(&p->lock, flags);
237
238
239 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
240
241
242 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
243
244
245 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
246
247 spin_unlock_irqrestore(&p->lock, flags);
248}
249
250static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
251{
252 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
253 int error;
254
255 error = pm_runtime_get_sync(&p->pdev->dev);
256 if (error < 0)
257 return error;
258
259 error = pinctrl_gpio_request(chip->base + offset);
260 if (error)
261 pm_runtime_put(&p->pdev->dev);
262
263 return error;
264}
265
266static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
267{
268 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
269
270 pinctrl_gpio_free(chip->base + offset);
271
272
273
274
275
276 gpio_rcar_config_general_input_output_mode(chip, offset, false);
277
278 pm_runtime_put(&p->pdev->dev);
279}
280
281static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
282{
283 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
284
285 return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
286}
287
288static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
289{
290 gpio_rcar_config_general_input_output_mode(chip, offset, false);
291 return 0;
292}
293
294static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
295{
296 u32 bit = BIT(offset);
297
298
299
300 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
301 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
302 else
303 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
304}
305
306static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
307{
308 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
309 unsigned long flags;
310
311 spin_lock_irqsave(&p->lock, flags);
312 gpio_rcar_modify_bit(p, OUTDT, offset, value);
313 spin_unlock_irqrestore(&p->lock, flags);
314}
315
316static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
317 unsigned long *bits)
318{
319 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
320 unsigned long flags;
321 u32 val, bankmask;
322
323 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
324 if (!bankmask)
325 return;
326
327 spin_lock_irqsave(&p->lock, flags);
328 val = gpio_rcar_read(p, OUTDT);
329 val &= ~bankmask;
330 val |= (bankmask & bits[0]);
331 gpio_rcar_write(p, OUTDT, val);
332 spin_unlock_irqrestore(&p->lock, flags);
333}
334
335static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
336 int value)
337{
338
339 gpio_rcar_set(chip, offset, value);
340 gpio_rcar_config_general_input_output_mode(chip, offset, true);
341 return 0;
342}
343
344struct gpio_rcar_info {
345 bool has_both_edge_trigger;
346};
347
348static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
349 .has_both_edge_trigger = false,
350};
351
352static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
353 .has_both_edge_trigger = true,
354};
355
356static const struct of_device_id gpio_rcar_of_table[] = {
357 {
358 .compatible = "renesas,gpio-r8a7743",
359
360 .data = &gpio_rcar_info_gen2,
361 }, {
362 .compatible = "renesas,gpio-r8a7790",
363 .data = &gpio_rcar_info_gen2,
364 }, {
365 .compatible = "renesas,gpio-r8a7791",
366 .data = &gpio_rcar_info_gen2,
367 }, {
368 .compatible = "renesas,gpio-r8a7792",
369 .data = &gpio_rcar_info_gen2,
370 }, {
371 .compatible = "renesas,gpio-r8a7793",
372 .data = &gpio_rcar_info_gen2,
373 }, {
374 .compatible = "renesas,gpio-r8a7794",
375 .data = &gpio_rcar_info_gen2,
376 }, {
377 .compatible = "renesas,gpio-r8a7795",
378
379 .data = &gpio_rcar_info_gen2,
380 }, {
381 .compatible = "renesas,gpio-r8a7796",
382
383 .data = &gpio_rcar_info_gen2,
384 }, {
385 .compatible = "renesas,rcar-gen1-gpio",
386 .data = &gpio_rcar_info_gen1,
387 }, {
388 .compatible = "renesas,rcar-gen2-gpio",
389 .data = &gpio_rcar_info_gen2,
390 }, {
391 .compatible = "renesas,rcar-gen3-gpio",
392
393 .data = &gpio_rcar_info_gen2,
394 }, {
395 .compatible = "renesas,gpio-rcar",
396 .data = &gpio_rcar_info_gen1,
397 }, {
398
399 },
400};
401
402MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
403
404static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
405{
406 struct device_node *np = p->pdev->dev.of_node;
407 const struct gpio_rcar_info *info;
408 struct of_phandle_args args;
409 int ret;
410
411 info = of_device_get_match_data(&p->pdev->dev);
412
413 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
414 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
415 p->has_both_edge_trigger = info->has_both_edge_trigger;
416
417 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
418 dev_warn(&p->pdev->dev,
419 "Invalid number of gpio lines %u, using %u\n", *npins,
420 RCAR_MAX_GPIO_PER_BANK);
421 *npins = RCAR_MAX_GPIO_PER_BANK;
422 }
423
424 return 0;
425}
426
427static int gpio_rcar_probe(struct platform_device *pdev)
428{
429 struct gpio_rcar_priv *p;
430 struct resource *io, *irq;
431 struct gpio_chip *gpio_chip;
432 struct irq_chip *irq_chip;
433 struct device *dev = &pdev->dev;
434 const char *name = dev_name(dev);
435 unsigned int npins;
436 int ret;
437
438 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
439 if (!p)
440 return -ENOMEM;
441
442 p->pdev = pdev;
443 spin_lock_init(&p->lock);
444
445
446 ret = gpio_rcar_parse_dt(p, &npins);
447 if (ret < 0)
448 return ret;
449
450 platform_set_drvdata(pdev, p);
451
452 pm_runtime_enable(dev);
453
454 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
455 if (!irq) {
456 dev_err(dev, "missing IRQ\n");
457 ret = -EINVAL;
458 goto err0;
459 }
460
461 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
462 p->base = devm_ioremap_resource(dev, io);
463 if (IS_ERR(p->base)) {
464 ret = PTR_ERR(p->base);
465 goto err0;
466 }
467
468 gpio_chip = &p->gpio_chip;
469 gpio_chip->request = gpio_rcar_request;
470 gpio_chip->free = gpio_rcar_free;
471 gpio_chip->get_direction = gpio_rcar_get_direction;
472 gpio_chip->direction_input = gpio_rcar_direction_input;
473 gpio_chip->get = gpio_rcar_get;
474 gpio_chip->direction_output = gpio_rcar_direction_output;
475 gpio_chip->set = gpio_rcar_set;
476 gpio_chip->set_multiple = gpio_rcar_set_multiple;
477 gpio_chip->label = name;
478 gpio_chip->parent = dev;
479 gpio_chip->owner = THIS_MODULE;
480 gpio_chip->base = -1;
481 gpio_chip->ngpio = npins;
482
483 irq_chip = &p->irq_chip;
484 irq_chip->name = name;
485 irq_chip->parent_device = dev;
486 irq_chip->irq_mask = gpio_rcar_irq_disable;
487 irq_chip->irq_unmask = gpio_rcar_irq_enable;
488 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
489 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
490 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
491
492 ret = gpiochip_add_data(gpio_chip, p);
493 if (ret) {
494 dev_err(dev, "failed to add GPIO controller\n");
495 goto err0;
496 }
497
498 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
499 IRQ_TYPE_NONE);
500 if (ret) {
501 dev_err(dev, "cannot add irqchip\n");
502 goto err1;
503 }
504
505 p->irq_parent = irq->start;
506 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
507 IRQF_SHARED, name, p)) {
508 dev_err(dev, "failed to request IRQ\n");
509 ret = -ENOENT;
510 goto err1;
511 }
512
513 dev_info(dev, "driving %d GPIOs\n", npins);
514
515 return 0;
516
517err1:
518 gpiochip_remove(gpio_chip);
519err0:
520 pm_runtime_disable(dev);
521 return ret;
522}
523
524static int gpio_rcar_remove(struct platform_device *pdev)
525{
526 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
527
528 gpiochip_remove(&p->gpio_chip);
529
530 pm_runtime_disable(&pdev->dev);
531 return 0;
532}
533
534#ifdef CONFIG_PM_SLEEP
535static int gpio_rcar_suspend(struct device *dev)
536{
537 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
538
539 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
540 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
541 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
542 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
543 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
544 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
545 if (p->has_both_edge_trigger)
546 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
547
548 if (atomic_read(&p->wakeup_path))
549 device_set_wakeup_path(dev);
550
551 return 0;
552}
553
554static int gpio_rcar_resume(struct device *dev)
555{
556 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
557 unsigned int offset;
558 u32 mask;
559
560 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
561 mask = BIT(offset);
562
563 if (!(p->bank_info.iointsel & mask)) {
564 if (p->bank_info.inoutsel & mask)
565 gpio_rcar_direction_output(
566 &p->gpio_chip, offset,
567 !!(p->bank_info.outdt & mask));
568 else
569 gpio_rcar_direction_input(&p->gpio_chip,
570 offset);
571 } else {
572
573 gpio_rcar_config_interrupt_input_mode(
574 p,
575 offset,
576 !(p->bank_info.posneg & mask),
577 !(p->bank_info.edglevel & mask),
578 !!(p->bank_info.bothedge & mask));
579
580 if (p->bank_info.intmsk & mask)
581 gpio_rcar_write(p, MSKCLR, mask);
582 }
583 }
584
585 return 0;
586}
587#endif
588
589static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
590
591static struct platform_driver gpio_rcar_device_driver = {
592 .probe = gpio_rcar_probe,
593 .remove = gpio_rcar_remove,
594 .driver = {
595 .name = "gpio_rcar",
596 .pm = &gpio_rcar_pm_ops,
597 .of_match_table = of_match_ptr(gpio_rcar_of_table),
598 }
599};
600
601module_platform_driver(gpio_rcar_device_driver);
602
603MODULE_AUTHOR("Magnus Damm");
604MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
605MODULE_LICENSE("GPL v2");
606