LXR linux/drivers/gpu/drm/msm/adreno/a6xx

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
   3
   4#ifndef _A6XX_GMU_H_
   5#define _A6XX_GMU_H_
   6
   7#include <linux/interrupt.h>
   8#include "msm_drv.h"
   9#include "a6xx_hfi.h"
  10
  11struct a6xx_gmu_bo {
  12        void *virt;
  13        size_t size;
  14        u64 iova;
  15        struct page **pages;
  16};
  17
  18/*
  19 * These define the different GMU wake up options - these define how both the
  20 * CPU and the GMU bring up the hardware
  21 */
  22
  23/* THe GMU has already been booted and the rentention registers are active */
  24#define GMU_WARM_BOOT 0
  25
  26/* the GMU is coming up for the first time or back from a power collapse */
  27#define GMU_COLD_BOOT 1
  28
  29/* The GMU is being soft reset after a fault */
  30#define GMU_RESET 2
  31
  32/*
  33 * These define the level of control that the GMU has - the higher the number
  34 * the more things that the GMU hardware controls on its own.
  35 */
  36
  37/* The GMU does not do any idle state management */
  38#define GMU_IDLE_STATE_ACTIVE 0
  39
  40/* The GMU manages SPTP power collapse */
  41#define GMU_IDLE_STATE_SPTP 2
  42
  43/* The GMU does automatic IFPC (intra-frame power collapse) */
  44#define GMU_IDLE_STATE_IFPC 3
  45
  46struct a6xx_gmu {
  47        struct device *dev;
  48
  49        void * __iomem mmio;
  50        void * __iomem pdc_mmio;
  51
  52        int hfi_irq;
  53        int gmu_irq;
  54
  55        struct regulator *gx;
  56
  57        struct iommu_domain *domain;
  58        u64 uncached_iova_base;
  59
  60        int idle_level;
  61
  62        struct a6xx_gmu_bo *hfi;
  63        struct a6xx_gmu_bo *debug;
  64
  65        int nr_clocks;
  66        struct clk_bulk_data *clocks;
  67        struct clk *core_clk;
  68
  69        int nr_gpu_freqs;
  70        unsigned long gpu_freqs[16];
  71        u32 gx_arc_votes[16];
  72
  73        int nr_gmu_freqs;
  74        unsigned long gmu_freqs[4];
  75        u32 cx_arc_votes[4];
  76
  77        struct a6xx_hfi_queue queues[2];
  78
  79        struct tasklet_struct hfi_tasklet;
  80};
  81
  82static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
  83{
  84        return msm_readl(gmu->mmio + (offset << 2));
  85}
  86
  87static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
  88{
  89        return msm_writel(value, gmu->mmio + (offset << 2));
  90}
  91
  92static inline void pdc_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
  93{
  94        return msm_writel(value, gmu->pdc_mmio + (offset << 2));
  95}
  96
  97static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
  98{
  99        u32 val = gmu_read(gmu, reg);
 100
 101        val &= ~mask;
 102
 103        gmu_write(gmu, reg, val | or);
 104}
 105
 106#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
 107        readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
 108                interval, timeout)
 109
 110/*
 111 * These are the available OOB (out of band requests) to the GMU where "out of
 112 * band" means that the CPU talks to the GMU directly and not through HFI.
 113 * Normally this works by writing a ITCM/DTCM register and then triggering a
 114 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
 115 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
 116 *
 117 * These are used to force the GMU/GPU to stay on during a critical sequence or
 118 * for hardware workarounds.
 119 */
 120
 121enum a6xx_gmu_oob_state {
 122        GMU_OOB_BOOT_SLUMBER = 0,
 123        GMU_OOB_GPU_SET,
 124        GMU_OOB_DCVS_SET,
 125};
 126
 127/* These are the interrupt / ack bits for each OOB request that are set
 128 * in a6xx_gmu_set_oob and a6xx_clear_oob
 129 */
 130
 131/*
 132 * Let the GMU know that a boot or slumber operation has started. The value in
 133 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
 134 * doing
 135 */
 136#define GMU_OOB_BOOT_SLUMBER_REQUEST    22
 137#define GMU_OOB_BOOT_SLUMBER_ACK        30
 138#define GMU_OOB_BOOT_SLUMBER_CLEAR      30
 139
 140/*
 141 * Set a new power level for the GPU when the CPU is doing frequency scaling
 142 */
 143#define GMU_OOB_DCVS_REQUEST    23
 144#define GMU_OOB_DCVS_ACK        31
 145#define GMU_OOB_DCVS_CLEAR      31
 146
 147/*
 148 * Let the GMU know to not turn off any GPU registers while the CPU is in a
 149 * critical section
 150 */
 151#define GMU_OOB_GPU_SET_REQUEST 16
 152#define GMU_OOB_GPU_SET_ACK     24
 153#define GMU_OOB_GPU_SET_CLEAR   24
 154
 155
 156void a6xx_hfi_init(struct a6xx_gmu *gmu);
 157int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
 158void a6xx_hfi_stop(struct a6xx_gmu *gmu);
 159
 160void a6xx_hfi_task(unsigned long data);
 161
 162#endif
 163