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10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include <linux/iio/buffer.h>
22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include <linux/iio/trigger.h>
25#include <linux/iio/trigger_consumer.h>
26#include <linux/iio/triggered_buffer.h>
27
28
29#define CC10001_ADC_CONFIG 0x00
30#define CC10001_ADC_START_CONV BIT(4)
31#define CC10001_ADC_MODE_SINGLE_CONV BIT(5)
32
33#define CC10001_ADC_DDATA_OUT 0x04
34#define CC10001_ADC_EOC 0x08
35#define CC10001_ADC_EOC_SET BIT(0)
36
37#define CC10001_ADC_CHSEL_SAMPLED 0x0c
38#define CC10001_ADC_POWER_DOWN 0x10
39#define CC10001_ADC_POWER_DOWN_SET BIT(0)
40
41#define CC10001_ADC_DEBUG 0x14
42#define CC10001_ADC_DATA_COUNT 0x20
43
44#define CC10001_ADC_DATA_MASK GENMASK(9, 0)
45#define CC10001_ADC_NUM_CHANNELS 8
46#define CC10001_ADC_CH_MASK GENMASK(2, 0)
47
48#define CC10001_INVALID_SAMPLED 0xffff
49#define CC10001_MAX_POLL_COUNT 20
50
51
52
53
54
55
56
57#define CC10001_WAIT_CYCLES 8
58
59struct cc10001_adc_device {
60 void __iomem *reg_base;
61 struct clk *adc_clk;
62 struct regulator *reg;
63 u16 *buf;
64
65 bool shared;
66 struct mutex lock;
67 unsigned int start_delay_ns;
68 unsigned int eoc_delay_ns;
69};
70
71static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
72 u32 reg, u32 val)
73{
74 writel(val, adc_dev->reg_base + reg);
75}
76
77static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
78 u32 reg)
79{
80 return readl(adc_dev->reg_base + reg);
81}
82
83static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
84{
85 cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
86 ndelay(adc_dev->start_delay_ns);
87}
88
89static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
90{
91 cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
92 CC10001_ADC_POWER_DOWN_SET);
93}
94
95static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
96 unsigned int channel)
97{
98 u32 val;
99
100
101 val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
102 cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
103
104 udelay(1);
105 val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
106 val = val | CC10001_ADC_START_CONV;
107 cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
108}
109
110static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
111 unsigned int channel,
112 unsigned int delay)
113{
114 struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
115 unsigned int poll_count = 0;
116
117 while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
118 CC10001_ADC_EOC_SET)) {
119
120 ndelay(delay);
121 if (poll_count++ == CC10001_MAX_POLL_COUNT)
122 return CC10001_INVALID_SAMPLED;
123 }
124
125 poll_count = 0;
126 while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
127 CC10001_ADC_CH_MASK) != channel) {
128
129 ndelay(delay);
130 if (poll_count++ == CC10001_MAX_POLL_COUNT)
131 return CC10001_INVALID_SAMPLED;
132 }
133
134
135 return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
136 CC10001_ADC_DATA_MASK;
137}
138
139static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
140{
141 struct cc10001_adc_device *adc_dev;
142 struct iio_poll_func *pf = p;
143 struct iio_dev *indio_dev;
144 unsigned int delay_ns;
145 unsigned int channel;
146 unsigned int scan_idx;
147 bool sample_invalid;
148 u16 *data;
149 int i;
150
151 indio_dev = pf->indio_dev;
152 adc_dev = iio_priv(indio_dev);
153 data = adc_dev->buf;
154
155 mutex_lock(&adc_dev->lock);
156
157 if (!adc_dev->shared)
158 cc10001_adc_power_up(adc_dev);
159
160
161 delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
162
163 i = 0;
164 sample_invalid = false;
165 for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
166 indio_dev->masklength) {
167
168 channel = indio_dev->channels[scan_idx].channel;
169 cc10001_adc_start(adc_dev, channel);
170
171 data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
172 if (data[i] == CC10001_INVALID_SAMPLED) {
173 dev_warn(&indio_dev->dev,
174 "invalid sample on channel %d\n", channel);
175 sample_invalid = true;
176 goto done;
177 }
178 i++;
179 }
180
181done:
182 if (!adc_dev->shared)
183 cc10001_adc_power_down(adc_dev);
184
185 mutex_unlock(&adc_dev->lock);
186
187 if (!sample_invalid)
188 iio_push_to_buffers_with_timestamp(indio_dev, data,
189 iio_get_time_ns(indio_dev));
190 iio_trigger_notify_done(indio_dev->trig);
191
192 return IRQ_HANDLED;
193}
194
195static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
196 struct iio_chan_spec const *chan)
197{
198 struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
199 unsigned int delay_ns;
200 u16 val;
201
202 if (!adc_dev->shared)
203 cc10001_adc_power_up(adc_dev);
204
205
206 delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
207
208 cc10001_adc_start(adc_dev, chan->channel);
209
210 val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
211
212 if (!adc_dev->shared)
213 cc10001_adc_power_down(adc_dev);
214
215 return val;
216}
217
218static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
219 struct iio_chan_spec const *chan,
220 int *val, int *val2, long mask)
221{
222 struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
223 int ret;
224
225 switch (mask) {
226 case IIO_CHAN_INFO_RAW:
227 if (iio_buffer_enabled(indio_dev))
228 return -EBUSY;
229 mutex_lock(&adc_dev->lock);
230 *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
231 mutex_unlock(&adc_dev->lock);
232
233 if (*val == CC10001_INVALID_SAMPLED)
234 return -EIO;
235 return IIO_VAL_INT;
236
237 case IIO_CHAN_INFO_SCALE:
238 ret = regulator_get_voltage(adc_dev->reg);
239 if (ret < 0)
240 return ret;
241
242 *val = ret / 1000;
243 *val2 = chan->scan_type.realbits;
244 return IIO_VAL_FRACTIONAL_LOG2;
245
246 default:
247 return -EINVAL;
248 }
249}
250
251static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
252 const unsigned long *scan_mask)
253{
254 struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
255
256 kfree(adc_dev->buf);
257 adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
258 if (!adc_dev->buf)
259 return -ENOMEM;
260
261 return 0;
262}
263
264static const struct iio_info cc10001_adc_info = {
265 .read_raw = &cc10001_adc_read_raw,
266 .update_scan_mode = &cc10001_update_scan_mode,
267};
268
269static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
270 unsigned long channel_map)
271{
272 struct iio_chan_spec *chan_array, *timestamp;
273 unsigned int bit, idx = 0;
274
275 indio_dev->num_channels = bitmap_weight(&channel_map,
276 CC10001_ADC_NUM_CHANNELS) + 1;
277
278 chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
279 sizeof(struct iio_chan_spec),
280 GFP_KERNEL);
281 if (!chan_array)
282 return -ENOMEM;
283
284 for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
285 struct iio_chan_spec *chan = &chan_array[idx];
286
287 chan->type = IIO_VOLTAGE;
288 chan->indexed = 1;
289 chan->channel = bit;
290 chan->scan_index = idx;
291 chan->scan_type.sign = 'u';
292 chan->scan_type.realbits = 10;
293 chan->scan_type.storagebits = 16;
294 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
295 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
296 idx++;
297 }
298
299 timestamp = &chan_array[idx];
300 timestamp->type = IIO_TIMESTAMP;
301 timestamp->channel = -1;
302 timestamp->scan_index = idx;
303 timestamp->scan_type.sign = 's';
304 timestamp->scan_type.realbits = 64;
305 timestamp->scan_type.storagebits = 64;
306
307 indio_dev->channels = chan_array;
308
309 return 0;
310}
311
312static int cc10001_adc_probe(struct platform_device *pdev)
313{
314 struct device_node *node = pdev->dev.of_node;
315 struct cc10001_adc_device *adc_dev;
316 unsigned long adc_clk_rate;
317 struct resource *res;
318 struct iio_dev *indio_dev;
319 unsigned long channel_map;
320 int ret;
321
322 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
323 if (indio_dev == NULL)
324 return -ENOMEM;
325
326 adc_dev = iio_priv(indio_dev);
327
328 channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
329 if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
330 adc_dev->shared = true;
331 channel_map &= ~ret;
332 }
333
334 adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
335 if (IS_ERR(adc_dev->reg))
336 return PTR_ERR(adc_dev->reg);
337
338 ret = regulator_enable(adc_dev->reg);
339 if (ret)
340 return ret;
341
342 indio_dev->dev.parent = &pdev->dev;
343 indio_dev->name = dev_name(&pdev->dev);
344 indio_dev->info = &cc10001_adc_info;
345 indio_dev->modes = INDIO_DIRECT_MODE;
346
347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res);
349 if (IS_ERR(adc_dev->reg_base)) {
350 ret = PTR_ERR(adc_dev->reg_base);
351 goto err_disable_reg;
352 }
353
354 adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
355 if (IS_ERR(adc_dev->adc_clk)) {
356 dev_err(&pdev->dev, "failed to get the clock\n");
357 ret = PTR_ERR(adc_dev->adc_clk);
358 goto err_disable_reg;
359 }
360
361 ret = clk_prepare_enable(adc_dev->adc_clk);
362 if (ret) {
363 dev_err(&pdev->dev, "failed to enable the clock\n");
364 goto err_disable_reg;
365 }
366
367 adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
368 if (!adc_clk_rate) {
369 ret = -EINVAL;
370 dev_err(&pdev->dev, "null clock rate!\n");
371 goto err_disable_clk;
372 }
373
374 adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
375 adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
376
377
378
379
380
381
382 if (adc_dev->shared)
383 cc10001_adc_power_up(adc_dev);
384
385
386 ret = cc10001_adc_channel_init(indio_dev, channel_map);
387 if (ret < 0)
388 goto err_disable_clk;
389
390 mutex_init(&adc_dev->lock);
391
392 ret = iio_triggered_buffer_setup(indio_dev, NULL,
393 &cc10001_adc_trigger_h, NULL);
394 if (ret < 0)
395 goto err_disable_clk;
396
397 ret = iio_device_register(indio_dev);
398 if (ret < 0)
399 goto err_cleanup_buffer;
400
401 platform_set_drvdata(pdev, indio_dev);
402
403 return 0;
404
405err_cleanup_buffer:
406 iio_triggered_buffer_cleanup(indio_dev);
407err_disable_clk:
408 clk_disable_unprepare(adc_dev->adc_clk);
409err_disable_reg:
410 regulator_disable(adc_dev->reg);
411 return ret;
412}
413
414static int cc10001_adc_remove(struct platform_device *pdev)
415{
416 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
417 struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
418
419 cc10001_adc_power_down(adc_dev);
420 iio_device_unregister(indio_dev);
421 iio_triggered_buffer_cleanup(indio_dev);
422 clk_disable_unprepare(adc_dev->adc_clk);
423 regulator_disable(adc_dev->reg);
424
425 return 0;
426}
427
428static const struct of_device_id cc10001_adc_dt_ids[] = {
429 { .compatible = "cosmic,10001-adc", },
430 { }
431};
432MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
433
434static struct platform_driver cc10001_adc_driver = {
435 .driver = {
436 .name = "cc10001-adc",
437 .of_match_table = cc10001_adc_dt_ids,
438 },
439 .probe = cc10001_adc_probe,
440 .remove = cc10001_adc_remove,
441};
442module_platform_driver(cc10001_adc_driver);
443
444MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
445MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
446MODULE_LICENSE("GPL v2");
447
