LXR linux/drivers/media/platform/omap3isp/ispcsi2.h

   1/*
   2 * ispcsi2.h
   3 *
   4 * TI OMAP3 ISP - CSI2 module
   5 *
   6 * Copyright (C) 2010 Nokia Corporation
   7 * Copyright (C) 2009 Texas Instruments, Inc.
   8 *
   9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10 *           Sakari Ailus <sakari.ailus@iki.fi>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation.
  15 */
  16
  17#ifndef OMAP3_ISP_CSI2_H
  18#define OMAP3_ISP_CSI2_H
  19
  20#include <linux/types.h>
  21#include <linux/videodev2.h>
  22
  23struct isp_csiphy;
  24
  25/* This is not an exhaustive list */
  26enum isp_csi2_pix_formats {
  27        CSI2_PIX_FMT_OTHERS = 0,
  28        CSI2_PIX_FMT_YUV422_8BIT = 0x1e,
  29        CSI2_PIX_FMT_YUV422_8BIT_VP = 0x9e,
  30        CSI2_PIX_FMT_RAW10_EXP16 = 0xab,
  31        CSI2_PIX_FMT_RAW10_EXP16_VP = 0x12f,
  32        CSI2_PIX_FMT_RAW8 = 0x2a,
  33        CSI2_PIX_FMT_RAW8_DPCM10_EXP16 = 0x2aa,
  34        CSI2_PIX_FMT_RAW8_DPCM10_VP = 0x32a,
  35        CSI2_PIX_FMT_RAW8_VP = 0x12a,
  36        CSI2_USERDEF_8BIT_DATA1_DPCM10_VP = 0x340,
  37        CSI2_USERDEF_8BIT_DATA1_DPCM10 = 0x2c0,
  38        CSI2_USERDEF_8BIT_DATA1 = 0x40,
  39};
  40
  41enum isp_csi2_irqevents {
  42        OCP_ERR_IRQ = 0x4000,
  43        SHORT_PACKET_IRQ = 0x2000,
  44        ECC_CORRECTION_IRQ = 0x1000,
  45        ECC_NO_CORRECTION_IRQ = 0x800,
  46        COMPLEXIO2_ERR_IRQ = 0x400,
  47        COMPLEXIO1_ERR_IRQ = 0x200,
  48        FIFO_OVF_IRQ = 0x100,
  49        CONTEXT7 = 0x80,
  50        CONTEXT6 = 0x40,
  51        CONTEXT5 = 0x20,
  52        CONTEXT4 = 0x10,
  53        CONTEXT3 = 0x8,
  54        CONTEXT2 = 0x4,
  55        CONTEXT1 = 0x2,
  56        CONTEXT0 = 0x1,
  57};
  58
  59enum isp_csi2_ctx_irqevents {
  60        CTX_ECC_CORRECTION = 0x100,
  61        CTX_LINE_NUMBER = 0x80,
  62        CTX_FRAME_NUMBER = 0x40,
  63        CTX_CS = 0x20,
  64        CTX_LE = 0x8,
  65        CTX_LS = 0x4,
  66        CTX_FE = 0x2,
  67        CTX_FS = 0x1,
  68};
  69
  70enum isp_csi2_frame_mode {
  71        ISP_CSI2_FRAME_IMMEDIATE,
  72        ISP_CSI2_FRAME_AFTERFEC,
  73};
  74
  75#define ISP_CSI2_MAX_CTX_NUM    7
  76
  77struct isp_csi2_ctx_cfg {
  78        u8 ctxnum;              /* context number 0 - 7 */
  79        u8 dpcm_decompress;
  80
  81        /* Fields in CSI2_CTx_CTRL2 - locked by CSI2_CTx_CTRL1.CTX_EN */
  82        u8 virtual_id;
  83        u16 format_id;          /* as in CSI2_CTx_CTRL2[9:0] */
  84        u8 dpcm_predictor;      /* 1: simple, 0: advanced */
  85
  86        /* Fields in CSI2_CTx_CTRL1/3 - Shadowed */
  87        u16 alpha;
  88        u16 data_offset;
  89        u32 ping_addr;
  90        u32 pong_addr;
  91        u8 eof_enabled;
  92        u8 eol_enabled;
  93        u8 checksum_enabled;
  94        u8 enabled;
  95};
  96
  97struct isp_csi2_timing_cfg {
  98        u8 ionum;                       /* IO1 or IO2 as in CSI2_TIMING */
  99        unsigned force_rx_mode:1;
 100        unsigned stop_state_16x:1;
 101        unsigned stop_state_4x:1;
 102        u16 stop_state_counter;
 103};
 104
 105struct isp_csi2_ctrl_cfg {
 106        bool vp_clk_enable;
 107        bool vp_only_enable;
 108        u8 vp_out_ctrl;
 109        enum isp_csi2_frame_mode frame_mode;
 110        bool ecc_enable;
 111        bool if_enable;
 112};
 113
 114#define CSI2_PAD_SINK           0
 115#define CSI2_PAD_SOURCE         1
 116#define CSI2_PADS_NUM           2
 117
 118#define CSI2_OUTPUT_CCDC        (1 << 0)
 119#define CSI2_OUTPUT_MEMORY      (1 << 1)
 120
 121struct isp_csi2_device {
 122        struct v4l2_subdev subdev;
 123        struct media_pad pads[CSI2_PADS_NUM];
 124        struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM];
 125
 126        struct isp_video video_out;
 127        struct isp_device *isp;
 128
 129        u8 available;           /* Is the IP present on the silicon? */
 130
 131        /* mem resources - enums as defined in enum isp_mem_resources */
 132        u8 regs1;
 133        u8 regs2;
 134
 135        u32 output; /* output to CCDC, memory or both? */
 136        bool dpcm_decompress;
 137        unsigned int frame_skip;
 138
 139        struct isp_csiphy *phy;
 140        struct isp_csi2_ctx_cfg contexts[ISP_CSI2_MAX_CTX_NUM + 1];
 141        struct isp_csi2_timing_cfg timing[2];
 142        struct isp_csi2_ctrl_cfg ctrl;
 143        enum isp_pipeline_stream_state state;
 144        wait_queue_head_t wait;
 145        atomic_t stopping;
 146};
 147
 148void omap3isp_csi2_isr(struct isp_csi2_device *csi2);
 149int omap3isp_csi2_reset(struct isp_csi2_device *csi2);
 150int omap3isp_csi2_init(struct isp_device *isp);
 151void omap3isp_csi2_cleanup(struct isp_device *isp);
 152void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2);
 153int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
 154                                    struct v4l2_device *vdev);
 155#endif  /* OMAP3_ISP_CSI2_H */
 156