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17#include <linux/pci.h>
18#include <linux/jiffies.h>
19#include <linux/ktime.h>
20#include <linux/delay.h>
21#include <linux/kthread.h>
22#include <linux/interrupt.h>
23#include <linux/pm_runtime.h>
24
25#include <linux/mei.h>
26
27#include "mei_dev.h"
28#include "hw-txe.h"
29#include "client.h"
30#include "hbm.h"
31
32#include "mei-trace.h"
33
34#define TXE_HBUF_DEPTH (PAYLOAD_SIZE / MEI_SLOT_SIZE)
35
36
37
38
39
40
41
42
43
44static inline u32 mei_txe_reg_read(void __iomem *base_addr,
45 unsigned long offset)
46{
47 return ioread32(base_addr + offset);
48}
49
50
51
52
53
54
55
56
57static inline void mei_txe_reg_write(void __iomem *base_addr,
58 unsigned long offset, u32 value)
59{
60 iowrite32(value, base_addr + offset);
61}
62
63
64
65
66
67
68
69
70
71
72
73static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
74 unsigned long offset)
75{
76 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
77}
78
79
80
81
82
83
84
85
86
87
88
89static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
90 unsigned long offset)
91{
92 WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
93 return mei_txe_sec_reg_read_silent(hw, offset);
94}
95
96
97
98
99
100
101
102
103
104
105static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
106 unsigned long offset, u32 value)
107{
108 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
109}
110
111
112
113
114
115
116
117
118
119
120static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
121 unsigned long offset, u32 value)
122{
123 WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
124 mei_txe_sec_reg_write_silent(hw, offset, value);
125}
126
127
128
129
130
131
132
133
134static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
135 unsigned long offset)
136{
137 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
138}
139
140
141
142
143
144
145
146
147static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
148 unsigned long offset, u32 value)
149{
150 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
151}
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
168{
169
170 struct mei_txe_hw *hw = to_txe_hw(dev);
171 bool do_req = hw->aliveness != req;
172
173 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
174 hw->aliveness, req);
175 if (do_req) {
176 dev->pg_event = MEI_PG_EVENT_WAIT;
177 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
178 }
179 return do_req;
180}
181
182
183
184
185
186
187
188
189
190
191
192
193static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
194{
195 struct mei_txe_hw *hw = to_txe_hw(dev);
196 u32 reg;
197
198 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
199 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
200}
201
202
203
204
205
206
207
208
209
210static u32 mei_txe_aliveness_get(struct mei_device *dev)
211{
212 struct mei_txe_hw *hw = to_txe_hw(dev);
213 u32 reg;
214
215 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
216 return reg & HICR_HOST_ALIVENESS_RESP_ACK;
217}
218
219
220
221
222
223
224
225
226
227
228
229static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
230{
231 struct mei_txe_hw *hw = to_txe_hw(dev);
232 ktime_t stop, start;
233
234 start = ktime_get();
235 stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
236 do {
237 hw->aliveness = mei_txe_aliveness_get(dev);
238 if (hw->aliveness == expected) {
239 dev->pg_event = MEI_PG_EVENT_IDLE;
240 dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
241 ktime_to_us(ktime_sub(ktime_get(), start)));
242 return 0;
243 }
244 usleep_range(20, 50);
245 } while (ktime_before(ktime_get(), stop));
246
247 dev->pg_event = MEI_PG_EVENT_IDLE;
248 dev_err(dev->dev, "aliveness timed out\n");
249 return -ETIME;
250}
251
252
253
254
255
256
257
258
259
260
261
262static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
263{
264 struct mei_txe_hw *hw = to_txe_hw(dev);
265 const unsigned long timeout =
266 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
267 long err;
268 int ret;
269
270 hw->aliveness = mei_txe_aliveness_get(dev);
271 if (hw->aliveness == expected)
272 return 0;
273
274 mutex_unlock(&dev->device_lock);
275 err = wait_event_timeout(hw->wait_aliveness_resp,
276 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
277 mutex_lock(&dev->device_lock);
278
279 hw->aliveness = mei_txe_aliveness_get(dev);
280 ret = hw->aliveness == expected ? 0 : -ETIME;
281
282 if (ret)
283 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
284 err, hw->aliveness, dev->pg_event);
285 else
286 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
287 jiffies_to_msecs(timeout - err),
288 hw->aliveness, dev->pg_event);
289
290 dev->pg_event = MEI_PG_EVENT_IDLE;
291 return ret;
292}
293
294
295
296
297
298
299
300
301
302int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
303{
304 if (mei_txe_aliveness_set(dev, req))
305 return mei_txe_aliveness_wait(dev, req);
306 return 0;
307}
308
309
310
311
312
313
314
315
316static bool mei_txe_pg_in_transition(struct mei_device *dev)
317{
318 return dev->pg_event == MEI_PG_EVENT_WAIT;
319}
320
321
322
323
324
325
326
327
328static bool mei_txe_pg_is_enabled(struct mei_device *dev)
329{
330 return true;
331}
332
333
334
335
336
337
338
339
340
341static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
342{
343 struct mei_txe_hw *hw = to_txe_hw(dev);
344
345 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
346}
347
348
349
350
351
352
353static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
354{
355 struct mei_txe_hw *hw = to_txe_hw(dev);
356 u32 hintmsk;
357
358 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
359 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
360 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
361}
362
363
364
365
366
367
368
369static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
370{
371
372 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
373 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
374}
375
376
377
378
379
380
381static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
382{
383 mei_txe_br_reg_write(hw,
384 SICR_SEC_IPC_OUTPUT_STATUS_REG,
385 SEC_IPC_OUTPUT_STATUS_RDY);
386}
387
388
389
390
391
392
393
394
395static bool mei_txe_is_input_ready(struct mei_device *dev)
396{
397 struct mei_txe_hw *hw = to_txe_hw(dev);
398 u32 status;
399
400 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
401 return !!(SEC_IPC_INPUT_STATUS_RDY & status);
402}
403
404
405
406
407
408
409static inline void mei_txe_intr_clear(struct mei_device *dev)
410{
411 struct mei_txe_hw *hw = to_txe_hw(dev);
412
413 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
414 SEC_IPC_HOST_INT_STATUS_PENDING);
415 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
416 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
417}
418
419
420
421
422
423
424static void mei_txe_intr_disable(struct mei_device *dev)
425{
426 struct mei_txe_hw *hw = to_txe_hw(dev);
427
428 mei_txe_br_reg_write(hw, HHIER_REG, 0);
429 mei_txe_br_reg_write(hw, HIER_REG, 0);
430}
431
432
433
434
435
436static void mei_txe_intr_enable(struct mei_device *dev)
437{
438 struct mei_txe_hw *hw = to_txe_hw(dev);
439
440 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
441 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
442}
443
444
445
446
447
448
449static void mei_txe_synchronize_irq(struct mei_device *dev)
450{
451 struct pci_dev *pdev = to_pci_dev(dev->dev);
452
453 synchronize_irq(pdev->irq);
454}
455
456
457
458
459
460
461
462
463
464
465
466
467static bool mei_txe_pending_interrupts(struct mei_device *dev)
468{
469
470 struct mei_txe_hw *hw = to_txe_hw(dev);
471 bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
472 TXE_INTR_ALIVENESS |
473 TXE_INTR_IN_READY |
474 TXE_INTR_OUT_DB));
475
476 if (ret) {
477 dev_dbg(dev->dev,
478 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
479 !!(hw->intr_cause & TXE_INTR_IN_READY),
480 !!(hw->intr_cause & TXE_INTR_READINESS),
481 !!(hw->intr_cause & TXE_INTR_ALIVENESS),
482 !!(hw->intr_cause & TXE_INTR_OUT_DB));
483 }
484 return ret;
485}
486
487
488
489
490
491
492
493
494
495static void mei_txe_input_payload_write(struct mei_device *dev,
496 unsigned long idx, u32 value)
497{
498 struct mei_txe_hw *hw = to_txe_hw(dev);
499
500 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
501 (idx * sizeof(u32)), value);
502}
503
504
505
506
507
508
509
510
511
512
513static u32 mei_txe_out_data_read(const struct mei_device *dev,
514 unsigned long idx)
515{
516 struct mei_txe_hw *hw = to_txe_hw(dev);
517
518 return mei_txe_br_reg_read(hw,
519 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
520}
521
522
523
524
525
526
527
528
529static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
530{
531 struct mei_txe_hw *hw = to_txe_hw(dev);
532
533 mei_txe_br_reg_write(hw,
534 SICR_HOST_IPC_READINESS_REQ_REG,
535 SICR_HOST_IPC_READINESS_HOST_RDY);
536}
537
538
539
540
541
542
543static void mei_txe_readiness_clear(struct mei_device *dev)
544{
545 struct mei_txe_hw *hw = to_txe_hw(dev);
546
547 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
548 SICR_HOST_IPC_READINESS_RDY_CLR);
549}
550
551
552
553
554
555
556
557
558static u32 mei_txe_readiness_get(struct mei_device *dev)
559{
560 struct mei_txe_hw *hw = to_txe_hw(dev);
561
562 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
563}
564
565
566
567
568
569
570
571
572
573
574static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
575{
576 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
577}
578
579
580
581
582
583
584
585
586static bool mei_txe_hw_is_ready(struct mei_device *dev)
587{
588 u32 readiness = mei_txe_readiness_get(dev);
589
590 return mei_txe_readiness_is_sec_rdy(readiness);
591}
592
593
594
595
596
597
598
599
600static inline bool mei_txe_host_is_ready(struct mei_device *dev)
601{
602 struct mei_txe_hw *hw = to_txe_hw(dev);
603 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
604
605 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
606}
607
608
609
610
611
612
613
614
615static int mei_txe_readiness_wait(struct mei_device *dev)
616{
617 if (mei_txe_hw_is_ready(dev))
618 return 0;
619
620 mutex_unlock(&dev->device_lock);
621 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
622 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
623 mutex_lock(&dev->device_lock);
624 if (!dev->recvd_hw_ready) {
625 dev_err(dev->dev, "wait for readiness failed\n");
626 return -ETIME;
627 }
628
629 dev->recvd_hw_ready = false;
630 return 0;
631}
632
633static const struct mei_fw_status mei_txe_fw_sts = {
634 .count = 2,
635 .status[0] = PCI_CFG_TXE_FW_STS0,
636 .status[1] = PCI_CFG_TXE_FW_STS1
637};
638
639
640
641
642
643
644
645
646
647static int mei_txe_fw_status(struct mei_device *dev,
648 struct mei_fw_status *fw_status)
649{
650 const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
651 struct pci_dev *pdev = to_pci_dev(dev->dev);
652 int ret;
653 int i;
654
655 if (!fw_status)
656 return -EINVAL;
657
658 fw_status->count = fw_src->count;
659 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
660 ret = pci_read_config_dword(pdev, fw_src->status[i],
661 &fw_status->status[i]);
662 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
663 fw_src->status[i],
664 fw_status->status[i]);
665 if (ret)
666 return ret;
667 }
668
669 return 0;
670}
671
672
673
674
675
676
677
678
679
680static void mei_txe_hw_config(struct mei_device *dev)
681{
682
683 struct mei_txe_hw *hw = to_txe_hw(dev);
684
685 hw->aliveness = mei_txe_aliveness_get(dev);
686 hw->readiness = mei_txe_readiness_get(dev);
687
688 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
689 hw->aliveness, hw->readiness);
690}
691
692
693
694
695
696
697
698
699
700
701
702
703static int mei_txe_write(struct mei_device *dev,
704 const void *hdr, size_t hdr_len,
705 const void *data, size_t data_len)
706{
707 struct mei_txe_hw *hw = to_txe_hw(dev);
708 unsigned long rem;
709 const u32 *reg_buf;
710 u32 slots = TXE_HBUF_DEPTH;
711 u32 dw_cnt;
712 unsigned long i, j;
713
714 if (WARN_ON(!hdr || !data || hdr_len & 0x3))
715 return -EINVAL;
716
717 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
718
719 dw_cnt = mei_data2slots(hdr_len + data_len);
720 if (dw_cnt > slots)
721 return -EMSGSIZE;
722
723 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
724 return -EAGAIN;
725
726
727 mei_txe_input_ready_interrupt_enable(dev);
728
729 if (!mei_txe_is_input_ready(dev)) {
730 char fw_sts_str[MEI_FW_STATUS_STR_SZ];
731
732 mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
733 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
734 return -EAGAIN;
735 }
736
737 reg_buf = hdr;
738 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
739 mei_txe_input_payload_write(dev, i, reg_buf[i]);
740
741 reg_buf = data;
742 for (j = 0; j < data_len / MEI_SLOT_SIZE; j++)
743 mei_txe_input_payload_write(dev, i + j, reg_buf[j]);
744
745 rem = data_len & 0x3;
746 if (rem > 0) {
747 u32 reg = 0;
748
749 memcpy(®, (const u8 *)data + data_len - rem, rem);
750 mei_txe_input_payload_write(dev, i + j, reg);
751 }
752
753
754 hw->slots = 0;
755
756
757 mei_txe_input_doorbell_set(hw);
758
759 return 0;
760}
761
762
763
764
765
766
767
768
769static u32 mei_txe_hbuf_depth(const struct mei_device *dev)
770{
771 return TXE_HBUF_DEPTH;
772}
773
774
775
776
777
778
779
780
781static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
782{
783 struct mei_txe_hw *hw = to_txe_hw(dev);
784
785 return hw->slots;
786}
787
788
789
790
791
792
793
794
795static int mei_txe_count_full_read_slots(struct mei_device *dev)
796{
797
798 return TXE_HBUF_DEPTH;
799}
800
801
802
803
804
805
806
807
808
809static u32 mei_txe_read_hdr(const struct mei_device *dev)
810{
811 return mei_txe_out_data_read(dev, 0);
812}
813
814
815
816
817
818
819
820
821
822static int mei_txe_read(struct mei_device *dev,
823 unsigned char *buf, unsigned long len)
824{
825
826 struct mei_txe_hw *hw = to_txe_hw(dev);
827 u32 *reg_buf, reg;
828 u32 rem;
829 u32 i;
830
831 if (WARN_ON(!buf || !len))
832 return -EINVAL;
833
834 reg_buf = (u32 *)buf;
835 rem = len & 0x3;
836
837 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
838 len, mei_txe_out_data_read(dev, 0));
839
840 for (i = 0; i < len / MEI_SLOT_SIZE; i++) {
841
842 reg = mei_txe_out_data_read(dev, i + 1);
843 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
844 *reg_buf++ = reg;
845 }
846
847 if (rem) {
848 reg = mei_txe_out_data_read(dev, i + 1);
849 memcpy(reg_buf, ®, rem);
850 }
851
852 mei_txe_output_ready_set(hw);
853 return 0;
854}
855
856
857
858
859
860
861
862
863
864static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
865{
866 struct mei_txe_hw *hw = to_txe_hw(dev);
867
868 u32 aliveness_req;
869
870
871
872
873 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
874
875 aliveness_req = mei_txe_aliveness_req_get(dev);
876 hw->aliveness = mei_txe_aliveness_get(dev);
877
878
879 mei_txe_intr_disable(dev);
880
881
882
883
884
885
886 if (aliveness_req != hw->aliveness)
887 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
888 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
889 return -EIO;
890 }
891
892
893
894
895 if (aliveness_req) {
896 mei_txe_aliveness_set(dev, 0);
897 if (mei_txe_aliveness_poll(dev, 0) < 0) {
898 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
899 return -EIO;
900 }
901 }
902
903
904
905
906 mei_txe_readiness_clear(dev);
907
908 return 0;
909}
910
911
912
913
914
915
916
917
918static int mei_txe_hw_start(struct mei_device *dev)
919{
920 struct mei_txe_hw *hw = to_txe_hw(dev);
921 int ret;
922
923 u32 hisr;
924
925
926 mei_txe_intr_enable(dev);
927
928 ret = mei_txe_readiness_wait(dev);
929 if (ret < 0) {
930 dev_err(dev->dev, "waiting for readiness failed\n");
931 return ret;
932 }
933
934
935
936
937 hisr = mei_txe_br_reg_read(hw, HISR_REG);
938 if (hisr & HISR_INT_2_STS)
939 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
940
941
942 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
943
944 ret = mei_txe_aliveness_set_sync(dev, 1);
945 if (ret < 0) {
946 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
947 return ret;
948 }
949
950 pm_runtime_set_active(dev->dev);
951
952
953
954
955 mei_txe_input_ready_interrupt_enable(dev);
956
957
958
959 mei_txe_output_ready_set(hw);
960
961
962
963 mei_txe_readiness_set_host_rdy(dev);
964
965 return 0;
966}
967
968
969
970
971
972
973
974
975
976
977static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
978{
979 struct mei_txe_hw *hw = to_txe_hw(dev);
980 u32 hisr;
981 u32 hhisr;
982 u32 ipc_isr;
983 u32 aliveness;
984 bool generated;
985
986
987 hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
988 generated = (hhisr & IPC_HHIER_MSK);
989 if (!generated)
990 goto out;
991
992 hisr = mei_txe_br_reg_read(hw, HISR_REG);
993
994 aliveness = mei_txe_aliveness_get(dev);
995 if (hhisr & IPC_HHIER_SEC && aliveness) {
996 ipc_isr = mei_txe_sec_reg_read_silent(hw,
997 SEC_IPC_HOST_INT_STATUS_REG);
998 } else {
999 ipc_isr = 0;
1000 hhisr &= ~IPC_HHIER_SEC;
1001 }
1002
1003 generated = generated ||
1004 (hisr & HISR_INT_STS_MSK) ||
1005 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
1006
1007 if (generated && do_ack) {
1008
1009 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
1010 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
1011 hw->intr_cause |= TXE_INTR_IN_READY;
1012
1013
1014 mei_txe_intr_disable(dev);
1015
1016
1017 mei_txe_sec_reg_write_silent(hw,
1018 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
1019 mei_txe_br_reg_write(hw, HISR_REG, hisr);
1020 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
1021 }
1022
1023out:
1024 return generated;
1025}
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1037{
1038 struct mei_device *dev = dev_id;
1039
1040 if (mei_txe_check_and_ack_intrs(dev, true))
1041 return IRQ_WAKE_THREAD;
1042 return IRQ_NONE;
1043}
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1055{
1056 struct mei_device *dev = (struct mei_device *) dev_id;
1057 struct mei_txe_hw *hw = to_txe_hw(dev);
1058 struct list_head cmpl_list;
1059 s32 slots;
1060 int rets = 0;
1061
1062 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1063 mei_txe_br_reg_read(hw, HHISR_REG),
1064 mei_txe_br_reg_read(hw, HISR_REG),
1065 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1066
1067
1068
1069 mutex_lock(&dev->device_lock);
1070 INIT_LIST_HEAD(&cmpl_list);
1071
1072 if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1073 mei_txe_check_and_ack_intrs(dev, true);
1074
1075
1076 mei_txe_pending_interrupts(dev);
1077
1078 hw->aliveness = mei_txe_aliveness_get(dev);
1079 hw->readiness = mei_txe_readiness_get(dev);
1080
1081
1082
1083
1084
1085 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1086 dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1087
1088
1089 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1090 dev_dbg(dev->dev, "we need to start the dev.\n");
1091 dev->recvd_hw_ready = true;
1092 } else {
1093 dev->recvd_hw_ready = false;
1094 if (dev->dev_state != MEI_DEV_RESETTING) {
1095
1096 dev_warn(dev->dev, "FW not ready: resetting.\n");
1097 schedule_work(&dev->reset_work);
1098 goto end;
1099
1100 }
1101 }
1102 wake_up(&dev->wait_hw_ready);
1103 }
1104
1105
1106
1107
1108
1109
1110
1111 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1112
1113 dev_dbg(dev->dev,
1114 "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1115 dev->pg_event = MEI_PG_EVENT_RECEIVED;
1116 if (waitqueue_active(&hw->wait_aliveness_resp))
1117 wake_up(&hw->wait_aliveness_resp);
1118 }
1119
1120
1121
1122
1123
1124 slots = mei_count_full_read_slots(dev);
1125 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1126
1127 rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1128 if (rets &&
1129 (dev->dev_state != MEI_DEV_RESETTING &&
1130 dev->dev_state != MEI_DEV_POWER_DOWN)) {
1131 dev_err(dev->dev,
1132 "mei_irq_read_handler ret = %d.\n", rets);
1133
1134 schedule_work(&dev->reset_work);
1135 goto end;
1136 }
1137 }
1138
1139 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1140 dev->hbuf_is_ready = true;
1141 hw->slots = TXE_HBUF_DEPTH;
1142 }
1143
1144 if (hw->aliveness && dev->hbuf_is_ready) {
1145
1146 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1147 rets = mei_irq_write_handler(dev, &cmpl_list);
1148 if (rets && rets != -EMSGSIZE)
1149 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1150 rets);
1151 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1152 }
1153
1154 mei_irq_compl_handler(dev, &cmpl_list);
1155
1156end:
1157 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1158
1159 mutex_unlock(&dev->device_lock);
1160
1161 mei_enable_interrupts(dev);
1162 return IRQ_HANDLED;
1163}
1164
1165static const struct mei_hw_ops mei_txe_hw_ops = {
1166
1167 .host_is_ready = mei_txe_host_is_ready,
1168
1169 .fw_status = mei_txe_fw_status,
1170 .pg_state = mei_txe_pg_state,
1171
1172 .hw_is_ready = mei_txe_hw_is_ready,
1173 .hw_reset = mei_txe_hw_reset,
1174 .hw_config = mei_txe_hw_config,
1175 .hw_start = mei_txe_hw_start,
1176
1177 .pg_in_transition = mei_txe_pg_in_transition,
1178 .pg_is_enabled = mei_txe_pg_is_enabled,
1179
1180 .intr_clear = mei_txe_intr_clear,
1181 .intr_enable = mei_txe_intr_enable,
1182 .intr_disable = mei_txe_intr_disable,
1183 .synchronize_irq = mei_txe_synchronize_irq,
1184
1185 .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1186 .hbuf_is_ready = mei_txe_is_input_ready,
1187 .hbuf_depth = mei_txe_hbuf_depth,
1188
1189 .write = mei_txe_write,
1190
1191 .rdbuf_full_slots = mei_txe_count_full_read_slots,
1192 .read_hdr = mei_txe_read_hdr,
1193
1194 .read = mei_txe_read,
1195
1196};
1197
1198
1199
1200
1201
1202
1203
1204
1205struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1206{
1207 struct mei_device *dev;
1208 struct mei_txe_hw *hw;
1209
1210 dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) +
1211 sizeof(struct mei_txe_hw), GFP_KERNEL);
1212 if (!dev)
1213 return NULL;
1214
1215 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1216
1217 hw = to_txe_hw(dev);
1218
1219 init_waitqueue_head(&hw->wait_aliveness_resp);
1220
1221 return dev;
1222}
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1234{
1235 struct mei_txe_hw *hw = to_txe_hw(dev);
1236
1237 u32 lo32 = lower_32_bits(addr);
1238 u32 hi32 = upper_32_bits(addr);
1239 u32 ctrl;
1240
1241
1242 if (hi32 & ~0xF)
1243 return -EINVAL;
1244
1245
1246 if (lo32 & 0xF)
1247 return -EINVAL;
1248
1249
1250 if (range & 0x4)
1251 return -EINVAL;
1252
1253
1254 if (range > SATT_RANGE_MAX)
1255 return -EINVAL;
1256
1257 ctrl = SATT2_CTRL_VALID_MSK;
1258 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1259
1260 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1261 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1262 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1263 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1264 range, lo32, ctrl);
1265
1266 return 0;
1267}
1268