linux/drivers/net/ethernet/3com/3c59x.c
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   1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
   2/*
   3        Written 1996-1999 by Donald Becker.
   4
   5        This software may be used and distributed according to the terms
   6        of the GNU General Public License, incorporated herein by reference.
   7
   8        This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
   9        Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
  10        and the EtherLink XL 3c900 and 3c905 cards.
  11
  12        Problem reports and questions should be directed to
  13        vortex@scyld.com
  14
  15        The author may be reached as becker@scyld.com, or C/O
  16        Scyld Computing Corporation
  17        410 Severn Ave., Suite 210
  18        Annapolis MD 21403
  19
  20*/
  21
  22/*
  23 * FIXME: This driver _could_ support MTU changing, but doesn't.  See Don's hamachi.c implementation
  24 * as well as other drivers
  25 *
  26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
  27 * due to dead code elimination.  There will be some performance benefits from this due to
  28 * elimination of all the tests and reduced cache footprint.
  29 */
  30
  31
  32#define DRV_NAME        "3c59x"
  33
  34
  35
  36/* A few values that may be tweaked. */
  37/* Keep the ring sizes a power of two for efficiency. */
  38#define TX_RING_SIZE    16
  39#define RX_RING_SIZE    32
  40#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/
  41
  42/* "Knobs" that adjust features and parameters. */
  43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  44   Setting to > 1512 effectively disables this feature. */
  45#ifndef __arm__
  46static int rx_copybreak = 200;
  47#else
  48/* ARM systems perform better by disregarding the bus-master
  49   transfer capability of these cards. -- rmk */
  50static int rx_copybreak = 1513;
  51#endif
  52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
  53static const int mtu = 1500;
  54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55static int max_interrupt_work = 32;
  56/* Tx timeout interval (millisecs) */
  57static int watchdog = 5000;
  58
  59/* Allow aggregation of Tx interrupts.  Saves CPU load at the cost
  60 * of possible Tx stalls if the system is blocking interrupts
  61 * somewhere else.  Undefine this to disable.
  62 */
  63#define tx_interrupt_mitigation 1
  64
  65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
  66#define vortex_debug debug
  67#ifdef VORTEX_DEBUG
  68static int vortex_debug = VORTEX_DEBUG;
  69#else
  70static int vortex_debug = 1;
  71#endif
  72
  73#include <linux/module.h>
  74#include <linux/kernel.h>
  75#include <linux/string.h>
  76#include <linux/timer.h>
  77#include <linux/errno.h>
  78#include <linux/in.h>
  79#include <linux/ioport.h>
  80#include <linux/interrupt.h>
  81#include <linux/pci.h>
  82#include <linux/mii.h>
  83#include <linux/init.h>
  84#include <linux/netdevice.h>
  85#include <linux/etherdevice.h>
  86#include <linux/skbuff.h>
  87#include <linux/ethtool.h>
  88#include <linux/highmem.h>
  89#include <linux/eisa.h>
  90#include <linux/bitops.h>
  91#include <linux/jiffies.h>
  92#include <linux/gfp.h>
  93#include <asm/irq.h>                    /* For nr_irqs only. */
  94#include <asm/io.h>
  95#include <linux/uaccess.h>
  96
  97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
  98   This is only in the support-all-kernels source code. */
  99
 100#define RUN_AT(x) (jiffies + (x))
 101
 102#include <linux/delay.h>
 103
 104
 105static const char version[] =
 106        DRV_NAME ": Donald Becker and others.\n";
 107
 108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
 110MODULE_LICENSE("GPL");
 111
 112
 113/* Operational parameter that usually are not changed. */
 114
 115/* The Vortex size is twice that of the original EtherLinkIII series: the
 116   runtime register window, window 1, is now always mapped in.
 117   The Boomerang size is twice as large as the Vortex -- it has additional
 118   bus master control registers. */
 119#define VORTEX_TOTAL_SIZE 0x20
 120#define BOOMERANG_TOTAL_SIZE 0x40
 121
 122/* Set iff a MII transceiver on any interface requires mdio preamble.
 123   This only set with the original DP83840 on older 3c905 boards, so the extra
 124   code size of a per-interface flag is not worthwhile. */
 125static char mii_preamble_required;
 126
 127#define PFX DRV_NAME ": "
 128
 129
 130
 131/*
 132                                Theory of Operation
 133
 134I. Board Compatibility
 135
 136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
 137XL, 3Com's PCI to 10/100baseT adapters.  It also works with the 10Mbs
 138versions of the FastEtherLink cards.  The supported product IDs are
 139  3c590, 3c592, 3c595, 3c597, 3c900, 3c905
 140
 141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
 142with the kernel source or available from
 143    cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
 144
 145II. Board-specific settings
 146
 147PCI bus devices are configured by the system at boot time, so no jumpers
 148need to be set on the board.  The system BIOS should be set to assign the
 149PCI INTA signal to an otherwise unused system IRQ line.
 150
 151The EEPROM settings for media type and forced-full-duplex are observed.
 152The EEPROM media type should be left at the default "autoselect" unless using
 15310base2 or AUI connections which cannot be reliably detected.
 154
 155III. Driver operation
 156
 157The 3c59x series use an interface that's very similar to the previous 3c5x9
 158series.  The primary interface is two programmed-I/O FIFOs, with an
 159alternate single-contiguous-region bus-master transfer (see next).
 160
 161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
 162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
 163DEC Tulip and Intel Speedo3.  The first chip version retains a compatible
 164programmed-I/O interface that has been removed in 'B' and subsequent board
 165revisions.
 166
 167One extension that is advertised in a very large font is that the adapters
 168are capable of being bus masters.  On the Vortex chip this capability was
 169only for a single contiguous region making it far less useful than the full
 170bus master capability.  There is a significant performance impact of taking
 171an extra interrupt or polling for the completion of each transfer, as well
 172as difficulty sharing the single transfer engine between the transmit and
 173receive threads.  Using DMA transfers is a win only with large blocks or
 174with the flawed versions of the Intel Orion motherboard PCI controller.
 175
 176The Boomerang chip's full-bus-master interface is useful, and has the
 177currently-unused advantages over other similar chips that queued transmit
 178packets may be reordered and receive buffer groups are associated with a
 179single frame.
 180
 181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
 182Rather than a fixed intermediate receive buffer, this scheme allocates
 183full-sized skbuffs as receive buffers.  The value RX_COPYBREAK is used as
 184the copying breakpoint: it is chosen to trade-off the memory wasted by
 185passing the full-sized skbuff to the queue layer for all frames vs. the
 186copying cost of copying a frame to a correctly-sized skbuff.
 187
 188IIIC. Synchronization
 189The driver runs as two independent, single-threaded flows of control.  One
 190is the send-packet routine, which enforces single-threaded use by the
 191dev->tbusy flag.  The other thread is the interrupt handler, which is single
 192threaded by the hardware and other software.
 193
 194IV. Notes
 195
 196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
 1973c590, 3c595, and 3c900 boards.
 198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
 199the EISA version is called "Demon".  According to Terry these names come
 200from rides at the local amusement park.
 201
 202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
 203This driver only supports ethernet packets because of the skbuff allocation
 204limit of 4K.
 205*/
 206
 207/* This table drives the PCI probe routines.  It's mostly boilerplate in all
 208   of the drivers, and will likely be provided by some future kernel.
 209*/
 210enum pci_flags_bit {
 211        PCI_USES_MASTER=4,
 212};
 213
 214enum {  IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
 215        EEPROM_8BIT=0x10,       /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
 216        HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
 217        INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
 218        EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
 219        EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
 220
 221enum vortex_chips {
 222        CH_3C590 = 0,
 223        CH_3C592,
 224        CH_3C597,
 225        CH_3C595_1,
 226        CH_3C595_2,
 227
 228        CH_3C595_3,
 229        CH_3C900_1,
 230        CH_3C900_2,
 231        CH_3C900_3,
 232        CH_3C900_4,
 233
 234        CH_3C900_5,
 235        CH_3C900B_FL,
 236        CH_3C905_1,
 237        CH_3C905_2,
 238        CH_3C905B_TX,
 239        CH_3C905B_1,
 240
 241        CH_3C905B_2,
 242        CH_3C905B_FX,
 243        CH_3C905C,
 244        CH_3C9202,
 245        CH_3C980,
 246        CH_3C9805,
 247
 248        CH_3CSOHO100_TX,
 249        CH_3C555,
 250        CH_3C556,
 251        CH_3C556B,
 252        CH_3C575,
 253
 254        CH_3C575_1,
 255        CH_3CCFE575,
 256        CH_3CCFE575CT,
 257        CH_3CCFE656,
 258        CH_3CCFEM656,
 259
 260        CH_3CCFEM656_1,
 261        CH_3C450,
 262        CH_3C920,
 263        CH_3C982A,
 264        CH_3C982B,
 265
 266        CH_905BT4,
 267        CH_920B_EMB_WNM,
 268};
 269
 270
 271/* note: this array directly indexed by above enums, and MUST
 272 * be kept in sync with both the enums above, and the PCI device
 273 * table below
 274 */
 275static struct vortex_chip_info {
 276        const char *name;
 277        int flags;
 278        int drv_flags;
 279        int io_size;
 280} vortex_info_tbl[] = {
 281        {"3c590 Vortex 10Mbps",
 282         PCI_USES_MASTER, IS_VORTEX, 32, },
 283        {"3c592 EISA 10Mbps Demon/Vortex",                                      /* AKPM: from Don's 3c59x_cb.c 0.49H */
 284         PCI_USES_MASTER, IS_VORTEX, 32, },
 285        {"3c597 EISA Fast Demon/Vortex",                                        /* AKPM: from Don's 3c59x_cb.c 0.49H */
 286         PCI_USES_MASTER, IS_VORTEX, 32, },
 287        {"3c595 Vortex 100baseTx",
 288         PCI_USES_MASTER, IS_VORTEX, 32, },
 289        {"3c595 Vortex 100baseT4",
 290         PCI_USES_MASTER, IS_VORTEX, 32, },
 291
 292        {"3c595 Vortex 100base-MII",
 293         PCI_USES_MASTER, IS_VORTEX, 32, },
 294        {"3c900 Boomerang 10baseT",
 295         PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
 296        {"3c900 Boomerang 10Mbps Combo",
 297         PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
 298        {"3c900 Cyclone 10Mbps TPO",                                            /* AKPM: from Don's 0.99M */
 299         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 300        {"3c900 Cyclone 10Mbps Combo",
 301         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 302
 303        {"3c900 Cyclone 10Mbps TPC",                                            /* AKPM: from Don's 0.99M */
 304         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 305        {"3c900B-FL Cyclone 10base-FL",
 306         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 307        {"3c905 Boomerang 100baseTx",
 308         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
 309        {"3c905 Boomerang 100baseT4",
 310         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
 311        {"3C905B-TX Fast Etherlink XL PCI",
 312         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 313        {"3c905B Cyclone 100baseTx",
 314         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 315
 316        {"3c905B Cyclone 10/100/BNC",
 317         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
 318        {"3c905B-FX Cyclone 100baseFx",
 319         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
 320        {"3c905C Tornado",
 321        PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 322        {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
 323         PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
 324        {"3c980 Cyclone",
 325         PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 326
 327        {"3c980C Python-T",
 328         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
 329        {"3cSOHO100-TX Hurricane",
 330         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 331        {"3c555 Laptop Hurricane",
 332         PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
 333        {"3c556 Laptop Tornado",
 334         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
 335                                                                        HAS_HWCKSM, 128, },
 336        {"3c556B Laptop Hurricane",
 337         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
 338                                        WNO_XCVR_PWR|HAS_HWCKSM, 128, },
 339
 340        {"3c575 [Megahertz] 10/100 LAN  CardBus",
 341        PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
 342        {"3c575 Boomerang CardBus",
 343         PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
 344        {"3CCFE575BT Cyclone CardBus",
 345         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
 346                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },
 347        {"3CCFE575CT Tornado CardBus",
 348         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 349                                                                        MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
 350        {"3CCFE656 Cyclone CardBus",
 351         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 352                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },
 353
 354        {"3CCFEM656B Cyclone+Winmodem CardBus",
 355         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 356                                                                        INVERT_LED_PWR|HAS_HWCKSM, 128, },
 357        {"3CXFEM656C Tornado+Winmodem CardBus",                 /* From pcmcia-cs-3.1.5 */
 358         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
 359                                                                        MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
 360        {"3c450 HomePNA Tornado",                                               /* AKPM: from Don's 0.99Q */
 361         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
 362        {"3c920 Tornado",
 363         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
 364        {"3c982 Hydra Dual Port A",
 365         PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
 366
 367        {"3c982 Hydra Dual Port B",
 368         PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
 369        {"3c905B-T4",
 370         PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
 371        {"3c920B-EMB-WNM Tornado",
 372         PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
 373
 374        {NULL,}, /* NULL terminated list. */
 375};
 376
 377
 378static const struct pci_device_id vortex_pci_tbl[] = {
 379        { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
 380        { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
 381        { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
 382        { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
 383        { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
 384
 385        { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
 386        { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
 387        { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
 388        { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
 389        { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
 390
 391        { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
 392        { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
 393        { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
 394        { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
 395        { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
 396        { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
 397
 398        { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
 399        { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
 400        { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
 401        { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
 402        { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
 403        { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
 404
 405        { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
 406        { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
 407        { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
 408        { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
 409        { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
 410
 411        { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
 412        { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
 413        { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
 414        { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
 415        { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
 416
 417        { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
 418        { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
 419        { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
 420        { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
 421        { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
 422
 423        { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
 424        { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
 425
 426        {0,}                                            /* 0 terminated list. */
 427};
 428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
 429
 430
 431/* Operational definitions.
 432   These are not used by other compilation units and thus are not
 433   exported in a ".h" file.
 434
 435   First the windows.  There are eight register windows, with the command
 436   and status registers available in each.
 437   */
 438#define EL3_CMD 0x0e
 439#define EL3_STATUS 0x0e
 440
 441/* The top five bits written to EL3_CMD are a command, the lower
 442   11 bits are the parameter, if applicable.
 443   Note that 11 parameters bits was fine for ethernet, but the new chip
 444   can handle FDDI length frames (~4500 octets) and now parameters count
 445   32-bit 'Dwords' rather than octets. */
 446
 447enum vortex_cmd {
 448        TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
 449        RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
 450        UpStall = 6<<11, UpUnstall = (6<<11)+1,
 451        DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
 452        RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
 453        FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
 454        SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
 455        SetTxThreshold = 18<<11, SetTxStart = 19<<11,
 456        StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
 457        StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
 458
 459/* The SetRxFilter command accepts the following classes: */
 460enum RxFilter {
 461        RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
 462
 463/* Bits in the general status register. */
 464enum vortex_status {
 465        IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
 466        TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
 467        IntReq = 0x0040, StatsFull = 0x0080,
 468        DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
 469        DMAInProgress = 1<<11,                  /* DMA controller is still busy.*/
 470        CmdInProgress = 1<<12,                  /* EL3_CMD is still busy.*/
 471};
 472
 473/* Register window 1 offsets, the window used in normal operation.
 474   On the Vortex this window is always mapped at offsets 0x10-0x1f. */
 475enum Window1 {
 476        TX_FIFO = 0x10,  RX_FIFO = 0x10,  RxErrors = 0x14,
 477        RxStatus = 0x18,  Timer=0x1A, TxStatus = 0x1B,
 478        TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
 479};
 480enum Window0 {
 481        Wn0EepromCmd = 10,              /* Window 0: EEPROM command register. */
 482        Wn0EepromData = 12,             /* Window 0: EEPROM results register. */
 483        IntrStatus=0x0E,                /* Valid in all windows. */
 484};
 485enum Win0_EEPROM_bits {
 486        EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
 487        EEPROM_EWENB = 0x30,            /* Enable erasing/writing for 10 msec. */
 488        EEPROM_EWDIS = 0x00,            /* Disable EWENB before 10 msec timeout. */
 489};
 490/* EEPROM locations. */
 491enum eeprom_offset {
 492        PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
 493        EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
 494        NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
 495        DriverTune=13, Checksum=15};
 496
 497enum Window2 {                  /* Window 2. */
 498        Wn2_ResetOptions=12,
 499};
 500enum Window3 {                  /* Window 3: MAC/config bits. */
 501        Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
 502};
 503
 504#define BFEXT(value, offset, bitcount)  \
 505    ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
 506
 507#define BFINS(lhs, rhs, offset, bitcount)                                       \
 508        (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |   \
 509        (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
 510
 511#define RAM_SIZE(v)             BFEXT(v, 0, 3)
 512#define RAM_WIDTH(v)    BFEXT(v, 3, 1)
 513#define RAM_SPEED(v)    BFEXT(v, 4, 2)
 514#define ROM_SIZE(v)             BFEXT(v, 6, 2)
 515#define RAM_SPLIT(v)    BFEXT(v, 16, 2)
 516#define XCVR(v)                 BFEXT(v, 20, 4)
 517#define AUTOSELECT(v)   BFEXT(v, 24, 1)
 518
 519enum Window4 {          /* Window 4: Xcvr/media bits. */
 520        Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
 521};
 522enum Win4_Media_bits {
 523        Media_SQE = 0x0008,             /* Enable SQE error counting for AUI. */
 524        Media_10TP = 0x00C0,    /* Enable link beat and jabber for 10baseT. */
 525        Media_Lnk = 0x0080,             /* Enable just link beat for 100TX/100FX. */
 526        Media_LnkBeat = 0x0800,
 527};
 528enum Window7 {                                  /* Window 7: Bus Master control. */
 529        Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
 530        Wn7_MasterStatus = 12,
 531};
 532/* Boomerang bus master control registers. */
 533enum MasterCtrl {
 534        PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
 535        TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
 536};
 537
 538/* The Rx and Tx descriptor lists.
 539   Caution Alpha hackers: these types are 32 bits!  Note also the 8 byte
 540   alignment contraint on tx_ring[] and rx_ring[]. */
 541#define LAST_FRAG       0x80000000                      /* Last Addr/Len pair in descriptor. */
 542#define DN_COMPLETE     0x00010000                      /* This packet has been downloaded */
 543struct boom_rx_desc {
 544        __le32 next;                                    /* Last entry points to 0.   */
 545        __le32 status;
 546        __le32 addr;                                    /* Up to 63 addr/len pairs possible. */
 547        __le32 length;                                  /* Set LAST_FRAG to indicate last pair. */
 548};
 549/* Values for the Rx status entry. */
 550enum rx_desc_status {
 551        RxDComplete=0x00008000, RxDError=0x4000,
 552        /* See boomerang_rx() for actual error bits */
 553        IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
 554        IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
 555};
 556
 557#ifdef MAX_SKB_FRAGS
 558#define DO_ZEROCOPY 1
 559#else
 560#define DO_ZEROCOPY 0
 561#endif
 562
 563struct boom_tx_desc {
 564        __le32 next;                                    /* Last entry points to 0.   */
 565        __le32 status;                                  /* bits 0:12 length, others see below.  */
 566#if DO_ZEROCOPY
 567        struct {
 568                __le32 addr;
 569                __le32 length;
 570        } frag[1+MAX_SKB_FRAGS];
 571#else
 572                __le32 addr;
 573                __le32 length;
 574#endif
 575};
 576
 577/* Values for the Tx status entry. */
 578enum tx_desc_status {
 579        CRCDisable=0x2000, TxDComplete=0x8000,
 580        AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
 581        TxIntrUploaded=0x80000000,              /* IRQ when in FIFO, but maybe not sent. */
 582};
 583
 584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
 585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
 586
 587struct vortex_extra_stats {
 588        unsigned long tx_deferred;
 589        unsigned long tx_max_collisions;
 590        unsigned long tx_multiple_collisions;
 591        unsigned long tx_single_collisions;
 592        unsigned long rx_bad_ssd;
 593};
 594
 595struct vortex_private {
 596        /* The Rx and Tx rings should be quad-word-aligned. */
 597        struct boom_rx_desc* rx_ring;
 598        struct boom_tx_desc* tx_ring;
 599        dma_addr_t rx_ring_dma;
 600        dma_addr_t tx_ring_dma;
 601        /* The addresses of transmit- and receive-in-place skbuffs. */
 602        struct sk_buff* rx_skbuff[RX_RING_SIZE];
 603        struct sk_buff* tx_skbuff[TX_RING_SIZE];
 604        unsigned int cur_rx, cur_tx;            /* The next free ring entry */
 605        unsigned int dirty_tx;  /* The ring entries to be free()ed. */
 606        struct vortex_extra_stats xstats;       /* NIC-specific extra stats */
 607        struct sk_buff *tx_skb;                         /* Packet being eaten by bus master ctrl.  */
 608        dma_addr_t tx_skb_dma;                          /* Allocated DMA address for bus master ctrl DMA.   */
 609
 610        /* PCI configuration space information. */
 611        struct device *gendev;
 612        void __iomem *ioaddr;                   /* IO address space */
 613        void __iomem *cb_fn_base;               /* CardBus function status addr space. */
 614
 615        /* Some values here only for performance evaluation and path-coverage */
 616        int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
 617        int card_idx;
 618
 619        /* The remainder are related to chip state, mostly media selection. */
 620        struct timer_list timer;                        /* Media selection timer. */
 621        int options;                                            /* User-settable misc. driver options. */
 622        unsigned int media_override:4,          /* Passed-in media type. */
 623                default_media:4,                                /* Read from the EEPROM/Wn3_Config. */
 624                full_duplex:1, autoselect:1,
 625                bus_master:1,                                   /* Vortex can only do a fragment bus-m. */
 626                full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang  */
 627                flow_ctrl:1,                                    /* Use 802.3x flow control (PAUSE only) */
 628                partner_flow_ctrl:1,                    /* Partner supports flow control */
 629                has_nway:1,
 630                enable_wol:1,                                   /* Wake-on-LAN is enabled */
 631                pm_state_valid:1,                               /* pci_dev->saved_config_space has sane contents */
 632                open:1,
 633                medialock:1,
 634                large_frames:1,                 /* accept large frames */
 635                handling_irq:1;                 /* private in_irq indicator */
 636        /* {get|set}_wol operations are already serialized by rtnl.
 637         * no additional locking is required for the enable_wol and acpi_set_WOL()
 638         */
 639        int drv_flags;
 640        u16 status_enable;
 641        u16 intr_enable;
 642        u16 available_media;                            /* From Wn3_Options. */
 643        u16 capabilities, info1, info2;         /* Various, from EEPROM. */
 644        u16 advertising;                                        /* NWay media advertisement */
 645        unsigned char phys[2];                          /* MII device addresses. */
 646        u16 deferred;                                           /* Resend these interrupts when we
 647                                                                                 * bale from the ISR */
 648        u16 io_size;                                            /* Size of PCI region (for release_region) */
 649
 650        /* Serialises access to hardware other than MII and variables below.
 651         * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
 652        spinlock_t lock;
 653
 654        spinlock_t mii_lock;            /* Serialises access to MII */
 655        struct mii_if_info mii;         /* MII lib hooks/info */
 656        spinlock_t window_lock;         /* Serialises access to windowed regs */
 657        int window;                     /* Register window */
 658};
 659
 660static void window_set(struct vortex_private *vp, int window)
 661{
 662        if (window != vp->window) {
 663                iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
 664                vp->window = window;
 665        }
 666}
 667
 668#define DEFINE_WINDOW_IO(size)                                          \
 669static u ## size                                                        \
 670window_read ## size(struct vortex_private *vp, int window, int addr)    \
 671{                                                                       \
 672        unsigned long flags;                                            \
 673        u ## size ret;                                                  \
 674        spin_lock_irqsave(&vp->window_lock, flags);                     \
 675        window_set(vp, window);                                         \
 676        ret = ioread ## size(vp->ioaddr + addr);                        \
 677        spin_unlock_irqrestore(&vp->window_lock, flags);                \
 678        return ret;                                                     \
 679}                                                                       \
 680static void                                                             \
 681window_write ## size(struct vortex_private *vp, u ## size value,        \
 682                     int window, int addr)                              \
 683{                                                                       \
 684        unsigned long flags;                                            \
 685        spin_lock_irqsave(&vp->window_lock, flags);                     \
 686        window_set(vp, window);                                         \
 687        iowrite ## size(value, vp->ioaddr + addr);                      \
 688        spin_unlock_irqrestore(&vp->window_lock, flags);                \
 689}
 690DEFINE_WINDOW_IO(8)
 691DEFINE_WINDOW_IO(16)
 692DEFINE_WINDOW_IO(32)
 693
 694#ifdef CONFIG_PCI
 695#define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
 696#else
 697#define DEVICE_PCI(dev) NULL
 698#endif
 699
 700#define VORTEX_PCI(vp)                                                  \
 701        ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
 702
 703#ifdef CONFIG_EISA
 704#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
 705#else
 706#define DEVICE_EISA(dev) NULL
 707#endif
 708
 709#define VORTEX_EISA(vp)                                                 \
 710        ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
 711
 712/* The action to take with a media selection timer tick.
 713   Note that we deviate from the 3Com order by checking 10base2 before AUI.
 714 */
 715enum xcvr_types {
 716        XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
 717        XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
 718};
 719
 720static const struct media_table {
 721        char *name;
 722        unsigned int media_bits:16,             /* Bits to set in Wn4_Media register. */
 723                mask:8,                                         /* The transceiver-present bit in Wn3_Config.*/
 724                next:8;                                         /* The media type to try next. */
 725        int wait;                                               /* Time before we check media status. */
 726} media_tbl[] = {
 727  {     "10baseT",   Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
 728  { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
 729  { "undefined", 0,                     0x80, XCVR_10baseT, 10000},
 730  { "10base2",   0,                     0x10, XCVR_AUI,         (1*HZ)/10},
 731  { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
 732  { "100baseFX", Media_Lnk, 0x04, XCVR_MII,             (14*HZ)/10},
 733  { "MII",               0,                     0x41, XCVR_10baseT, 3*HZ },
 734  { "undefined", 0,                     0x01, XCVR_10baseT, 10000},
 735  { "Autonegotiate", 0,         0x41, XCVR_10baseT, 3*HZ},
 736  { "MII-External",      0,             0x41, XCVR_10baseT, 3*HZ },
 737  { "Default",   0,                     0xFF, XCVR_10baseT, 10000},
 738};
 739
 740static struct {
 741        const char str[ETH_GSTRING_LEN];
 742} ethtool_stats_keys[] = {
 743        { "tx_deferred" },
 744        { "tx_max_collisions" },
 745        { "tx_multiple_collisions" },
 746        { "tx_single_collisions" },
 747        { "rx_bad_ssd" },
 748};
 749
 750/* number of ETHTOOL_GSTATS u64's */
 751#define VORTEX_NUM_STATS    5
 752
 753static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
 754                                   int chip_idx, int card_idx);
 755static int vortex_up(struct net_device *dev);
 756static void vortex_down(struct net_device *dev, int final);
 757static int vortex_open(struct net_device *dev);
 758static void mdio_sync(struct vortex_private *vp, int bits);
 759static int mdio_read(struct net_device *dev, int phy_id, int location);
 760static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
 761static void vortex_timer(struct timer_list *t);
 762static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
 763                                     struct net_device *dev);
 764static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
 765                                        struct net_device *dev);
 766static int vortex_rx(struct net_device *dev);
 767static int boomerang_rx(struct net_device *dev);
 768static irqreturn_t vortex_boomerang_interrupt(int irq, void *dev_id);
 769static irqreturn_t _vortex_interrupt(int irq, struct net_device *dev);
 770static irqreturn_t _boomerang_interrupt(int irq, struct net_device *dev);
 771static int vortex_close(struct net_device *dev);
 772static void dump_tx_ring(struct net_device *dev);
 773static void update_stats(void __iomem *ioaddr, struct net_device *dev);
 774static struct net_device_stats *vortex_get_stats(struct net_device *dev);
 775static void set_rx_mode(struct net_device *dev);
 776#ifdef CONFIG_PCI
 777static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 778#endif
 779static void vortex_tx_timeout(struct net_device *dev);
 780static void acpi_set_WOL(struct net_device *dev);
 781static const struct ethtool_ops vortex_ethtool_ops;
 782static void set_8021q_mode(struct net_device *dev, int enable);
 783
 784/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
 785/* Option count limit only -- unlimited interfaces are supported. */
 786#define MAX_UNITS 8
 787static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
 788static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 789static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 790static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 791static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 792static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
 793static int global_options = -1;
 794static int global_full_duplex = -1;
 795static int global_enable_wol = -1;
 796static int global_use_mmio = -1;
 797
 798/* Variables to work-around the Compaq PCI BIOS32 problem. */
 799static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
 800static struct net_device *compaq_net_device;
 801
 802static int vortex_cards_found;
 803
 804module_param(debug, int, 0);
 805module_param(global_options, int, 0);
 806module_param_array(options, int, NULL, 0);
 807module_param(global_full_duplex, int, 0);
 808module_param_array(full_duplex, int, NULL, 0);
 809module_param_array(hw_checksums, int, NULL, 0);
 810module_param_array(flow_ctrl, int, NULL, 0);
 811module_param(global_enable_wol, int, 0);
 812module_param_array(enable_wol, int, NULL, 0);
 813module_param(rx_copybreak, int, 0);
 814module_param(max_interrupt_work, int, 0);
 815module_param_hw(compaq_ioaddr, int, ioport, 0);
 816module_param_hw(compaq_irq, int, irq, 0);
 817module_param(compaq_device_id, int, 0);
 818module_param(watchdog, int, 0);
 819module_param(global_use_mmio, int, 0);
 820module_param_array(use_mmio, int, NULL, 0);
 821MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
 822MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
 823MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
 824MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
 825MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
 826MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
 827MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
 828MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
 829MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
 830MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
 831MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
 832MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
 833MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
 834MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
 835MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
 836MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
 837MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
 838
 839#ifdef CONFIG_NET_POLL_CONTROLLER
 840static void poll_vortex(struct net_device *dev)
 841{
 842        vortex_boomerang_interrupt(dev->irq, dev);
 843}
 844#endif
 845
 846#ifdef CONFIG_PM
 847
 848static int vortex_suspend(struct device *dev)
 849{
 850        struct pci_dev *pdev = to_pci_dev(dev);
 851        struct net_device *ndev = pci_get_drvdata(pdev);
 852
 853        if (!ndev || !netif_running(ndev))
 854                return 0;
 855
 856        netif_device_detach(ndev);
 857        vortex_down(ndev, 1);
 858
 859        return 0;
 860}
 861
 862static int vortex_resume(struct device *dev)
 863{
 864        struct pci_dev *pdev = to_pci_dev(dev);
 865        struct net_device *ndev = pci_get_drvdata(pdev);
 866        int err;
 867
 868        if (!ndev || !netif_running(ndev))
 869                return 0;
 870
 871        err = vortex_up(ndev);
 872        if (err)
 873                return err;
 874
 875        netif_device_attach(ndev);
 876
 877        return 0;
 878}
 879
 880static const struct dev_pm_ops vortex_pm_ops = {
 881        .suspend = vortex_suspend,
 882        .resume = vortex_resume,
 883        .freeze = vortex_suspend,
 884        .thaw = vortex_resume,
 885        .poweroff = vortex_suspend,
 886        .restore = vortex_resume,
 887};
 888
 889#define VORTEX_PM_OPS (&vortex_pm_ops)
 890
 891#else /* !CONFIG_PM */
 892
 893#define VORTEX_PM_OPS NULL
 894
 895#endif /* !CONFIG_PM */
 896
 897#ifdef CONFIG_EISA
 898static const struct eisa_device_id vortex_eisa_ids[] = {
 899        { "TCM5920", CH_3C592 },
 900        { "TCM5970", CH_3C597 },
 901        { "" }
 902};
 903MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
 904
 905static int vortex_eisa_probe(struct device *device)
 906{
 907        void __iomem *ioaddr;
 908        struct eisa_device *edev;
 909
 910        edev = to_eisa_device(device);
 911
 912        if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
 913                return -EBUSY;
 914
 915        ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
 916
 917        if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
 918                                          edev->id.driver_data, vortex_cards_found)) {
 919                release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
 920                return -ENODEV;
 921        }
 922
 923        vortex_cards_found++;
 924
 925        return 0;
 926}
 927
 928static int vortex_eisa_remove(struct device *device)
 929{
 930        struct eisa_device *edev;
 931        struct net_device *dev;
 932        struct vortex_private *vp;
 933        void __iomem *ioaddr;
 934
 935        edev = to_eisa_device(device);
 936        dev = eisa_get_drvdata(edev);
 937
 938        if (!dev) {
 939                pr_err("vortex_eisa_remove called for Compaq device!\n");
 940                BUG();
 941        }
 942
 943        vp = netdev_priv(dev);
 944        ioaddr = vp->ioaddr;
 945
 946        unregister_netdev(dev);
 947        iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
 948        release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
 949
 950        free_netdev(dev);
 951        return 0;
 952}
 953
 954static struct eisa_driver vortex_eisa_driver = {
 955        .id_table = vortex_eisa_ids,
 956        .driver   = {
 957                .name    = "3c59x",
 958                .probe   = vortex_eisa_probe,
 959                .remove  = vortex_eisa_remove
 960        }
 961};
 962
 963#endif /* CONFIG_EISA */
 964
 965/* returns count found (>= 0), or negative on error */
 966static int __init vortex_eisa_init(void)
 967{
 968        int eisa_found = 0;
 969        int orig_cards_found = vortex_cards_found;
 970
 971#ifdef CONFIG_EISA
 972        int err;
 973
 974        err = eisa_driver_register (&vortex_eisa_driver);
 975        if (!err) {
 976                /*
 977                 * Because of the way EISA bus is probed, we cannot assume
 978                 * any device have been found when we exit from
 979                 * eisa_driver_register (the bus root driver may not be
 980                 * initialized yet). So we blindly assume something was
 981                 * found, and let the sysfs magic happened...
 982                 */
 983                eisa_found = 1;
 984        }
 985#endif
 986
 987        /* Special code to work-around the Compaq PCI BIOS32 problem. */
 988        if (compaq_ioaddr) {
 989                vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
 990                              compaq_irq, compaq_device_id, vortex_cards_found++);
 991        }
 992
 993        return vortex_cards_found - orig_cards_found + eisa_found;
 994}
 995
 996/* returns count (>= 0), or negative on error */
 997static int vortex_init_one(struct pci_dev *pdev,
 998                           const struct pci_device_id *ent)
 999{
1000        int rc, unit, pci_bar;
1001        struct vortex_chip_info *vci;
1002        void __iomem *ioaddr;
1003
1004        /* wake up and enable device */
1005        rc = pci_enable_device(pdev);
1006        if (rc < 0)
1007                goto out;
1008
1009        rc = pci_request_regions(pdev, DRV_NAME);
1010        if (rc < 0)
1011                goto out_disable;
1012
1013        unit = vortex_cards_found;
1014
1015        if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1016                /* Determine the default if the user didn't override us */
1017                vci = &vortex_info_tbl[ent->driver_data];
1018                pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1019        } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1020                pci_bar = use_mmio[unit] ? 1 : 0;
1021        else
1022                pci_bar = global_use_mmio ? 1 : 0;
1023
1024        ioaddr = pci_iomap(pdev, pci_bar, 0);
1025        if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1026                ioaddr = pci_iomap(pdev, 0, 0);
1027        if (!ioaddr) {
1028                rc = -ENOMEM;
1029                goto out_release;
1030        }
1031
1032        rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1033                           ent->driver_data, unit);
1034        if (rc < 0)
1035                goto out_iounmap;
1036
1037        vortex_cards_found++;
1038        goto out;
1039
1040out_iounmap:
1041        pci_iounmap(pdev, ioaddr);
1042out_release:
1043        pci_release_regions(pdev);
1044out_disable:
1045        pci_disable_device(pdev);
1046out:
1047        return rc;
1048}
1049
1050static const struct net_device_ops boomrang_netdev_ops = {
1051        .ndo_open               = vortex_open,
1052        .ndo_stop               = vortex_close,
1053        .ndo_start_xmit         = boomerang_start_xmit,
1054        .ndo_tx_timeout         = vortex_tx_timeout,
1055        .ndo_get_stats          = vortex_get_stats,
1056#ifdef CONFIG_PCI
1057        .ndo_do_ioctl           = vortex_ioctl,
1058#endif
1059        .ndo_set_rx_mode        = set_rx_mode,
1060        .ndo_set_mac_address    = eth_mac_addr,
1061        .ndo_validate_addr      = eth_validate_addr,
1062#ifdef CONFIG_NET_POLL_CONTROLLER
1063        .ndo_poll_controller    = poll_vortex,
1064#endif
1065};
1066
1067static const struct net_device_ops vortex_netdev_ops = {
1068        .ndo_open               = vortex_open,
1069        .ndo_stop               = vortex_close,
1070        .ndo_start_xmit         = vortex_start_xmit,
1071        .ndo_tx_timeout         = vortex_tx_timeout,
1072        .ndo_get_stats          = vortex_get_stats,
1073#ifdef CONFIG_PCI
1074        .ndo_do_ioctl           = vortex_ioctl,
1075#endif
1076        .ndo_set_rx_mode        = set_rx_mode,
1077        .ndo_set_mac_address    = eth_mac_addr,
1078        .ndo_validate_addr      = eth_validate_addr,
1079#ifdef CONFIG_NET_POLL_CONTROLLER
1080        .ndo_poll_controller    = poll_vortex,
1081#endif
1082};
1083
1084/*
1085 * Start up the PCI/EISA device which is described by *gendev.
1086 * Return 0 on success.
1087 *
1088 * NOTE: pdev can be NULL, for the case of a Compaq device
1089 */
1090static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1091                         int chip_idx, int card_idx)
1092{
1093        struct vortex_private *vp;
1094        int option;
1095        unsigned int eeprom[0x40], checksum = 0;                /* EEPROM contents */
1096        int i, step;
1097        struct net_device *dev;
1098        static int printed_version;
1099        int retval, print_info;
1100        struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1101        const char *print_name = "3c59x";
1102        struct pci_dev *pdev = NULL;
1103        struct eisa_device *edev = NULL;
1104
1105        if (!printed_version) {
1106                pr_info("%s", version);
1107                printed_version = 1;
1108        }
1109
1110        if (gendev) {
1111                if ((pdev = DEVICE_PCI(gendev))) {
1112                        print_name = pci_name(pdev);
1113                }
1114
1115                if ((edev = DEVICE_EISA(gendev))) {
1116                        print_name = dev_name(&edev->dev);
1117                }
1118        }
1119
1120        dev = alloc_etherdev(sizeof(*vp));
1121        retval = -ENOMEM;
1122        if (!dev)
1123                goto out;
1124
1125        SET_NETDEV_DEV(dev, gendev);
1126        vp = netdev_priv(dev);
1127
1128        option = global_options;
1129
1130        /* The lower four bits are the media type. */
1131        if (dev->mem_start) {
1132                /*
1133                 * The 'options' param is passed in as the third arg to the
1134                 * LILO 'ether=' argument for non-modular use
1135                 */
1136                option = dev->mem_start;
1137        }
1138        else if (card_idx < MAX_UNITS) {
1139                if (options[card_idx] >= 0)
1140                        option = options[card_idx];
1141        }
1142
1143        if (option > 0) {
1144                if (option & 0x8000)
1145                        vortex_debug = 7;
1146                if (option & 0x4000)
1147                        vortex_debug = 2;
1148                if (option & 0x0400)
1149                        vp->enable_wol = 1;
1150        }
1151
1152        print_info = (vortex_debug > 1);
1153        if (print_info)
1154                pr_info("See Documentation/networking/vortex.txt\n");
1155
1156        pr_info("%s: 3Com %s %s at %p.\n",
1157               print_name,
1158               pdev ? "PCI" : "EISA",
1159               vci->name,
1160               ioaddr);
1161
1162        dev->base_addr = (unsigned long)ioaddr;
1163        dev->irq = irq;
1164        dev->mtu = mtu;
1165        vp->ioaddr = ioaddr;
1166        vp->large_frames = mtu > 1500;
1167        vp->drv_flags = vci->drv_flags;
1168        vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1169        vp->io_size = vci->io_size;
1170        vp->card_idx = card_idx;
1171        vp->window = -1;
1172
1173        /* module list only for Compaq device */
1174        if (gendev == NULL) {
1175                compaq_net_device = dev;
1176        }
1177
1178        /* PCI-only startup logic */
1179        if (pdev) {
1180                /* enable bus-mastering if necessary */
1181                if (vci->flags & PCI_USES_MASTER)
1182                        pci_set_master(pdev);
1183
1184                if (vci->drv_flags & IS_VORTEX) {
1185                        u8 pci_latency;
1186                        u8 new_latency = 248;
1187
1188                        /* Check the PCI latency value.  On the 3c590 series the latency timer
1189                           must be set to the maximum value to avoid data corruption that occurs
1190                           when the timer expires during a transfer.  This bug exists the Vortex
1191                           chip only. */
1192                        pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1193                        if (pci_latency < new_latency) {
1194                                pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1195                                        print_name, pci_latency, new_latency);
1196                                pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1197                        }
1198                }
1199        }
1200
1201        spin_lock_init(&vp->lock);
1202        spin_lock_init(&vp->mii_lock);
1203        spin_lock_init(&vp->window_lock);
1204        vp->gendev = gendev;
1205        vp->mii.dev = dev;
1206        vp->mii.mdio_read = mdio_read;
1207        vp->mii.mdio_write = mdio_write;
1208        vp->mii.phy_id_mask = 0x1f;
1209        vp->mii.reg_num_mask = 0x1f;
1210
1211        /* Makes sure rings are at least 16 byte aligned. */
1212        vp->rx_ring = dma_alloc_coherent(gendev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1213                                           + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1214                                           &vp->rx_ring_dma, GFP_KERNEL);
1215        retval = -ENOMEM;
1216        if (!vp->rx_ring)
1217                goto free_device;
1218
1219        vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1220        vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1221
1222        /* if we are a PCI driver, we store info in pdev->driver_data
1223         * instead of a module list */
1224        if (pdev)
1225                pci_set_drvdata(pdev, dev);
1226        if (edev)
1227                eisa_set_drvdata(edev, dev);
1228
1229        vp->media_override = 7;
1230        if (option >= 0) {
1231                vp->media_override = ((option & 7) == 2)  ?  0  :  option & 15;
1232                if (vp->media_override != 7)
1233                        vp->medialock = 1;
1234                vp->full_duplex = (option & 0x200) ? 1 : 0;
1235                vp->bus_master = (option & 16) ? 1 : 0;
1236        }
1237
1238        if (global_full_duplex > 0)
1239                vp->full_duplex = 1;
1240        if (global_enable_wol > 0)
1241                vp->enable_wol = 1;
1242
1243        if (card_idx < MAX_UNITS) {
1244                if (full_duplex[card_idx] > 0)
1245                        vp->full_duplex = 1;
1246                if (flow_ctrl[card_idx] > 0)
1247                        vp->flow_ctrl = 1;
1248                if (enable_wol[card_idx] > 0)
1249                        vp->enable_wol = 1;
1250        }
1251
1252        vp->mii.force_media = vp->full_duplex;
1253        vp->options = option;
1254        /* Read the station address from the EEPROM. */
1255        {
1256                int base;
1257
1258                if (vci->drv_flags & EEPROM_8BIT)
1259                        base = 0x230;
1260                else if (vci->drv_flags & EEPROM_OFFSET)
1261                        base = EEPROM_Read + 0x30;
1262                else
1263                        base = EEPROM_Read;
1264
1265                for (i = 0; i < 0x40; i++) {
1266                        int timer;
1267                        window_write16(vp, base + i, 0, Wn0EepromCmd);
1268                        /* Pause for at least 162 us. for the read to take place. */
1269                        for (timer = 10; timer >= 0; timer--) {
1270                                udelay(162);
1271                                if ((window_read16(vp, 0, Wn0EepromCmd) &
1272                                     0x8000) == 0)
1273                                        break;
1274                        }
1275                        eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1276                }
1277        }
1278        for (i = 0; i < 0x18; i++)
1279                checksum ^= eeprom[i];
1280        checksum = (checksum ^ (checksum >> 8)) & 0xff;
1281        if (checksum != 0x00) {         /* Grrr, needless incompatible change 3Com. */
1282                while (i < 0x21)
1283                        checksum ^= eeprom[i++];
1284                checksum = (checksum ^ (checksum >> 8)) & 0xff;
1285        }
1286        if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1287                pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1288        for (i = 0; i < 3; i++)
1289                ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1290        if (print_info)
1291                pr_cont(" %pM", dev->dev_addr);
1292        /* Unfortunately an all zero eeprom passes the checksum and this
1293           gets found in the wild in failure cases. Crypto is hard 8) */
1294        if (!is_valid_ether_addr(dev->dev_addr)) {
1295                retval = -EINVAL;
1296                pr_err("*** EEPROM MAC address is invalid.\n");
1297                goto free_ring; /* With every pack */
1298        }
1299        for (i = 0; i < 6; i++)
1300                window_write8(vp, dev->dev_addr[i], 2, i);
1301
1302        if (print_info)
1303                pr_cont(", IRQ %d\n", dev->irq);
1304        /* Tell them about an invalid IRQ. */
1305        if (dev->irq <= 0 || dev->irq >= nr_irqs)
1306                pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
1307                        dev->irq);
1308
1309        step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1310        if (print_info) {
1311                pr_info("  product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1312                        eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1313                        step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1314        }
1315
1316
1317        if (pdev && vci->drv_flags & HAS_CB_FNS) {
1318                unsigned short n;
1319
1320                vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1321                if (!vp->cb_fn_base) {
1322                        retval = -ENOMEM;
1323                        goto free_ring;
1324                }
1325
1326                if (print_info) {
1327                        pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1328                                print_name,
1329                                (unsigned long long)pci_resource_start(pdev, 2),
1330                                vp->cb_fn_base);
1331                }
1332
1333                n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1334                if (vp->drv_flags & INVERT_LED_PWR)
1335                        n |= 0x10;
1336                if (vp->drv_flags & INVERT_MII_PWR)
1337                        n |= 0x4000;
1338                window_write16(vp, n, 2, Wn2_ResetOptions);
1339                if (vp->drv_flags & WNO_XCVR_PWR) {
1340                        window_write16(vp, 0x0800, 0, 0);
1341                }
1342        }
1343
1344        /* Extract our information from the EEPROM data. */
1345        vp->info1 = eeprom[13];
1346        vp->info2 = eeprom[15];
1347        vp->capabilities = eeprom[16];
1348
1349        if (vp->info1 & 0x8000) {
1350                vp->full_duplex = 1;
1351                if (print_info)
1352                        pr_info("Full duplex capable\n");
1353        }
1354
1355        {
1356                static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1357                unsigned int config;
1358                vp->available_media = window_read16(vp, 3, Wn3_Options);
1359                if ((vp->available_media & 0xff) == 0)          /* Broken 3c916 */
1360                        vp->available_media = 0x40;
1361                config = window_read32(vp, 3, Wn3_Config);
1362                if (print_info) {
1363                        pr_debug("  Internal config register is %4.4x, transceivers %#x.\n",
1364                                config, window_read16(vp, 3, Wn3_Options));
1365                        pr_info("  %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1366                                   8 << RAM_SIZE(config),
1367                                   RAM_WIDTH(config) ? "word" : "byte",
1368                                   ram_split[RAM_SPLIT(config)],
1369                                   AUTOSELECT(config) ? "autoselect/" : "",
1370                                   XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1371                                   media_tbl[XCVR(config)].name);
1372                }
1373                vp->default_media = XCVR(config);
1374                if (vp->default_media == XCVR_NWAY)
1375                        vp->has_nway = 1;
1376                vp->autoselect = AUTOSELECT(config);
1377        }
1378
1379        if (vp->media_override != 7) {
1380                pr_info("%s:  Media override to transceiver type %d (%s).\n",
1381                                print_name, vp->media_override,
1382                                media_tbl[vp->media_override].name);
1383                dev->if_port = vp->media_override;
1384        } else
1385                dev->if_port = vp->default_media;
1386
1387        if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1388                dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1389                int phy, phy_idx = 0;
1390                mii_preamble_required++;
1391                if (vp->drv_flags & EXTRA_PREAMBLE)
1392                        mii_preamble_required++;
1393                mdio_sync(vp, 32);
1394                mdio_read(dev, 24, MII_BMSR);
1395                for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1396                        int mii_status, phyx;
1397
1398                        /*
1399                         * For the 3c905CX we look at index 24 first, because it bogusly
1400                         * reports an external PHY at all indices
1401                         */
1402                        if (phy == 0)
1403                                phyx = 24;
1404                        else if (phy <= 24)
1405                                phyx = phy - 1;
1406                        else
1407                                phyx = phy;
1408                        mii_status = mdio_read(dev, phyx, MII_BMSR);
1409                        if (mii_status  &&  mii_status != 0xffff) {
1410                                vp->phys[phy_idx++] = phyx;
1411                                if (print_info) {
1412                                        pr_info("  MII transceiver found at address %d, status %4x.\n",
1413                                                phyx, mii_status);
1414                                }
1415                                if ((mii_status & 0x0040) == 0)
1416                                        mii_preamble_required++;
1417                        }
1418                }
1419                mii_preamble_required--;
1420                if (phy_idx == 0) {
1421                        pr_warn("  ***WARNING*** No MII transceivers found!\n");
1422                        vp->phys[0] = 24;
1423                } else {
1424                        vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1425                        if (vp->full_duplex) {
1426                                /* Only advertise the FD media types. */
1427                                vp->advertising &= ~0x02A0;
1428                                mdio_write(dev, vp->phys[0], 4, vp->advertising);
1429                        }
1430                }
1431                vp->mii.phy_id = vp->phys[0];
1432        }
1433
1434        if (vp->capabilities & CapBusMaster) {
1435                vp->full_bus_master_tx = 1;
1436                if (print_info) {
1437                        pr_info("  Enabling bus-master transmits and %s receives.\n",
1438                        (vp->info2 & 1) ? "early" : "whole-frame" );
1439                }
1440                vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1441                vp->bus_master = 0;             /* AKPM: vortex only */
1442        }
1443
1444        /* The 3c59x-specific entries in the device structure. */
1445        if (vp->full_bus_master_tx) {
1446                dev->netdev_ops = &boomrang_netdev_ops;
1447                /* Actually, it still should work with iommu. */
1448                if (card_idx < MAX_UNITS &&
1449                    ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1450                                hw_checksums[card_idx] == 1)) {
1451                        dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1452                }
1453        } else
1454                dev->netdev_ops =  &vortex_netdev_ops;
1455
1456        if (print_info) {
1457                pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1458                                print_name,
1459                                (dev->features & NETIF_F_SG) ? "en":"dis",
1460                                (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1461        }
1462
1463        dev->ethtool_ops = &vortex_ethtool_ops;
1464        dev->watchdog_timeo = (watchdog * HZ) / 1000;
1465
1466        if (pdev) {
1467                vp->pm_state_valid = 1;
1468                pci_save_state(pdev);
1469                acpi_set_WOL(dev);
1470        }
1471        retval = register_netdev(dev);
1472        if (retval == 0)
1473                return 0;
1474
1475free_ring:
1476        dma_free_coherent(&pdev->dev,
1477                sizeof(struct boom_rx_desc) * RX_RING_SIZE +
1478                sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1479                vp->rx_ring, vp->rx_ring_dma);
1480free_device:
1481        free_netdev(dev);
1482        pr_err(PFX "vortex_probe1 fails.  Returns %d\n", retval);
1483out:
1484        return retval;
1485}
1486
1487static void
1488issue_and_wait(struct net_device *dev, int cmd)
1489{
1490        struct vortex_private *vp = netdev_priv(dev);
1491        void __iomem *ioaddr = vp->ioaddr;
1492        int i;
1493
1494        iowrite16(cmd, ioaddr + EL3_CMD);
1495        for (i = 0; i < 2000; i++) {
1496                if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1497                        return;
1498        }
1499
1500        /* OK, that didn't work.  Do it the slow way.  One second */
1501        for (i = 0; i < 100000; i++) {
1502                if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1503                        if (vortex_debug > 1)
1504                                pr_info("%s: command 0x%04x took %d usecs\n",
1505                                           dev->name, cmd, i * 10);
1506                        return;
1507                }
1508                udelay(10);
1509        }
1510        pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1511                           dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1512}
1513
1514static void
1515vortex_set_duplex(struct net_device *dev)
1516{
1517        struct vortex_private *vp = netdev_priv(dev);
1518
1519        pr_info("%s:  setting %s-duplex.\n",
1520                dev->name, (vp->full_duplex) ? "full" : "half");
1521
1522        /* Set the full-duplex bit. */
1523        window_write16(vp,
1524                       ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1525                       (vp->large_frames ? 0x40 : 0) |
1526                       ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1527                        0x100 : 0),
1528                       3, Wn3_MAC_Ctrl);
1529}
1530
1531static void vortex_check_media(struct net_device *dev, unsigned int init)
1532{
1533        struct vortex_private *vp = netdev_priv(dev);
1534        unsigned int ok_to_print = 0;
1535
1536        if (vortex_debug > 3)
1537                ok_to_print = 1;
1538
1539        if (mii_check_media(&vp->mii, ok_to_print, init)) {
1540                vp->full_duplex = vp->mii.full_duplex;
1541                vortex_set_duplex(dev);
1542        } else if (init) {
1543                vortex_set_duplex(dev);
1544        }
1545}
1546
1547static int
1548vortex_up(struct net_device *dev)
1549{
1550        struct vortex_private *vp = netdev_priv(dev);
1551        void __iomem *ioaddr = vp->ioaddr;
1552        unsigned int config;
1553        int i, mii_reg1, mii_reg5, err = 0;
1554
1555        if (VORTEX_PCI(vp)) {
1556                pci_set_power_state(VORTEX_PCI(vp), PCI_D0);    /* Go active */
1557                if (vp->pm_state_valid)
1558                        pci_restore_state(VORTEX_PCI(vp));
1559                err = pci_enable_device(VORTEX_PCI(vp));
1560                if (err) {
1561                        pr_warn("%s: Could not enable device\n", dev->name);
1562                        goto err_out;
1563                }
1564        }
1565
1566        /* Before initializing select the active media port. */
1567        config = window_read32(vp, 3, Wn3_Config);
1568
1569        if (vp->media_override != 7) {
1570                pr_info("%s: Media override to transceiver %d (%s).\n",
1571                           dev->name, vp->media_override,
1572                           media_tbl[vp->media_override].name);
1573                dev->if_port = vp->media_override;
1574        } else if (vp->autoselect) {
1575                if (vp->has_nway) {
1576                        if (vortex_debug > 1)
1577                                pr_info("%s: using NWAY device table, not %d\n",
1578                                                                dev->name, dev->if_port);
1579                        dev->if_port = XCVR_NWAY;
1580                } else {
1581                        /* Find first available media type, starting with 100baseTx. */
1582                        dev->if_port = XCVR_100baseTx;
1583                        while (! (vp->available_media & media_tbl[dev->if_port].mask))
1584                                dev->if_port = media_tbl[dev->if_port].next;
1585                        if (vortex_debug > 1)
1586                                pr_info("%s: first available media type: %s\n",
1587                                        dev->name, media_tbl[dev->if_port].name);
1588                }
1589        } else {
1590                dev->if_port = vp->default_media;
1591                if (vortex_debug > 1)
1592                        pr_info("%s: using default media %s\n",
1593                                dev->name, media_tbl[dev->if_port].name);
1594        }
1595
1596        timer_setup(&vp->timer, vortex_timer, 0);
1597        mod_timer(&vp->timer, RUN_AT(media_tbl[dev->if_port].wait));
1598
1599        if (vortex_debug > 1)
1600                pr_debug("%s: Initial media type %s.\n",
1601                           dev->name, media_tbl[dev->if_port].name);
1602
1603        vp->full_duplex = vp->mii.force_media;
1604        config = BFINS(config, dev->if_port, 20, 4);
1605        if (vortex_debug > 6)
1606                pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1607        window_write32(vp, config, 3, Wn3_Config);
1608
1609        if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1610                mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1611                mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1612                vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1613                vp->mii.full_duplex = vp->full_duplex;
1614
1615                vortex_check_media(dev, 1);
1616        }
1617        else
1618                vortex_set_duplex(dev);
1619
1620        issue_and_wait(dev, TxReset);
1621        /*
1622         * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1623         */
1624        issue_and_wait(dev, RxReset|0x04);
1625
1626
1627        iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1628
1629        if (vortex_debug > 1) {
1630                pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1631                           dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1632        }
1633
1634        /* Set the station address and mask in window 2 each time opened. */
1635        for (i = 0; i < 6; i++)
1636                window_write8(vp, dev->dev_addr[i], 2, i);
1637        for (; i < 12; i+=2)
1638                window_write16(vp, 0, 2, i);
1639
1640        if (vp->cb_fn_base) {
1641                unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1642                if (vp->drv_flags & INVERT_LED_PWR)
1643                        n |= 0x10;
1644                if (vp->drv_flags & INVERT_MII_PWR)
1645                        n |= 0x4000;
1646                window_write16(vp, n, 2, Wn2_ResetOptions);
1647        }
1648
1649        if (dev->if_port == XCVR_10base2)
1650                /* Start the thinnet transceiver. We should really wait 50ms...*/
1651                iowrite16(StartCoax, ioaddr + EL3_CMD);
1652        if (dev->if_port != XCVR_NWAY) {
1653                window_write16(vp,
1654                               (window_read16(vp, 4, Wn4_Media) &
1655                                ~(Media_10TP|Media_SQE)) |
1656                               media_tbl[dev->if_port].media_bits,
1657                               4, Wn4_Media);
1658        }
1659
1660        /* Switch to the stats window, and clear all stats by reading. */
1661        iowrite16(StatsDisable, ioaddr + EL3_CMD);
1662        for (i = 0; i < 10; i++)
1663                window_read8(vp, 6, i);
1664        window_read16(vp, 6, 10);
1665        window_read16(vp, 6, 12);
1666        /* New: On the Vortex we must also clear the BadSSD counter. */
1667        window_read8(vp, 4, 12);
1668        /* ..and on the Boomerang we enable the extra statistics bits. */
1669        window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1670
1671        if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1672                vp->cur_rx = 0;
1673                /* Initialize the RxEarly register as recommended. */
1674                iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1675                iowrite32(0x0020, ioaddr + PktStatus);
1676                iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1677        }
1678        if (vp->full_bus_master_tx) {           /* Boomerang bus master Tx. */
1679                vp->cur_tx = vp->dirty_tx = 0;
1680                if (vp->drv_flags & IS_BOOMERANG)
1681                        iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1682                /* Clear the Rx, Tx rings. */
1683                for (i = 0; i < RX_RING_SIZE; i++)      /* AKPM: this is done in vortex_open, too */
1684                        vp->rx_ring[i].status = 0;
1685                for (i = 0; i < TX_RING_SIZE; i++)
1686                        vp->tx_skbuff[i] = NULL;
1687                iowrite32(0, ioaddr + DownListPtr);
1688        }
1689        /* Set receiver mode: presumably accept b-case and phys addr only. */
1690        set_rx_mode(dev);
1691        /* enable 802.1q tagged frames */
1692        set_8021q_mode(dev, 1);
1693        iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1694
1695        iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1696        iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1697        /* Allow status bits to be seen. */
1698        vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1699                (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1700                (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1701                (vp->bus_master ? DMADone : 0);
1702        vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1703                (vp->full_bus_master_rx ? 0 : RxComplete) |
1704                StatsFull | HostError | TxComplete | IntReq
1705                | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1706        iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1707        /* Ack all pending events, and set active indicator mask. */
1708        iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1709                 ioaddr + EL3_CMD);
1710        iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1711        if (vp->cb_fn_base)                     /* The PCMCIA people are idiots.  */
1712                iowrite32(0x8000, vp->cb_fn_base + 4);
1713        netif_start_queue (dev);
1714        netdev_reset_queue(dev);
1715err_out:
1716        return err;
1717}
1718
1719static int
1720vortex_open(struct net_device *dev)
1721{
1722        struct vortex_private *vp = netdev_priv(dev);
1723        int i;
1724        int retval;
1725        dma_addr_t dma;
1726
1727        /* Use the now-standard shared IRQ implementation. */
1728        if ((retval = request_irq(dev->irq, vortex_boomerang_interrupt, IRQF_SHARED, dev->name, dev))) {
1729                pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1730                goto err;
1731        }
1732
1733        if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1734                if (vortex_debug > 2)
1735                        pr_debug("%s:  Filling in the Rx ring.\n", dev->name);
1736                for (i = 0; i < RX_RING_SIZE; i++) {
1737                        struct sk_buff *skb;
1738                        vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1739                        vp->rx_ring[i].status = 0;      /* Clear complete bit. */
1740                        vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1741
1742                        skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1743                                                 GFP_KERNEL);
1744                        vp->rx_skbuff[i] = skb;
1745                        if (skb == NULL)
1746                                break;                  /* Bad news!  */
1747
1748                        skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1749                        dma = dma_map_single(vp->gendev, skb->data,
1750                                             PKT_BUF_SZ, DMA_FROM_DEVICE);
1751                        if (dma_mapping_error(vp->gendev, dma))
1752                                break;
1753                        vp->rx_ring[i].addr = cpu_to_le32(dma);
1754                }
1755                if (i != RX_RING_SIZE) {
1756                        pr_emerg("%s: no memory for rx ring\n", dev->name);
1757                        retval = -ENOMEM;
1758                        goto err_free_skb;
1759                }
1760                /* Wrap the ring. */
1761                vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1762        }
1763
1764        retval = vortex_up(dev);
1765        if (!retval)
1766                goto out;
1767
1768err_free_skb:
1769        for (i = 0; i < RX_RING_SIZE; i++) {
1770                if (vp->rx_skbuff[i]) {
1771                        dev_kfree_skb(vp->rx_skbuff[i]);
1772                        vp->rx_skbuff[i] = NULL;
1773                }
1774        }
1775        free_irq(dev->irq, dev);
1776err:
1777        if (vortex_debug > 1)
1778                pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1779out:
1780        return retval;
1781}
1782
1783static void
1784vortex_timer(struct timer_list *t)
1785{
1786        struct vortex_private *vp = from_timer(vp, t, timer);
1787        struct net_device *dev = vp->mii.dev;
1788        void __iomem *ioaddr = vp->ioaddr;
1789        int next_tick = 60*HZ;
1790        int ok = 0;
1791        int media_status;
1792
1793        if (vortex_debug > 2) {
1794                pr_debug("%s: Media selection timer tick happened, %s.\n",
1795                           dev->name, media_tbl[dev->if_port].name);
1796                pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1797        }
1798
1799        media_status = window_read16(vp, 4, Wn4_Media);
1800        switch (dev->if_port) {
1801        case XCVR_10baseT:  case XCVR_100baseTx:  case XCVR_100baseFx:
1802                if (media_status & Media_LnkBeat) {
1803                        netif_carrier_on(dev);
1804                        ok = 1;
1805                        if (vortex_debug > 1)
1806                                pr_debug("%s: Media %s has link beat, %x.\n",
1807                                           dev->name, media_tbl[dev->if_port].name, media_status);
1808                } else {
1809                        netif_carrier_off(dev);
1810                        if (vortex_debug > 1) {
1811                                pr_debug("%s: Media %s has no link beat, %x.\n",
1812                                           dev->name, media_tbl[dev->if_port].name, media_status);
1813                        }
1814                }
1815                break;
1816        case XCVR_MII: case XCVR_NWAY:
1817                {
1818                        ok = 1;
1819                        vortex_check_media(dev, 0);
1820                }
1821                break;
1822          default:                                      /* Other media types handled by Tx timeouts. */
1823                if (vortex_debug > 1)
1824                  pr_debug("%s: Media %s has no indication, %x.\n",
1825                                 dev->name, media_tbl[dev->if_port].name, media_status);
1826                ok = 1;
1827        }
1828
1829        if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1830                next_tick = 5*HZ;
1831
1832        if (vp->medialock)
1833                goto leave_media_alone;
1834
1835        if (!ok) {
1836                unsigned int config;
1837
1838                spin_lock_irq(&vp->lock);
1839
1840                do {
1841                        dev->if_port = media_tbl[dev->if_port].next;
1842                } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1843                if (dev->if_port == XCVR_Default) { /* Go back to default. */
1844                  dev->if_port = vp->default_media;
1845                  if (vortex_debug > 1)
1846                        pr_debug("%s: Media selection failing, using default %s port.\n",
1847                                   dev->name, media_tbl[dev->if_port].name);
1848                } else {
1849                        if (vortex_debug > 1)
1850                                pr_debug("%s: Media selection failed, now trying %s port.\n",
1851                                           dev->name, media_tbl[dev->if_port].name);
1852                        next_tick = media_tbl[dev->if_port].wait;
1853                }
1854                window_write16(vp,
1855                               (media_status & ~(Media_10TP|Media_SQE)) |
1856                               media_tbl[dev->if_port].media_bits,
1857                               4, Wn4_Media);
1858
1859                config = window_read32(vp, 3, Wn3_Config);
1860                config = BFINS(config, dev->if_port, 20, 4);
1861                window_write32(vp, config, 3, Wn3_Config);
1862
1863                iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1864                         ioaddr + EL3_CMD);
1865                if (vortex_debug > 1)
1866                        pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1867                /* AKPM: FIXME: Should reset Rx & Tx here.  P60 of 3c90xc.pdf */
1868
1869                spin_unlock_irq(&vp->lock);
1870        }
1871
1872leave_media_alone:
1873        if (vortex_debug > 2)
1874          pr_debug("%s: Media selection timer finished, %s.\n",
1875                         dev->name, media_tbl[dev->if_port].name);
1876
1877        mod_timer(&vp->timer, RUN_AT(next_tick));
1878        if (vp->deferred)
1879                iowrite16(FakeIntr, ioaddr + EL3_CMD);
1880}
1881
1882static void vortex_tx_timeout(struct net_device *dev)
1883{
1884        struct vortex_private *vp = netdev_priv(dev);
1885        void __iomem *ioaddr = vp->ioaddr;
1886
1887        pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1888                   dev->name, ioread8(ioaddr + TxStatus),
1889                   ioread16(ioaddr + EL3_STATUS));
1890        pr_err("  diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1891                        window_read16(vp, 4, Wn4_NetDiag),
1892                        window_read16(vp, 4, Wn4_Media),
1893                        ioread32(ioaddr + PktStatus),
1894                        window_read16(vp, 4, Wn4_FIFODiag));
1895        /* Slight code bloat to be user friendly. */
1896        if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1897                pr_err("%s: Transmitter encountered 16 collisions --"
1898                           " network cable problem?\n", dev->name);
1899        if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1900                pr_err("%s: Interrupt posted but not delivered --"
1901                           " IRQ blocked by another device?\n", dev->name);
1902                /* Bad idea here.. but we might as well handle a few events. */
1903                vortex_boomerang_interrupt(dev->irq, dev);
1904        }
1905
1906        if (vortex_debug > 0)
1907                dump_tx_ring(dev);
1908
1909        issue_and_wait(dev, TxReset);
1910
1911        dev->stats.tx_errors++;
1912        if (vp->full_bus_master_tx) {
1913                pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1914                if (vp->cur_tx - vp->dirty_tx > 0  &&  ioread32(ioaddr + DownListPtr) == 0)
1915                        iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1916                                 ioaddr + DownListPtr);
1917                if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) {
1918                        netif_wake_queue (dev);
1919                        netdev_reset_queue (dev);
1920                }
1921                if (vp->drv_flags & IS_BOOMERANG)
1922                        iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1923                iowrite16(DownUnstall, ioaddr + EL3_CMD);
1924        } else {
1925                dev->stats.tx_dropped++;
1926                netif_wake_queue(dev);
1927                netdev_reset_queue(dev);
1928        }
1929        /* Issue Tx Enable */
1930        iowrite16(TxEnable, ioaddr + EL3_CMD);
1931        netif_trans_update(dev); /* prevent tx timeout */
1932}
1933
1934/*
1935 * Handle uncommon interrupt sources.  This is a separate routine to minimize
1936 * the cache impact.
1937 */
1938static void
1939vortex_error(struct net_device *dev, int status)
1940{
1941        struct vortex_private *vp = netdev_priv(dev);
1942        void __iomem *ioaddr = vp->ioaddr;
1943        int do_tx_reset = 0, reset_mask = 0;
1944        unsigned char tx_status = 0;
1945
1946        if (vortex_debug > 2) {
1947                pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1948        }
1949
1950        if (status & TxComplete) {                      /* Really "TxError" for us. */
1951                tx_status = ioread8(ioaddr + TxStatus);
1952                /* Presumably a tx-timeout. We must merely re-enable. */
1953                if (vortex_debug > 2 ||
1954                    (tx_status != 0x88 && vortex_debug > 0)) {
1955                        pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1956                                   dev->name, tx_status);
1957                        if (tx_status == 0x82) {
1958                                pr_err("Probably a duplex mismatch.  See "
1959                                                "Documentation/networking/vortex.txt\n");
1960                        }
1961                        dump_tx_ring(dev);
1962                }
1963                if (tx_status & 0x14)  dev->stats.tx_fifo_errors++;
1964                if (tx_status & 0x38)  dev->stats.tx_aborted_errors++;
1965                if (tx_status & 0x08)  vp->xstats.tx_max_collisions++;
1966                iowrite8(0, ioaddr + TxStatus);
1967                if (tx_status & 0x30) {                 /* txJabber or txUnderrun */
1968                        do_tx_reset = 1;
1969                } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET))  {      /* maxCollisions */
1970                        do_tx_reset = 1;
1971                        reset_mask = 0x0108;            /* Reset interface logic, but not download logic */
1972                } else {                                /* Merely re-enable the transmitter. */
1973                        iowrite16(TxEnable, ioaddr + EL3_CMD);
1974                }
1975        }
1976
1977        if (status & RxEarly)                           /* Rx early is unused. */
1978                iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1979
1980        if (status & StatsFull) {                       /* Empty statistics. */
1981                static int DoneDidThat;
1982                if (vortex_debug > 4)
1983                        pr_debug("%s: Updating stats.\n", dev->name);
1984                update_stats(ioaddr, dev);
1985                /* HACK: Disable statistics as an interrupt source. */
1986                /* This occurs when we have the wrong media type! */
1987                if (DoneDidThat == 0  &&
1988                        ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1989                        pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
1990                                dev->name);
1991                        iowrite16(SetIntrEnb |
1992                                  (window_read16(vp, 5, 10) & ~StatsFull),
1993                                  ioaddr + EL3_CMD);
1994                        vp->intr_enable &= ~StatsFull;
1995                        DoneDidThat++;
1996                }
1997        }
1998        if (status & IntReq) {          /* Restore all interrupt sources.  */
1999                iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2000                iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2001        }
2002        if (status & HostError) {
2003                u16 fifo_diag;
2004                fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2005                pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2006                           dev->name, fifo_diag);
2007                /* Adapter failure requires Tx/Rx reset and reinit. */
2008                if (vp->full_bus_master_tx) {
2009                        int bus_status = ioread32(ioaddr + PktStatus);
2010                        /* 0x80000000 PCI master abort. */
2011                        /* 0x40000000 PCI target abort. */
2012                        if (vortex_debug)
2013                                pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2014
2015                        /* In this case, blow the card away */
2016                        /* Must not enter D3 or we can't legally issue the reset! */
2017                        vortex_down(dev, 0);
2018                        issue_and_wait(dev, TotalReset | 0xff);
2019                        vortex_up(dev);         /* AKPM: bug.  vortex_up() assumes that the rx ring is full. It may not be. */
2020                } else if (fifo_diag & 0x0400)
2021                        do_tx_reset = 1;
2022                if (fifo_diag & 0x3000) {
2023                        /* Reset Rx fifo and upload logic */
2024                        issue_and_wait(dev, RxReset|0x07);
2025                        /* Set the Rx filter to the current state. */
2026                        set_rx_mode(dev);
2027                        /* enable 802.1q VLAN tagged frames */
2028                        set_8021q_mode(dev, 1);
2029                        iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2030                        iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2031                }
2032        }
2033
2034        if (do_tx_reset) {
2035                issue_and_wait(dev, TxReset|reset_mask);
2036                iowrite16(TxEnable, ioaddr + EL3_CMD);
2037                if (!vp->full_bus_master_tx)
2038                        netif_wake_queue(dev);
2039        }
2040}
2041
2042static netdev_tx_t
2043vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2044{
2045        struct vortex_private *vp = netdev_priv(dev);
2046        void __iomem *ioaddr = vp->ioaddr;
2047        int skblen = skb->len;
2048
2049        /* Put out the doubleword header... */
2050        iowrite32(skb->len, ioaddr + TX_FIFO);
2051        if (vp->bus_master) {
2052                /* Set the bus-master controller to transfer the packet. */
2053                int len = (skb->len + 3) & ~3;
2054                vp->tx_skb_dma = dma_map_single(vp->gendev, skb->data, len,
2055                                                DMA_TO_DEVICE);
2056                if (dma_mapping_error(vp->gendev, vp->tx_skb_dma)) {
2057                        dev_kfree_skb_any(skb);
2058                        dev->stats.tx_dropped++;
2059                        return NETDEV_TX_OK;
2060                }
2061
2062                spin_lock_irq(&vp->window_lock);
2063                window_set(vp, 7);
2064                iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2065                iowrite16(len, ioaddr + Wn7_MasterLen);
2066                spin_unlock_irq(&vp->window_lock);
2067                vp->tx_skb = skb;
2068                skb_tx_timestamp(skb);
2069                iowrite16(StartDMADown, ioaddr + EL3_CMD);
2070                /* netif_wake_queue() will be called at the DMADone interrupt. */
2071        } else {
2072                /* ... and the packet rounded to a doubleword. */
2073                skb_tx_timestamp(skb);
2074                iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2075                dev_consume_skb_any (skb);
2076                if (ioread16(ioaddr + TxFree) > 1536) {
2077                        netif_start_queue (dev);        /* AKPM: redundant? */
2078                } else {
2079                        /* Interrupt us when the FIFO has room for max-sized packet. */
2080                        netif_stop_queue(dev);
2081                        iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2082                }
2083        }
2084
2085        netdev_sent_queue(dev, skblen);
2086
2087        /* Clear the Tx status stack. */
2088        {
2089                int tx_status;
2090                int i = 32;
2091
2092                while (--i > 0  &&      (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2093                        if (tx_status & 0x3C) {         /* A Tx-disabling error occurred.  */
2094                                if (vortex_debug > 2)
2095                                  pr_debug("%s: Tx error, status %2.2x.\n",
2096                                                 dev->name, tx_status);
2097                                if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2098                                if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2099                                if (tx_status & 0x30) {
2100                                        issue_and_wait(dev, TxReset);
2101                                }
2102                                iowrite16(TxEnable, ioaddr + EL3_CMD);
2103                        }
2104                        iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2105                }
2106        }
2107        return NETDEV_TX_OK;
2108}
2109
2110static netdev_tx_t
2111boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2112{
2113        struct vortex_private *vp = netdev_priv(dev);
2114        void __iomem *ioaddr = vp->ioaddr;
2115        /* Calculate the next Tx descriptor entry. */
2116        int entry = vp->cur_tx % TX_RING_SIZE;
2117        int skblen = skb->len;
2118        struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2119        unsigned long flags;
2120        dma_addr_t dma_addr;
2121
2122        if (vortex_debug > 6) {
2123                pr_debug("boomerang_start_xmit()\n");
2124                pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2125                           dev->name, vp->cur_tx);
2126        }
2127
2128        /*
2129         * We can't allow a recursion from our interrupt handler back into the
2130         * tx routine, as they take the same spin lock, and that causes
2131         * deadlock.  Just return NETDEV_TX_BUSY and let the stack try again in
2132         * a bit
2133         */
2134        if (vp->handling_irq)
2135                return NETDEV_TX_BUSY;
2136
2137        if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2138                if (vortex_debug > 0)
2139                        pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
2140                                dev->name);
2141                netif_stop_queue(dev);
2142                return NETDEV_TX_BUSY;
2143        }
2144
2145        vp->tx_skbuff[entry] = skb;
2146
2147        vp->tx_ring[entry].next = 0;
2148#if DO_ZEROCOPY
2149        if (skb->ip_summed != CHECKSUM_PARTIAL)
2150                        vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2151        else
2152                        vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2153
2154        if (!skb_shinfo(skb)->nr_frags) {
2155                dma_addr = dma_map_single(vp->gendev, skb->data, skb->len,
2156                                          DMA_TO_DEVICE);
2157                if (dma_mapping_error(vp->gendev, dma_addr))
2158                        goto out_dma_err;
2159
2160                vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2161                vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2162        } else {
2163                int i;
2164
2165                dma_addr = dma_map_single(vp->gendev, skb->data,
2166                                          skb_headlen(skb), DMA_TO_DEVICE);
2167                if (dma_mapping_error(vp->gendev, dma_addr))
2168                        goto out_dma_err;
2169
2170                vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2171                vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2172
2173                for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2174                        skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2175
2176                        dma_addr = skb_frag_dma_map(vp->gendev, frag,
2177                                                    0,
2178                                                    frag->size,
2179                                                    DMA_TO_DEVICE);
2180                        if (dma_mapping_error(vp->gendev, dma_addr)) {
2181                                for(i = i-1; i >= 0; i--)
2182                                        dma_unmap_page(vp->gendev,
2183                                                       le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2184                                                       le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2185                                                       DMA_TO_DEVICE);
2186
2187                                dma_unmap_single(vp->gendev,
2188                                                 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2189                                                 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2190                                                 DMA_TO_DEVICE);
2191
2192                                goto out_dma_err;
2193                        }
2194
2195                        vp->tx_ring[entry].frag[i+1].addr =
2196                                                cpu_to_le32(dma_addr);
2197
2198                        if (i == skb_shinfo(skb)->nr_frags-1)
2199                                        vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2200                        else
2201                                        vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2202                }
2203        }
2204#else
2205        dma_addr = dma_map_single(vp->gendev, skb->data, skb->len, DMA_TO_DEVICE);
2206        if (dma_mapping_error(vp->gendev, dma_addr))
2207                goto out_dma_err;
2208        vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2209        vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2210        vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2211#endif
2212
2213        spin_lock_irqsave(&vp->lock, flags);
2214        /* Wait for the stall to complete. */
2215        issue_and_wait(dev, DownStall);
2216        prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2217        if (ioread32(ioaddr + DownListPtr) == 0) {
2218                iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2219                vp->queued_packet++;
2220        }
2221
2222        vp->cur_tx++;
2223        netdev_sent_queue(dev, skblen);
2224
2225        if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2226                netif_stop_queue (dev);
2227        } else {                                        /* Clear previous interrupt enable. */
2228#if defined(tx_interrupt_mitigation)
2229                /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2230                 * were selected, this would corrupt DN_COMPLETE. No?
2231                 */
2232                prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2233#endif
2234        }
2235        skb_tx_timestamp(skb);
2236        iowrite16(DownUnstall, ioaddr + EL3_CMD);
2237        spin_unlock_irqrestore(&vp->lock, flags);
2238out:
2239        return NETDEV_TX_OK;
2240out_dma_err:
2241        dev_err(vp->gendev, "Error mapping dma buffer\n");
2242        goto out;
2243}
2244
2245/* The interrupt handler does all of the Rx thread work and cleans up
2246   after the Tx thread. */
2247
2248/*
2249 * This is the ISR for the vortex series chips.
2250 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2251 */
2252
2253static irqreturn_t
2254_vortex_interrupt(int irq, struct net_device *dev)
2255{
2256        struct vortex_private *vp = netdev_priv(dev);
2257        void __iomem *ioaddr;
2258        int status;
2259        int work_done = max_interrupt_work;
2260        int handled = 0;
2261        unsigned int bytes_compl = 0, pkts_compl = 0;
2262
2263        ioaddr = vp->ioaddr;
2264
2265        status = ioread16(ioaddr + EL3_STATUS);
2266
2267        if (vortex_debug > 6)
2268                pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2269
2270        if ((status & IntLatch) == 0)
2271                goto handler_exit;              /* No interrupt: shared IRQs cause this */
2272        handled = 1;
2273
2274        if (status & IntReq) {
2275                status |= vp->deferred;
2276                vp->deferred = 0;
2277        }
2278
2279        if (status == 0xffff)           /* h/w no longer present (hotplug)? */
2280                goto handler_exit;
2281
2282        if (vortex_debug > 4)
2283                pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2284                           dev->name, status, ioread8(ioaddr + Timer));
2285
2286        spin_lock(&vp->window_lock);
2287        window_set(vp, 7);
2288
2289        do {
2290                if (vortex_debug > 5)
2291                                pr_debug("%s: In interrupt loop, status %4.4x.\n",
2292                                           dev->name, status);
2293                if (status & RxComplete)
2294                        vortex_rx(dev);
2295
2296                if (status & TxAvailable) {
2297                        if (vortex_debug > 5)
2298                                pr_debug("      TX room bit was handled.\n");
2299                        /* There's room in the FIFO for a full-sized packet. */
2300                        iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2301                        netif_wake_queue (dev);
2302                }
2303
2304                if (status & DMADone) {
2305                        if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2306                                iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2307                                dma_unmap_single(vp->gendev, vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, DMA_TO_DEVICE);
2308                                pkts_compl++;
2309                                bytes_compl += vp->tx_skb->len;
2310                                dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2311                                if (ioread16(ioaddr + TxFree) > 1536) {
2312                                        /*
2313                                         * AKPM: FIXME: I don't think we need this.  If the queue was stopped due to
2314                                         * insufficient FIFO room, the TxAvailable test will succeed and call
2315                                         * netif_wake_queue()
2316                                         */
2317                                        netif_wake_queue(dev);
2318                                } else { /* Interrupt when FIFO has room for max-sized packet. */
2319                                        iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2320                                        netif_stop_queue(dev);
2321                                }
2322                        }
2323                }
2324                /* Check for all uncommon interrupts at once. */
2325                if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2326                        if (status == 0xffff)
2327                                break;
2328                        if (status & RxEarly)
2329                                vortex_rx(dev);
2330                        spin_unlock(&vp->window_lock);
2331                        vortex_error(dev, status);
2332                        spin_lock(&vp->window_lock);
2333                        window_set(vp, 7);
2334                }
2335
2336                if (--work_done < 0) {
2337                        pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2338                                dev->name, status);
2339                        /* Disable all pending interrupts. */
2340                        do {
2341                                vp->deferred |= status;
2342                                iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2343                                         ioaddr + EL3_CMD);
2344                                iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2345                        } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2346                        /* The timer will reenable interrupts. */
2347                        mod_timer(&vp->timer, jiffies + 1*HZ);
2348                        break;
2349                }
2350                /* Acknowledge the IRQ. */
2351                iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2352        } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2353
2354        netdev_completed_queue(dev, pkts_compl, bytes_compl);
2355        spin_unlock(&vp->window_lock);
2356
2357        if (vortex_debug > 4)
2358                pr_debug("%s: exiting interrupt, status %4.4x.\n",
2359                           dev->name, status);
2360handler_exit:
2361        return IRQ_RETVAL(handled);
2362}
2363
2364/*
2365 * This is the ISR for the boomerang series chips.
2366 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2367 */
2368
2369static irqreturn_t
2370_boomerang_interrupt(int irq, struct net_device *dev)
2371{
2372        struct vortex_private *vp = netdev_priv(dev);
2373        void __iomem *ioaddr;
2374        int status;
2375        int work_done = max_interrupt_work;
2376        int handled = 0;
2377        unsigned int bytes_compl = 0, pkts_compl = 0;
2378
2379        ioaddr = vp->ioaddr;
2380
2381        vp->handling_irq = 1;
2382
2383        status = ioread16(ioaddr + EL3_STATUS);
2384
2385        if (vortex_debug > 6)
2386                pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2387
2388        if ((status & IntLatch) == 0)
2389                goto handler_exit;              /* No interrupt: shared IRQs can cause this */
2390        handled = 1;
2391
2392        if (status == 0xffff) {         /* h/w no longer present (hotplug)? */
2393                if (vortex_debug > 1)
2394                        pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2395                goto handler_exit;
2396        }
2397
2398        if (status & IntReq) {
2399                status |= vp->deferred;
2400                vp->deferred = 0;
2401        }
2402
2403        if (vortex_debug > 4)
2404                pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2405                           dev->name, status, ioread8(ioaddr + Timer));
2406        do {
2407                if (vortex_debug > 5)
2408                                pr_debug("%s: In interrupt loop, status %4.4x.\n",
2409                                           dev->name, status);
2410                if (status & UpComplete) {
2411                        iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2412                        if (vortex_debug > 5)
2413                                pr_debug("boomerang_interrupt->boomerang_rx\n");
2414                        boomerang_rx(dev);
2415                }
2416
2417                if (status & DownComplete) {
2418                        unsigned int dirty_tx = vp->dirty_tx;
2419
2420                        iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2421                        while (vp->cur_tx - dirty_tx > 0) {
2422                                int entry = dirty_tx % TX_RING_SIZE;
2423#if 1   /* AKPM: the latter is faster, but cyclone-only */
2424                                if (ioread32(ioaddr + DownListPtr) ==
2425                                        vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2426                                        break;                  /* It still hasn't been processed. */
2427#else
2428                                if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2429                                        break;                  /* It still hasn't been processed. */
2430#endif
2431
2432                                if (vp->tx_skbuff[entry]) {
2433                                        struct sk_buff *skb = vp->tx_skbuff[entry];
2434#if DO_ZEROCOPY
2435                                        int i;
2436                                        dma_unmap_single(vp->gendev,
2437                                                        le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2438                                                        le32_to_cpu(vp->tx_ring[entry].frag[0].length)&0xFFF,
2439                                                        DMA_TO_DEVICE);
2440
2441                                        for (i=1; i<=skb_shinfo(skb)->nr_frags; i++)
2442                                                        dma_unmap_page(vp->gendev,
2443                                                                                         le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2444                                                                                         le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2445                                                                                         DMA_TO_DEVICE);
2446#else
2447                                        dma_unmap_single(vp->gendev,
2448                                                le32_to_cpu(vp->tx_ring[entry].addr), skb->len, DMA_TO_DEVICE);
2449#endif
2450                                        pkts_compl++;
2451                                        bytes_compl += skb->len;
2452                                        dev_kfree_skb_irq(skb);
2453                                        vp->tx_skbuff[entry] = NULL;
2454                                } else {
2455                                        pr_debug("boomerang_interrupt: no skb!\n");
2456                                }
2457                                /* dev->stats.tx_packets++;  Counted below. */
2458                                dirty_tx++;
2459                        }
2460                        vp->dirty_tx = dirty_tx;
2461                        if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2462                                if (vortex_debug > 6)
2463                                        pr_debug("boomerang_interrupt: wake queue\n");
2464                                netif_wake_queue (dev);
2465                        }
2466                }
2467
2468                /* Check for all uncommon interrupts at once. */
2469                if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2470                        vortex_error(dev, status);
2471
2472                if (--work_done < 0) {
2473                        pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2474                                dev->name, status);
2475                        /* Disable all pending interrupts. */
2476                        do {
2477                                vp->deferred |= status;
2478                                iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2479                                         ioaddr + EL3_CMD);
2480                                iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2481                        } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2482                        /* The timer will reenable interrupts. */
2483                        mod_timer(&vp->timer, jiffies + 1*HZ);
2484                        break;
2485                }
2486                /* Acknowledge the IRQ. */
2487                iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2488                if (vp->cb_fn_base)                     /* The PCMCIA people are idiots.  */
2489                        iowrite32(0x8000, vp->cb_fn_base + 4);
2490
2491        } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2492        netdev_completed_queue(dev, pkts_compl, bytes_compl);
2493
2494        if (vortex_debug > 4)
2495                pr_debug("%s: exiting interrupt, status %4.4x.\n",
2496                           dev->name, status);
2497handler_exit:
2498        vp->handling_irq = 0;
2499        return IRQ_RETVAL(handled);
2500}
2501
2502static irqreturn_t
2503vortex_boomerang_interrupt(int irq, void *dev_id)
2504{
2505        struct net_device *dev = dev_id;
2506        struct vortex_private *vp = netdev_priv(dev);
2507        unsigned long flags;
2508        irqreturn_t ret;
2509
2510        spin_lock_irqsave(&vp->lock, flags);
2511
2512        if (vp->full_bus_master_rx)
2513                ret = _boomerang_interrupt(dev->irq, dev);
2514        else
2515                ret = _vortex_interrupt(dev->irq, dev);
2516
2517        spin_unlock_irqrestore(&vp->lock, flags);
2518
2519        return ret;
2520}
2521
2522static int vortex_rx(struct net_device *dev)
2523{
2524        struct vortex_private *vp = netdev_priv(dev);
2525        void __iomem *ioaddr = vp->ioaddr;
2526        int i;
2527        short rx_status;
2528
2529        if (vortex_debug > 5)
2530                pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2531                           ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2532        while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2533                if (rx_status & 0x4000) { /* Error, update stats. */
2534                        unsigned char rx_error = ioread8(ioaddr + RxErrors);
2535                        if (vortex_debug > 2)
2536                                pr_debug(" Rx error: status %2.2x.\n", rx_error);
2537                        dev->stats.rx_errors++;
2538                        if (rx_error & 0x01)  dev->stats.rx_over_errors++;
2539                        if (rx_error & 0x02)  dev->stats.rx_length_errors++;
2540                        if (rx_error & 0x04)  dev->stats.rx_frame_errors++;
2541                        if (rx_error & 0x08)  dev->stats.rx_crc_errors++;
2542                        if (rx_error & 0x10)  dev->stats.rx_length_errors++;
2543                } else {
2544                        /* The packet length: up to 4.5K!. */
2545                        int pkt_len = rx_status & 0x1fff;
2546                        struct sk_buff *skb;
2547
2548                        skb = netdev_alloc_skb(dev, pkt_len + 5);
2549                        if (vortex_debug > 4)
2550                                pr_debug("Receiving packet size %d status %4.4x.\n",
2551                                           pkt_len, rx_status);
2552                        if (skb != NULL) {
2553                                skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
2554                                /* 'skb_put()' points to the start of sk_buff data area. */
2555                                if (vp->bus_master &&
2556                                        ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2557                                        dma_addr_t dma = dma_map_single(vp->gendev, skb_put(skb, pkt_len),
2558                                                                           pkt_len, DMA_FROM_DEVICE);
2559                                        iowrite32(dma, ioaddr + Wn7_MasterAddr);
2560                                        iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2561                                        iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2562                                        while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2563                                                ;
2564                                        dma_unmap_single(vp->gendev, dma, pkt_len, DMA_FROM_DEVICE);
2565                                } else {
2566                                        ioread32_rep(ioaddr + RX_FIFO,
2567                                                     skb_put(skb, pkt_len),
2568                                                     (pkt_len + 3) >> 2);
2569                                }
2570                                iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2571                                skb->protocol = eth_type_trans(skb, dev);
2572                                netif_rx(skb);
2573                                dev->stats.rx_packets++;
2574                                /* Wait a limited time to go to next packet. */
2575                                for (i = 200; i >= 0; i--)
2576                                        if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2577                                                break;
2578                                continue;
2579                        } else if (vortex_debug > 0)
2580                                pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2581                                        dev->name, pkt_len);
2582                        dev->stats.rx_dropped++;
2583                }
2584                issue_and_wait(dev, RxDiscard);
2585        }
2586
2587        return 0;
2588}
2589
2590static int
2591boomerang_rx(struct net_device *dev)
2592{
2593        struct vortex_private *vp = netdev_priv(dev);
2594        int entry = vp->cur_rx % RX_RING_SIZE;
2595        void __iomem *ioaddr = vp->ioaddr;
2596        int rx_status;
2597        int rx_work_limit = RX_RING_SIZE;
2598
2599        if (vortex_debug > 5)
2600                pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2601
2602        while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2603                if (--rx_work_limit < 0)
2604                        break;
2605                if (rx_status & RxDError) { /* Error, update stats. */
2606                        unsigned char rx_error = rx_status >> 16;
2607                        if (vortex_debug > 2)
2608                                pr_debug(" Rx error: status %2.2x.\n", rx_error);
2609                        dev->stats.rx_errors++;
2610                        if (rx_error & 0x01)  dev->stats.rx_over_errors++;
2611                        if (rx_error & 0x02)  dev->stats.rx_length_errors++;
2612                        if (rx_error & 0x04)  dev->stats.rx_frame_errors++;
2613                        if (rx_error & 0x08)  dev->stats.rx_crc_errors++;
2614                        if (rx_error & 0x10)  dev->stats.rx_length_errors++;
2615                } else {
2616                        /* The packet length: up to 4.5K!. */
2617                        int pkt_len = rx_status & 0x1fff;
2618                        struct sk_buff *skb, *newskb;
2619                        dma_addr_t newdma;
2620                        dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2621
2622                        if (vortex_debug > 4)
2623                                pr_debug("Receiving packet size %d status %4.4x.\n",
2624                                           pkt_len, rx_status);
2625
2626                        /* Check if the packet is long enough to just accept without
2627                           copying to a properly sized skbuff. */
2628                        if (pkt_len < rx_copybreak &&
2629                            (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2630                                skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
2631                                dma_sync_single_for_cpu(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2632                                /* 'skb_put()' points to the start of sk_buff data area. */
2633                                skb_put_data(skb, vp->rx_skbuff[entry]->data,
2634                                             pkt_len);
2635                                dma_sync_single_for_device(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2636                                vp->rx_copy++;
2637                        } else {
2638                                /* Pre-allocate the replacement skb.  If it or its
2639                                 * mapping fails then recycle the buffer thats already
2640                                 * in place
2641                                 */
2642                                newskb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2643                                if (!newskb) {
2644                                        dev->stats.rx_dropped++;
2645                                        goto clear_complete;
2646                                }
2647                                newdma = dma_map_single(vp->gendev, newskb->data,
2648                                                        PKT_BUF_SZ, DMA_FROM_DEVICE);
2649                                if (dma_mapping_error(vp->gendev, newdma)) {
2650                                        dev->stats.rx_dropped++;
2651                                        consume_skb(newskb);
2652                                        goto clear_complete;
2653                                }
2654
2655                                /* Pass up the skbuff already on the Rx ring. */
2656                                skb = vp->rx_skbuff[entry];
2657                                vp->rx_skbuff[entry] = newskb;
2658                                vp->rx_ring[entry].addr = cpu_to_le32(newdma);
2659                                skb_put(skb, pkt_len);
2660                                dma_unmap_single(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2661                                vp->rx_nocopy++;
2662                        }
2663                        skb->protocol = eth_type_trans(skb, dev);
2664                        {                                       /* Use hardware checksum info. */
2665                                int csum_bits = rx_status & 0xee000000;
2666                                if (csum_bits &&
2667                                        (csum_bits == (IPChksumValid | TCPChksumValid) ||
2668                                         csum_bits == (IPChksumValid | UDPChksumValid))) {
2669                                        skb->ip_summed = CHECKSUM_UNNECESSARY;
2670                                        vp->rx_csumhits++;
2671                                }
2672                        }
2673                        netif_rx(skb);
2674                        dev->stats.rx_packets++;
2675                }
2676
2677clear_complete:
2678                vp->rx_ring[entry].status = 0;  /* Clear complete bit. */
2679                iowrite16(UpUnstall, ioaddr + EL3_CMD);
2680                entry = (++vp->cur_rx) % RX_RING_SIZE;
2681        }
2682        return 0;
2683}
2684
2685static void
2686vortex_down(struct net_device *dev, int final_down)
2687{
2688        struct vortex_private *vp = netdev_priv(dev);
2689        void __iomem *ioaddr = vp->ioaddr;
2690
2691        netdev_reset_queue(dev);
2692        netif_stop_queue(dev);
2693
2694        del_timer_sync(&vp->timer);
2695
2696        /* Turn off statistics ASAP.  We update dev->stats below. */
2697        iowrite16(StatsDisable, ioaddr + EL3_CMD);
2698
2699        /* Disable the receiver and transmitter. */
2700        iowrite16(RxDisable, ioaddr + EL3_CMD);
2701        iowrite16(TxDisable, ioaddr + EL3_CMD);
2702
2703        /* Disable receiving 802.1q tagged frames */
2704        set_8021q_mode(dev, 0);
2705
2706        if (dev->if_port == XCVR_10base2)
2707                /* Turn off thinnet power.  Green! */
2708                iowrite16(StopCoax, ioaddr + EL3_CMD);
2709
2710        iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2711
2712        update_stats(ioaddr, dev);
2713        if (vp->full_bus_master_rx)
2714                iowrite32(0, ioaddr + UpListPtr);
2715        if (vp->full_bus_master_tx)
2716                iowrite32(0, ioaddr + DownListPtr);
2717
2718        if (final_down && VORTEX_PCI(vp)) {
2719                vp->pm_state_valid = 1;
2720                pci_save_state(VORTEX_PCI(vp));
2721                acpi_set_WOL(dev);
2722        }
2723}
2724
2725static int
2726vortex_close(struct net_device *dev)
2727{
2728        struct vortex_private *vp = netdev_priv(dev);
2729        void __iomem *ioaddr = vp->ioaddr;
2730        int i;
2731
2732        if (netif_device_present(dev))
2733                vortex_down(dev, 1);
2734
2735        if (vortex_debug > 1) {
2736                pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2737                           dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2738                pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2739                           " tx_queued %d Rx pre-checksummed %d.\n",
2740                           dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2741        }
2742
2743#if DO_ZEROCOPY
2744        if (vp->rx_csumhits &&
2745            (vp->drv_flags & HAS_HWCKSM) == 0 &&
2746            (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2747                pr_warn("%s supports hardware checksums, and we're not using them!\n",
2748                        dev->name);
2749        }
2750#endif
2751
2752        free_irq(dev->irq, dev);
2753
2754        if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2755                for (i = 0; i < RX_RING_SIZE; i++)
2756                        if (vp->rx_skbuff[i]) {
2757                                dma_unmap_single(vp->gendev, le32_to_cpu(vp->rx_ring[i].addr),
2758                                                                        PKT_BUF_SZ, DMA_FROM_DEVICE);
2759                                dev_kfree_skb(vp->rx_skbuff[i]);
2760                                vp->rx_skbuff[i] = NULL;
2761                        }
2762        }
2763        if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2764                for (i = 0; i < TX_RING_SIZE; i++) {
2765                        if (vp->tx_skbuff[i]) {
2766                                struct sk_buff *skb = vp->tx_skbuff[i];
2767#if DO_ZEROCOPY
2768                                int k;
2769
2770                                for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2771                                                dma_unmap_single(vp->gendev,
2772                                                                                 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2773                                                                                 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2774                                                                                 DMA_TO_DEVICE);
2775#else
2776                                dma_unmap_single(vp->gendev, le32_to_cpu(vp->tx_ring[i].addr), skb->len, DMA_TO_DEVICE);
2777#endif
2778                                dev_kfree_skb(skb);
2779                                vp->tx_skbuff[i] = NULL;
2780                        }
2781                }
2782        }
2783
2784        return 0;
2785}
2786
2787static void
2788dump_tx_ring(struct net_device *dev)
2789{
2790        if (vortex_debug > 0) {
2791        struct vortex_private *vp = netdev_priv(dev);
2792                void __iomem *ioaddr = vp->ioaddr;
2793
2794                if (vp->full_bus_master_tx) {
2795                        int i;
2796                        int stalled = ioread32(ioaddr + PktStatus) & 0x04;      /* Possible racy. But it's only debug stuff */
2797
2798                        pr_err("  Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2799                                        vp->full_bus_master_tx,
2800                                        vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2801                                        vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2802                        pr_err("  Transmit list %8.8x vs. %p.\n",
2803                                   ioread32(ioaddr + DownListPtr),
2804                                   &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2805                        issue_and_wait(dev, DownStall);
2806                        for (i = 0; i < TX_RING_SIZE; i++) {
2807                                unsigned int length;
2808
2809#if DO_ZEROCOPY
2810                                length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2811#else
2812                                length = le32_to_cpu(vp->tx_ring[i].length);
2813#endif
2814                                pr_err("  %d: @%p  length %8.8x status %8.8x\n",
2815                                           i, &vp->tx_ring[i], length,
2816                                           le32_to_cpu(vp->tx_ring[i].status));
2817                        }
2818                        if (!stalled)
2819                                iowrite16(DownUnstall, ioaddr + EL3_CMD);
2820                }
2821        }
2822}
2823
2824static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2825{
2826        struct vortex_private *vp = netdev_priv(dev);
2827        void __iomem *ioaddr = vp->ioaddr;
2828        unsigned long flags;
2829
2830        if (netif_device_present(dev)) {        /* AKPM: Used to be netif_running */
2831                spin_lock_irqsave (&vp->lock, flags);
2832                update_stats(ioaddr, dev);
2833                spin_unlock_irqrestore (&vp->lock, flags);
2834        }
2835        return &dev->stats;
2836}
2837
2838/*  Update statistics.
2839        Unlike with the EL3 we need not worry about interrupts changing
2840        the window setting from underneath us, but we must still guard
2841        against a race condition with a StatsUpdate interrupt updating the
2842        table.  This is done by checking that the ASM (!) code generated uses
2843        atomic updates with '+='.
2844        */
2845static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2846{
2847        struct vortex_private *vp = netdev_priv(dev);
2848
2849        /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2850        /* Switch to the stats window, and read everything. */
2851        dev->stats.tx_carrier_errors            += window_read8(vp, 6, 0);
2852        dev->stats.tx_heartbeat_errors          += window_read8(vp, 6, 1);
2853        dev->stats.tx_window_errors             += window_read8(vp, 6, 4);
2854        dev->stats.rx_fifo_errors               += window_read8(vp, 6, 5);
2855        dev->stats.tx_packets                   += window_read8(vp, 6, 6);
2856        dev->stats.tx_packets                   += (window_read8(vp, 6, 9) &
2857                                                    0x30) << 4;
2858        /* Rx packets   */                      window_read8(vp, 6, 7);   /* Must read to clear */
2859        /* Don't bother with register 9, an extension of registers 6&7.
2860           If we do use the 6&7 values the atomic update assumption above
2861           is invalid. */
2862        dev->stats.rx_bytes                     += window_read16(vp, 6, 10);
2863        dev->stats.tx_bytes                     += window_read16(vp, 6, 12);
2864        /* Extra stats for get_ethtool_stats() */
2865        vp->xstats.tx_multiple_collisions       += window_read8(vp, 6, 2);
2866        vp->xstats.tx_single_collisions         += window_read8(vp, 6, 3);
2867        vp->xstats.tx_deferred                  += window_read8(vp, 6, 8);
2868        vp->xstats.rx_bad_ssd                   += window_read8(vp, 4, 12);
2869
2870        dev->stats.collisions = vp->xstats.tx_multiple_collisions
2871                + vp->xstats.tx_single_collisions
2872                + vp->xstats.tx_max_collisions;
2873
2874        {
2875                u8 up = window_read8(vp, 4, 13);
2876                dev->stats.rx_bytes += (up & 0x0f) << 16;
2877                dev->stats.tx_bytes += (up & 0xf0) << 12;
2878        }
2879}
2880
2881static int vortex_nway_reset(struct net_device *dev)
2882{
2883        struct vortex_private *vp = netdev_priv(dev);
2884
2885        return mii_nway_restart(&vp->mii);
2886}
2887
2888static int vortex_get_link_ksettings(struct net_device *dev,
2889                                     struct ethtool_link_ksettings *cmd)
2890{
2891        struct vortex_private *vp = netdev_priv(dev);
2892
2893        mii_ethtool_get_link_ksettings(&vp->mii, cmd);
2894
2895        return 0;
2896}
2897
2898static int vortex_set_link_ksettings(struct net_device *dev,
2899                                     const struct ethtool_link_ksettings *cmd)
2900{
2901        struct vortex_private *vp = netdev_priv(dev);
2902
2903        return mii_ethtool_set_link_ksettings(&vp->mii, cmd);
2904}
2905
2906static u32 vortex_get_msglevel(struct net_device *dev)
2907{
2908        return vortex_debug;
2909}
2910
2911static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2912{
2913        vortex_debug = dbg;
2914}
2915
2916static int vortex_get_sset_count(struct net_device *dev, int sset)
2917{
2918        switch (sset) {
2919        case ETH_SS_STATS:
2920                return VORTEX_NUM_STATS;
2921        default:
2922                return -EOPNOTSUPP;
2923        }
2924}
2925
2926static void vortex_get_ethtool_stats(struct net_device *dev,
2927        struct ethtool_stats *stats, u64 *data)
2928{
2929        struct vortex_private *vp = netdev_priv(dev);
2930        void __iomem *ioaddr = vp->ioaddr;
2931        unsigned long flags;
2932
2933        spin_lock_irqsave(&vp->lock, flags);
2934        update_stats(ioaddr, dev);
2935        spin_unlock_irqrestore(&vp->lock, flags);
2936
2937        data[0] = vp->xstats.tx_deferred;
2938        data[1] = vp->xstats.tx_max_collisions;
2939        data[2] = vp->xstats.tx_multiple_collisions;
2940        data[3] = vp->xstats.tx_single_collisions;
2941        data[4] = vp->xstats.rx_bad_ssd;
2942}
2943
2944
2945static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2946{
2947        switch (stringset) {
2948        case ETH_SS_STATS:
2949                memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2950                break;
2951        default:
2952                WARN_ON(1);
2953                break;
2954        }
2955}
2956
2957static void vortex_get_drvinfo(struct net_device *dev,
2958                                        struct ethtool_drvinfo *info)
2959{
2960        struct vortex_private *vp = netdev_priv(dev);
2961
2962        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2963        if (VORTEX_PCI(vp)) {
2964                strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2965                        sizeof(info->bus_info));
2966        } else {
2967                if (VORTEX_EISA(vp))
2968                        strlcpy(info->bus_info, dev_name(vp->gendev),
2969                                sizeof(info->bus_info));
2970                else
2971                        snprintf(info->bus_info, sizeof(info->bus_info),
2972                                "EISA 0x%lx %d", dev->base_addr, dev->irq);
2973        }
2974}
2975
2976static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2977{
2978        struct vortex_private *vp = netdev_priv(dev);
2979
2980        if (!VORTEX_PCI(vp))
2981                return;
2982
2983        wol->supported = WAKE_MAGIC;
2984
2985        wol->wolopts = 0;
2986        if (vp->enable_wol)
2987                wol->wolopts |= WAKE_MAGIC;
2988}
2989
2990static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2991{
2992        struct vortex_private *vp = netdev_priv(dev);
2993
2994        if (!VORTEX_PCI(vp))
2995                return -EOPNOTSUPP;
2996
2997        if (wol->wolopts & ~WAKE_MAGIC)
2998                return -EINVAL;
2999
3000        if (wol->wolopts & WAKE_MAGIC)
3001                vp->enable_wol = 1;
3002        else
3003                vp->enable_wol = 0;
3004        acpi_set_WOL(dev);
3005
3006        return 0;
3007}
3008
3009static const struct ethtool_ops vortex_ethtool_ops = {
3010        .get_drvinfo            = vortex_get_drvinfo,
3011        .get_strings            = vortex_get_strings,
3012        .get_msglevel           = vortex_get_msglevel,
3013        .set_msglevel           = vortex_set_msglevel,
3014        .get_ethtool_stats      = vortex_get_ethtool_stats,
3015        .get_sset_count         = vortex_get_sset_count,
3016        .get_link               = ethtool_op_get_link,
3017        .nway_reset             = vortex_nway_reset,
3018        .get_wol                = vortex_get_wol,
3019        .set_wol                = vortex_set_wol,
3020        .get_ts_info            = ethtool_op_get_ts_info,
3021        .get_link_ksettings     = vortex_get_link_ksettings,
3022        .set_link_ksettings     = vortex_set_link_ksettings,
3023};
3024
3025#ifdef CONFIG_PCI
3026/*
3027 *      Must power the device up to do MDIO operations
3028 */
3029static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3030{
3031        int err;
3032        struct vortex_private *vp = netdev_priv(dev);
3033        pci_power_t state = 0;
3034
3035        if(VORTEX_PCI(vp))
3036                state = VORTEX_PCI(vp)->current_state;
3037
3038        /* The kernel core really should have pci_get_power_state() */
3039
3040        if(state != 0)
3041                pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3042        err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3043        if(state != 0)
3044                pci_set_power_state(VORTEX_PCI(vp), state);
3045
3046        return err;
3047}
3048#endif
3049
3050
3051/* Pre-Cyclone chips have no documented multicast filter, so the only
3052   multicast setting is to receive all multicast frames.  At least
3053   the chip has a very clean way to set the mode, unlike many others. */
3054static void set_rx_mode(struct net_device *dev)
3055{
3056        struct vortex_private *vp = netdev_priv(dev);
3057        void __iomem *ioaddr = vp->ioaddr;
3058        int new_mode;
3059
3060        if (dev->flags & IFF_PROMISC) {
3061                if (vortex_debug > 3)
3062                        pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3063                new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3064        } else  if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3065                new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3066        } else
3067                new_mode = SetRxFilter | RxStation | RxBroadcast;
3068
3069        iowrite16(new_mode, ioaddr + EL3_CMD);
3070}
3071
3072#if IS_ENABLED(CONFIG_VLAN_8021Q)
3073/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3074   Note that this must be done after each RxReset due to some backwards
3075   compatibility logic in the Cyclone and Tornado ASICs */
3076
3077/* The Ethernet Type used for 802.1q tagged frames */
3078#define VLAN_ETHER_TYPE 0x8100
3079
3080static void set_8021q_mode(struct net_device *dev, int enable)
3081{
3082        struct vortex_private *vp = netdev_priv(dev);
3083        int mac_ctrl;
3084
3085        if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3086                /* cyclone and tornado chipsets can recognize 802.1q
3087                 * tagged frames and treat them correctly */
3088
3089                int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3090                if (enable)
3091                        max_pkt_size += 4;      /* 802.1Q VLAN tag */
3092
3093                window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3094
3095                /* set VlanEtherType to let the hardware checksumming
3096                   treat tagged frames correctly */
3097                window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3098        } else {
3099                /* on older cards we have to enable large frames */
3100
3101                vp->large_frames = dev->mtu > 1500 || enable;
3102
3103                mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3104                if (vp->large_frames)
3105                        mac_ctrl |= 0x40;
3106                else
3107                        mac_ctrl &= ~0x40;
3108                window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3109        }
3110}
3111#else
3112
3113static void set_8021q_mode(struct net_device *dev, int enable)
3114{
3115}
3116
3117
3118#endif
3119
3120/* MII transceiver control section.
3121   Read and write the MII registers using software-generated serial
3122   MDIO protocol.  See the MII specifications or DP83840A data sheet
3123   for details. */
3124
3125/* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
3126   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3127   "overclocking" issues. */
3128static void mdio_delay(struct vortex_private *vp)
3129{
3130        window_read32(vp, 4, Wn4_PhysicalMgmt);
3131}
3132
3133#define MDIO_SHIFT_CLK  0x01
3134#define MDIO_DIR_WRITE  0x04
3135#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3136#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3137#define MDIO_DATA_READ  0x02
3138#define MDIO_ENB_IN             0x00
3139
3140/* Generate the preamble required for initial synchronization and
3141   a few older transceivers. */
3142static void mdio_sync(struct vortex_private *vp, int bits)
3143{
3144        /* Establish sync by sending at least 32 logic ones. */
3145        while (-- bits >= 0) {
3146                window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3147                mdio_delay(vp);
3148                window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3149                               4, Wn4_PhysicalMgmt);
3150                mdio_delay(vp);
3151        }
3152}
3153
3154static int mdio_read(struct net_device *dev, int phy_id, int location)
3155{
3156        int i;
3157        struct vortex_private *vp = netdev_priv(dev);
3158        int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3159        unsigned int retval = 0;
3160
3161        spin_lock_bh(&vp->mii_lock);
3162
3163        if (mii_preamble_required)
3164                mdio_sync(vp, 32);
3165
3166        /* Shift the read command bits out. */
3167        for (i = 14; i >= 0; i--) {
3168                int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3169                window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3170                mdio_delay(vp);
3171                window_write16(vp, dataval | MDIO_SHIFT_CLK,
3172                               4, Wn4_PhysicalMgmt);
3173                mdio_delay(vp);
3174        }
3175        /* Read the two transition, 16 data, and wire-idle bits. */
3176        for (i = 19; i > 0; i--) {
3177                window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3178                mdio_delay(vp);
3179                retval = (retval << 1) |
3180                        ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3181                          MDIO_DATA_READ) ? 1 : 0);
3182                window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3183                               4, Wn4_PhysicalMgmt);
3184                mdio_delay(vp);
3185        }
3186
3187        spin_unlock_bh(&vp->mii_lock);
3188
3189        return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3190}
3191
3192static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3193{
3194        struct vortex_private *vp = netdev_priv(dev);
3195        int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3196        int i;
3197
3198        spin_lock_bh(&vp->mii_lock);
3199
3200        if (mii_preamble_required)
3201                mdio_sync(vp, 32);
3202
3203        /* Shift the command bits out. */
3204        for (i = 31; i >= 0; i--) {
3205                int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3206                window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3207                mdio_delay(vp);
3208                window_write16(vp, dataval | MDIO_SHIFT_CLK,
3209                               4, Wn4_PhysicalMgmt);
3210                mdio_delay(vp);
3211        }
3212        /* Leave the interface idle. */
3213        for (i = 1; i >= 0; i--) {
3214                window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3215                mdio_delay(vp);
3216                window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3217                               4, Wn4_PhysicalMgmt);
3218                mdio_delay(vp);
3219        }
3220
3221        spin_unlock_bh(&vp->mii_lock);
3222}
3223
3224/* ACPI: Advanced Configuration and Power Interface. */
3225/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3226static void acpi_set_WOL(struct net_device *dev)
3227{
3228        struct vortex_private *vp = netdev_priv(dev);
3229        void __iomem *ioaddr = vp->ioaddr;
3230
3231        device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3232
3233        if (vp->enable_wol) {
3234                /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3235                window_write16(vp, 2, 7, 0x0c);
3236                /* The RxFilter must accept the WOL frames. */
3237                iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3238                iowrite16(RxEnable, ioaddr + EL3_CMD);
3239
3240                if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3241                        pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3242
3243                        vp->enable_wol = 0;
3244                        return;
3245                }
3246
3247                if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3248                        return;
3249
3250                /* Change the power state to D3; RxEnable doesn't take effect. */
3251                pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3252        }
3253}
3254
3255
3256static void vortex_remove_one(struct pci_dev *pdev)
3257{
3258        struct net_device *dev = pci_get_drvdata(pdev);
3259        struct vortex_private *vp;
3260
3261        if (!dev) {
3262                pr_err("vortex_remove_one called for Compaq device!\n");
3263                BUG();
3264        }
3265
3266        vp = netdev_priv(dev);
3267
3268        if (vp->cb_fn_base)
3269                pci_iounmap(pdev, vp->cb_fn_base);
3270
3271        unregister_netdev(dev);
3272
3273        pci_set_power_state(pdev, PCI_D0);      /* Go active */
3274        if (vp->pm_state_valid)
3275                pci_restore_state(pdev);
3276        pci_disable_device(pdev);
3277
3278        /* Should really use issue_and_wait() here */
3279        iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3280             vp->ioaddr + EL3_CMD);
3281
3282        pci_iounmap(pdev, vp->ioaddr);
3283
3284        dma_free_coherent(&pdev->dev,
3285                        sizeof(struct boom_rx_desc) * RX_RING_SIZE +
3286                        sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3287                        vp->rx_ring, vp->rx_ring_dma);
3288
3289        pci_release_regions(pdev);
3290
3291        free_netdev(dev);
3292}
3293
3294
3295static struct pci_driver vortex_driver = {
3296        .name           = "3c59x",
3297        .probe          = vortex_init_one,
3298        .remove         = vortex_remove_one,
3299        .id_table       = vortex_pci_tbl,
3300        .driver.pm      = VORTEX_PM_OPS,
3301};
3302
3303
3304static int vortex_have_pci;
3305static int vortex_have_eisa;
3306
3307
3308static int __init vortex_init(void)
3309{
3310        int pci_rc, eisa_rc;
3311
3312        pci_rc = pci_register_driver(&vortex_driver);
3313        eisa_rc = vortex_eisa_init();
3314
3315        if (pci_rc == 0)
3316                vortex_have_pci = 1;
3317        if (eisa_rc > 0)
3318                vortex_have_eisa = 1;
3319
3320        return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3321}
3322
3323
3324static void __exit vortex_eisa_cleanup(void)
3325{
3326        void __iomem *ioaddr;
3327
3328#ifdef CONFIG_EISA
3329        /* Take care of the EISA devices */
3330        eisa_driver_unregister(&vortex_eisa_driver);
3331#endif
3332
3333        if (compaq_net_device) {
3334                ioaddr = ioport_map(compaq_net_device->base_addr,
3335                                    VORTEX_TOTAL_SIZE);
3336
3337                unregister_netdev(compaq_net_device);
3338                iowrite16(TotalReset, ioaddr + EL3_CMD);
3339                release_region(compaq_net_device->base_addr,
3340                               VORTEX_TOTAL_SIZE);
3341
3342                free_netdev(compaq_net_device);
3343        }
3344}
3345
3346
3347static void __exit vortex_cleanup(void)
3348{
3349        if (vortex_have_pci)
3350                pci_unregister_driver(&vortex_driver);
3351        if (vortex_have_eisa)
3352                vortex_eisa_cleanup();
3353}
3354
3355
3356module_init(vortex_init);
3357module_exit(vortex_cleanup);
3358