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10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/bcma/bcma.h>
13#include <linux/etherdevice.h>
14#include <linux/interrupt.h>
15#include <linux/bcm47xx_nvram.h>
16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
18#include <net/dsa.h>
19#include "bgmac.h"
20
21static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
22 u32 value, int timeout)
23{
24 u32 val;
25 int i;
26
27 for (i = 0; i < timeout / 10; i++) {
28 val = bgmac_read(bgmac, reg);
29 if ((val & mask) == value)
30 return true;
31 udelay(10);
32 }
33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
34 return false;
35}
36
37
38
39
40
41static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
42{
43 u32 val;
44 int i;
45
46 if (!ring->mmio_base)
47 return;
48
49
50
51
52
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
54 BGMAC_DMA_TX_SUSPEND);
55 for (i = 0; i < 10000 / 10; i++) {
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
57 val &= BGMAC_DMA_TX_STAT;
58 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
59 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
60 val == BGMAC_DMA_TX_STAT_STOPPED) {
61 i = 0;
62 break;
63 }
64 udelay(10);
65 }
66 if (i)
67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
68 ring->mmio_base, val);
69
70
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
72 if (!bgmac_wait_value(bgmac,
73 ring->mmio_base + BGMAC_DMA_TX_STATUS,
74 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
75 10000)) {
76 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
77 ring->mmio_base);
78 udelay(300);
79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
80 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
81 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
82 ring->mmio_base);
83 }
84}
85
86static void bgmac_dma_tx_enable(struct bgmac *bgmac,
87 struct bgmac_dma_ring *ring)
88{
89 u32 ctl;
90
91 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
92 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
93 ctl &= ~BGMAC_DMA_TX_BL_MASK;
94 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
95
96 ctl &= ~BGMAC_DMA_TX_MR_MASK;
97 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
98
99 ctl &= ~BGMAC_DMA_TX_PC_MASK;
100 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
101
102 ctl &= ~BGMAC_DMA_TX_PT_MASK;
103 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
104 }
105 ctl |= BGMAC_DMA_TX_ENABLE;
106 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
107 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
108}
109
110static void
111bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
112 int i, int len, u32 ctl0)
113{
114 struct bgmac_slot_info *slot;
115 struct bgmac_dma_desc *dma_desc;
116 u32 ctl1;
117
118 if (i == BGMAC_TX_RING_SLOTS - 1)
119 ctl0 |= BGMAC_DESC_CTL0_EOT;
120
121 ctl1 = len & BGMAC_DESC_CTL1_LEN;
122
123 slot = &ring->slots[i];
124 dma_desc = &ring->cpu_base[i];
125 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
126 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
127 dma_desc->ctl0 = cpu_to_le32(ctl0);
128 dma_desc->ctl1 = cpu_to_le32(ctl1);
129}
130
131static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
132 struct bgmac_dma_ring *ring,
133 struct sk_buff *skb)
134{
135 struct device *dma_dev = bgmac->dma_dev;
136 struct net_device *net_dev = bgmac->net_dev;
137 int index = ring->end % BGMAC_TX_RING_SLOTS;
138 struct bgmac_slot_info *slot = &ring->slots[index];
139 int nr_frags;
140 u32 flags;
141 int i;
142
143 if (skb->len > BGMAC_DESC_CTL1_LEN) {
144 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
145 goto err_drop;
146 }
147
148 if (skb->ip_summed == CHECKSUM_PARTIAL)
149 skb_checksum_help(skb);
150
151 nr_frags = skb_shinfo(skb)->nr_frags;
152
153
154
155
156 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
157 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
158 netif_stop_queue(net_dev);
159 return NETDEV_TX_BUSY;
160 }
161
162 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
163 DMA_TO_DEVICE);
164 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
165 goto err_dma_head;
166
167 flags = BGMAC_DESC_CTL0_SOF;
168 if (!nr_frags)
169 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
170
171 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
172 flags = 0;
173
174 for (i = 0; i < nr_frags; i++) {
175 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
176 int len = skb_frag_size(frag);
177
178 index = (index + 1) % BGMAC_TX_RING_SLOTS;
179 slot = &ring->slots[index];
180 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
181 len, DMA_TO_DEVICE);
182 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
183 goto err_dma;
184
185 if (i == nr_frags - 1)
186 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
187
188 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
189 }
190
191 slot->skb = skb;
192 ring->end += nr_frags + 1;
193 netdev_sent_queue(net_dev, skb->len);
194
195 wmb();
196
197
198
199
200 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
201 ring->index_base +
202 (ring->end % BGMAC_TX_RING_SLOTS) *
203 sizeof(struct bgmac_dma_desc));
204
205 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
206 netif_stop_queue(net_dev);
207
208 return NETDEV_TX_OK;
209
210err_dma:
211 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
212 DMA_TO_DEVICE);
213
214 while (i-- > 0) {
215 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
216 struct bgmac_slot_info *slot = &ring->slots[index];
217 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
218 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
219
220 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
221 }
222
223err_dma_head:
224 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
225 ring->mmio_base);
226
227err_drop:
228 dev_kfree_skb(skb);
229 net_dev->stats.tx_dropped++;
230 net_dev->stats.tx_errors++;
231 return NETDEV_TX_OK;
232}
233
234
235static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
236{
237 struct device *dma_dev = bgmac->dma_dev;
238 int empty_slot;
239 unsigned bytes_compl = 0, pkts_compl = 0;
240
241
242 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
243 empty_slot &= BGMAC_DMA_TX_STATDPTR;
244 empty_slot -= ring->index_base;
245 empty_slot &= BGMAC_DMA_TX_STATDPTR;
246 empty_slot /= sizeof(struct bgmac_dma_desc);
247
248 while (ring->start != ring->end) {
249 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
250 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
251 u32 ctl0, ctl1;
252 int len;
253
254 if (slot_idx == empty_slot)
255 break;
256
257 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
258 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
259 len = ctl1 & BGMAC_DESC_CTL1_LEN;
260 if (ctl0 & BGMAC_DESC_CTL0_SOF)
261
262 dma_unmap_single(dma_dev, slot->dma_addr, len,
263 DMA_TO_DEVICE);
264 else
265 dma_unmap_page(dma_dev, slot->dma_addr, len,
266 DMA_TO_DEVICE);
267
268 if (slot->skb) {
269 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
270 bgmac->net_dev->stats.tx_packets++;
271 bytes_compl += slot->skb->len;
272 pkts_compl++;
273
274
275 dev_kfree_skb(slot->skb);
276 slot->skb = NULL;
277 }
278
279 slot->dma_addr = 0;
280 ring->start++;
281 }
282
283 if (!pkts_compl)
284 return;
285
286 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
287
288 if (netif_queue_stopped(bgmac->net_dev))
289 netif_wake_queue(bgmac->net_dev);
290}
291
292static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
293{
294 if (!ring->mmio_base)
295 return;
296
297 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
298 if (!bgmac_wait_value(bgmac,
299 ring->mmio_base + BGMAC_DMA_RX_STATUS,
300 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
301 10000))
302 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
303 ring->mmio_base);
304}
305
306static void bgmac_dma_rx_enable(struct bgmac *bgmac,
307 struct bgmac_dma_ring *ring)
308{
309 u32 ctl;
310
311 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
312
313
314 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
315
316 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
317 ctl &= ~BGMAC_DMA_RX_BL_MASK;
318 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
319
320 ctl &= ~BGMAC_DMA_RX_PC_MASK;
321 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
322
323 ctl &= ~BGMAC_DMA_RX_PT_MASK;
324 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
325 }
326 ctl |= BGMAC_DMA_RX_ENABLE;
327 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
328 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
329 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
330 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
331}
332
333static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
334 struct bgmac_slot_info *slot)
335{
336 struct device *dma_dev = bgmac->dma_dev;
337 dma_addr_t dma_addr;
338 struct bgmac_rx_header *rx;
339 void *buf;
340
341
342 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
343 if (!buf)
344 return -ENOMEM;
345
346
347 rx = buf + BGMAC_RX_BUF_OFFSET;
348 rx->len = cpu_to_le16(0xdead);
349 rx->flags = cpu_to_le16(0xbeef);
350
351
352 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
353 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
354 if (dma_mapping_error(dma_dev, dma_addr)) {
355 netdev_err(bgmac->net_dev, "DMA mapping error\n");
356 put_page(virt_to_head_page(buf));
357 return -ENOMEM;
358 }
359
360
361 slot->buf = buf;
362 slot->dma_addr = dma_addr;
363
364 return 0;
365}
366
367static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
368 struct bgmac_dma_ring *ring)
369{
370 dma_wmb();
371
372 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
373 ring->index_base +
374 ring->end * sizeof(struct bgmac_dma_desc));
375}
376
377static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
378 struct bgmac_dma_ring *ring, int desc_idx)
379{
380 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
381 u32 ctl0 = 0, ctl1 = 0;
382
383 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
384 ctl0 |= BGMAC_DESC_CTL0_EOT;
385 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
386
387
388
389
390
391 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
392 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
393 dma_desc->ctl0 = cpu_to_le32(ctl0);
394 dma_desc->ctl1 = cpu_to_le32(ctl1);
395
396 ring->end = desc_idx;
397}
398
399static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
400 struct bgmac_slot_info *slot)
401{
402 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
403
404 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
405 DMA_FROM_DEVICE);
406 rx->len = cpu_to_le16(0xdead);
407 rx->flags = cpu_to_le16(0xbeef);
408 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
409 DMA_FROM_DEVICE);
410}
411
412static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
413 int weight)
414{
415 u32 end_slot;
416 int handled = 0;
417
418 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
419 end_slot &= BGMAC_DMA_RX_STATDPTR;
420 end_slot -= ring->index_base;
421 end_slot &= BGMAC_DMA_RX_STATDPTR;
422 end_slot /= sizeof(struct bgmac_dma_desc);
423
424 while (ring->start != end_slot) {
425 struct device *dma_dev = bgmac->dma_dev;
426 struct bgmac_slot_info *slot = &ring->slots[ring->start];
427 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
428 struct sk_buff *skb;
429 void *buf = slot->buf;
430 dma_addr_t dma_addr = slot->dma_addr;
431 u16 len, flags;
432
433 do {
434
435 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
436 bgmac_dma_rx_poison_buf(dma_dev, slot);
437 break;
438 }
439
440
441 dma_unmap_single(dma_dev, dma_addr,
442 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
443
444
445 len = le16_to_cpu(rx->len);
446 flags = le16_to_cpu(rx->flags);
447
448
449 if (len == 0xdead && flags == 0xbeef) {
450 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
451 ring->start);
452 put_page(virt_to_head_page(buf));
453 bgmac->net_dev->stats.rx_errors++;
454 break;
455 }
456
457 if (len > BGMAC_RX_ALLOC_SIZE) {
458 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
459 ring->start);
460 put_page(virt_to_head_page(buf));
461 bgmac->net_dev->stats.rx_length_errors++;
462 bgmac->net_dev->stats.rx_errors++;
463 break;
464 }
465
466
467 len -= ETH_FCS_LEN;
468
469 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
470 if (unlikely(!skb)) {
471 netdev_err(bgmac->net_dev, "build_skb failed\n");
472 put_page(virt_to_head_page(buf));
473 bgmac->net_dev->stats.rx_errors++;
474 break;
475 }
476 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
477 BGMAC_RX_BUF_OFFSET + len);
478 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
479 BGMAC_RX_BUF_OFFSET);
480
481 skb_checksum_none_assert(skb);
482 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
483 bgmac->net_dev->stats.rx_bytes += len;
484 bgmac->net_dev->stats.rx_packets++;
485 napi_gro_receive(&bgmac->napi, skb);
486 handled++;
487 } while (0);
488
489 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
490
491 if (++ring->start >= BGMAC_RX_RING_SLOTS)
492 ring->start = 0;
493
494 if (handled >= weight)
495 break;
496 }
497
498 bgmac_dma_rx_update_index(bgmac, ring);
499
500 return handled;
501}
502
503
504static bool bgmac_dma_unaligned(struct bgmac *bgmac,
505 struct bgmac_dma_ring *ring,
506 enum bgmac_dma_ring_type ring_type)
507{
508 switch (ring_type) {
509 case BGMAC_DMA_RING_TX:
510 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
511 0xff0);
512 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
513 return true;
514 break;
515 case BGMAC_DMA_RING_RX:
516 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
517 0xff0);
518 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
519 return true;
520 break;
521 }
522 return false;
523}
524
525static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
526 struct bgmac_dma_ring *ring)
527{
528 struct device *dma_dev = bgmac->dma_dev;
529 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
530 struct bgmac_slot_info *slot;
531 int i;
532
533 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
534 u32 ctl1 = le32_to_cpu(dma_desc[i].ctl1);
535 unsigned int len = ctl1 & BGMAC_DESC_CTL1_LEN;
536
537 slot = &ring->slots[i];
538 dev_kfree_skb(slot->skb);
539
540 if (!slot->dma_addr)
541 continue;
542
543 if (slot->skb)
544 dma_unmap_single(dma_dev, slot->dma_addr,
545 len, DMA_TO_DEVICE);
546 else
547 dma_unmap_page(dma_dev, slot->dma_addr,
548 len, DMA_TO_DEVICE);
549 }
550}
551
552static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
553 struct bgmac_dma_ring *ring)
554{
555 struct device *dma_dev = bgmac->dma_dev;
556 struct bgmac_slot_info *slot;
557 int i;
558
559 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
560 slot = &ring->slots[i];
561 if (!slot->dma_addr)
562 continue;
563
564 dma_unmap_single(dma_dev, slot->dma_addr,
565 BGMAC_RX_BUF_SIZE,
566 DMA_FROM_DEVICE);
567 put_page(virt_to_head_page(slot->buf));
568 slot->dma_addr = 0;
569 }
570}
571
572static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
573 struct bgmac_dma_ring *ring,
574 int num_slots)
575{
576 struct device *dma_dev = bgmac->dma_dev;
577 int size;
578
579 if (!ring->cpu_base)
580 return;
581
582
583 size = num_slots * sizeof(struct bgmac_dma_desc);
584 dma_free_coherent(dma_dev, size, ring->cpu_base,
585 ring->dma_base);
586}
587
588static void bgmac_dma_cleanup(struct bgmac *bgmac)
589{
590 int i;
591
592 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
593 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
594
595 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
596 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
597}
598
599static void bgmac_dma_free(struct bgmac *bgmac)
600{
601 int i;
602
603 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
604 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
605 BGMAC_TX_RING_SLOTS);
606
607 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
608 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
609 BGMAC_RX_RING_SLOTS);
610}
611
612static int bgmac_dma_alloc(struct bgmac *bgmac)
613{
614 struct device *dma_dev = bgmac->dma_dev;
615 struct bgmac_dma_ring *ring;
616 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
617 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
618 int size;
619 int err;
620 int i;
621
622 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
623 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
624
625 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
626 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
627 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
628 return -ENOTSUPP;
629 }
630 }
631
632 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
633 ring = &bgmac->tx_ring[i];
634 ring->mmio_base = ring_base[i];
635
636
637 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
638 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
639 &ring->dma_base,
640 GFP_KERNEL);
641 if (!ring->cpu_base) {
642 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
643 ring->mmio_base);
644 goto err_dma_free;
645 }
646
647 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
648 BGMAC_DMA_RING_TX);
649 if (ring->unaligned)
650 ring->index_base = lower_32_bits(ring->dma_base);
651 else
652 ring->index_base = 0;
653
654
655 }
656
657 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
658 ring = &bgmac->rx_ring[i];
659 ring->mmio_base = ring_base[i];
660
661
662 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
663 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
664 &ring->dma_base,
665 GFP_KERNEL);
666 if (!ring->cpu_base) {
667 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
668 ring->mmio_base);
669 err = -ENOMEM;
670 goto err_dma_free;
671 }
672
673 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
674 BGMAC_DMA_RING_RX);
675 if (ring->unaligned)
676 ring->index_base = lower_32_bits(ring->dma_base);
677 else
678 ring->index_base = 0;
679 }
680
681 return 0;
682
683err_dma_free:
684 bgmac_dma_free(bgmac);
685 return -ENOMEM;
686}
687
688static int bgmac_dma_init(struct bgmac *bgmac)
689{
690 struct bgmac_dma_ring *ring;
691 int i, err;
692
693 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
694 ring = &bgmac->tx_ring[i];
695
696 if (!ring->unaligned)
697 bgmac_dma_tx_enable(bgmac, ring);
698 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
699 lower_32_bits(ring->dma_base));
700 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
701 upper_32_bits(ring->dma_base));
702 if (ring->unaligned)
703 bgmac_dma_tx_enable(bgmac, ring);
704
705 ring->start = 0;
706 ring->end = 0;
707 }
708
709 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
710 int j;
711
712 ring = &bgmac->rx_ring[i];
713
714 if (!ring->unaligned)
715 bgmac_dma_rx_enable(bgmac, ring);
716 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
717 lower_32_bits(ring->dma_base));
718 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
719 upper_32_bits(ring->dma_base));
720 if (ring->unaligned)
721 bgmac_dma_rx_enable(bgmac, ring);
722
723 ring->start = 0;
724 ring->end = 0;
725 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
726 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
727 if (err)
728 goto error;
729
730 bgmac_dma_rx_setup_desc(bgmac, ring, j);
731 }
732
733 bgmac_dma_rx_update_index(bgmac, ring);
734 }
735
736 return 0;
737
738error:
739 bgmac_dma_cleanup(bgmac);
740 return err;
741}
742
743
744
745
746
747
748
749
750
751static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
752 bool force)
753{
754 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
755 u32 new_val = (cmdcfg & mask) | set;
756 u32 cmdcfg_sr;
757
758 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
759 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
760 else
761 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
762
763 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
764 udelay(2);
765
766 if (new_val != cmdcfg || force)
767 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
768
769 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
770 udelay(2);
771}
772
773static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
774{
775 u32 tmp;
776
777 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
778 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
779 tmp = (addr[4] << 8) | addr[5];
780 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
781}
782
783static void bgmac_set_rx_mode(struct net_device *net_dev)
784{
785 struct bgmac *bgmac = netdev_priv(net_dev);
786
787 if (net_dev->flags & IFF_PROMISC)
788 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
789 else
790 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
791}
792
793#if 0
794static void bgmac_chip_stats_update(struct bgmac *bgmac)
795{
796 int i;
797
798 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
799 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
800 bgmac->mib_tx_regs[i] =
801 bgmac_read(bgmac,
802 BGMAC_TX_GOOD_OCTETS + (i * 4));
803 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
804 bgmac->mib_rx_regs[i] =
805 bgmac_read(bgmac,
806 BGMAC_RX_GOOD_OCTETS + (i * 4));
807 }
808
809
810}
811#endif
812
813static void bgmac_clear_mib(struct bgmac *bgmac)
814{
815 int i;
816
817 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
818 return;
819
820 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
821 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
822 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
823 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
824 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
825}
826
827
828static void bgmac_mac_speed(struct bgmac *bgmac)
829{
830 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
831 u32 set = 0;
832
833 switch (bgmac->mac_speed) {
834 case SPEED_10:
835 set |= BGMAC_CMDCFG_ES_10;
836 break;
837 case SPEED_100:
838 set |= BGMAC_CMDCFG_ES_100;
839 break;
840 case SPEED_1000:
841 set |= BGMAC_CMDCFG_ES_1000;
842 break;
843 case SPEED_2500:
844 set |= BGMAC_CMDCFG_ES_2500;
845 break;
846 default:
847 dev_err(bgmac->dev, "Unsupported speed: %d\n",
848 bgmac->mac_speed);
849 }
850
851 if (bgmac->mac_duplex == DUPLEX_HALF)
852 set |= BGMAC_CMDCFG_HD;
853
854 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
855}
856
857static void bgmac_miiconfig(struct bgmac *bgmac)
858{
859 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
860 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
861 bgmac_idm_write(bgmac, BCMA_IOCTL,
862 bgmac_idm_read(bgmac, BCMA_IOCTL) |
863 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN);
864 }
865 bgmac->mac_speed = SPEED_2500;
866 bgmac->mac_duplex = DUPLEX_FULL;
867 bgmac_mac_speed(bgmac);
868 } else {
869 u8 imode;
870
871 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
872 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
873 if (imode == 0 || imode == 1) {
874 bgmac->mac_speed = SPEED_100;
875 bgmac->mac_duplex = DUPLEX_FULL;
876 bgmac_mac_speed(bgmac);
877 }
878 }
879}
880
881static void bgmac_chip_reset_idm_config(struct bgmac *bgmac)
882{
883 u32 iost;
884
885 iost = bgmac_idm_read(bgmac, BCMA_IOST);
886 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
887 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
888
889
890 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
891 u32 flags = 0;
892
893 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
894 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
895 if (!bgmac->has_robosw)
896 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
897 }
898 bgmac_clk_enable(bgmac, flags);
899 }
900
901 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
902 bgmac_idm_write(bgmac, BCMA_IOCTL,
903 bgmac_idm_read(bgmac, BCMA_IOCTL) &
904 ~BGMAC_BCMA_IOCTL_SW_RESET);
905}
906
907
908static void bgmac_chip_reset(struct bgmac *bgmac)
909{
910 u32 cmdcfg_sr;
911 int i;
912
913 if (bgmac_clk_enabled(bgmac)) {
914 if (!bgmac->stats_grabbed) {
915
916 bgmac->stats_grabbed = true;
917 }
918
919 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
920 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
921
922 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
923 udelay(1);
924
925 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
926 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
927
928
929 }
930
931 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK))
932 bgmac_chip_reset_idm_config(bgmac);
933
934
935 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
936 bgmac_set(bgmac, BCMA_CLKCTLST,
937 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
938 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
939 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
940 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
941 1000);
942 }
943
944 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
945 u8 et_swtype = 0;
946 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
947 BGMAC_CHIPCTL_1_IF_TYPE_MII;
948 char buf[4];
949
950 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
951 if (kstrtou8(buf, 0, &et_swtype))
952 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
953 buf);
954 et_swtype &= 0x0f;
955 et_swtype <<= 4;
956 sw_type = et_swtype;
957 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
958 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
959 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
960 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
961 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
962 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
963 }
964 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
965 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
966 sw_type);
967 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
968 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
969 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
970 u8 et_swtype = 0;
971 char buf[4];
972
973 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
974 if (kstrtou8(buf, 0, &et_swtype))
975 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
976 buf);
977 sw_type = (et_swtype & 0x0f) << 12;
978 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
979 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
980 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
981 }
982 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
983 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
984 sw_type);
985 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
986 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
987 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
988 }
989
990
991
992
993
994
995 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
996 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
997 else
998 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
999
1000 bgmac_cmdcfg_maskset(bgmac,
1001 ~(BGMAC_CMDCFG_TE |
1002 BGMAC_CMDCFG_RE |
1003 BGMAC_CMDCFG_RPI |
1004 BGMAC_CMDCFG_TAI |
1005 BGMAC_CMDCFG_HD |
1006 BGMAC_CMDCFG_ML |
1007 BGMAC_CMDCFG_CFE |
1008 BGMAC_CMDCFG_RL |
1009 BGMAC_CMDCFG_RED |
1010 BGMAC_CMDCFG_PE |
1011 BGMAC_CMDCFG_TPI |
1012 BGMAC_CMDCFG_PAD_EN |
1013 BGMAC_CMDCFG_PF),
1014 BGMAC_CMDCFG_PROM |
1015 BGMAC_CMDCFG_NLC |
1016 BGMAC_CMDCFG_CFE |
1017 cmdcfg_sr,
1018 false);
1019 bgmac->mac_speed = SPEED_UNKNOWN;
1020 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1021
1022 bgmac_clear_mib(bgmac);
1023 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1024 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1025 BCMA_GMAC_CMN_PC_MTE);
1026 else
1027 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1028 bgmac_miiconfig(bgmac);
1029 if (bgmac->mii_bus)
1030 bgmac->mii_bus->reset(bgmac->mii_bus);
1031
1032 netdev_reset_queue(bgmac->net_dev);
1033}
1034
1035static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1036{
1037 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1038}
1039
1040static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1041{
1042 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1043 bgmac_read(bgmac, BGMAC_INT_MASK);
1044}
1045
1046
1047static void bgmac_enable(struct bgmac *bgmac)
1048{
1049 u32 cmdcfg_sr;
1050 u32 cmdcfg;
1051 u32 mode;
1052
1053 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1054 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1055 else
1056 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1057
1058 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1059 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1060 cmdcfg_sr, true);
1061 udelay(2);
1062 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1063 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1064
1065 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1066 BGMAC_DS_MM_SHIFT;
1067 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1068 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1069 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
1070 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1071 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1072
1073 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1074 BGMAC_FEAT_FLW_CTRL2)) {
1075 u32 fl_ctl;
1076
1077 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1078 fl_ctl = 0x2300e1;
1079 else
1080 fl_ctl = 0x03cb04cb;
1081
1082 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1083 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1084 }
1085
1086 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1087 u32 rxq_ctl;
1088 u16 bp_clk;
1089 u8 mdp;
1090
1091 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1092 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1093 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1094 mdp = (bp_clk * 128 / 1000) - 3;
1095 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1096 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1097 }
1098}
1099
1100
1101static void bgmac_chip_init(struct bgmac *bgmac)
1102{
1103
1104 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1105
1106
1107 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1108
1109
1110 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1111
1112 bgmac_set_rx_mode(bgmac->net_dev);
1113
1114 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1115
1116 if (bgmac->loopback)
1117 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1118 else
1119 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1120
1121 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1122
1123 bgmac_chip_intrs_on(bgmac);
1124
1125 bgmac_enable(bgmac);
1126}
1127
1128static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1129{
1130 struct bgmac *bgmac = netdev_priv(dev_id);
1131
1132 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1133 int_status &= bgmac->int_mask;
1134
1135 if (!int_status)
1136 return IRQ_NONE;
1137
1138 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1139 if (int_status)
1140 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1141
1142
1143 bgmac_chip_intrs_off(bgmac);
1144
1145 napi_schedule(&bgmac->napi);
1146
1147 return IRQ_HANDLED;
1148}
1149
1150static int bgmac_poll(struct napi_struct *napi, int weight)
1151{
1152 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1153 int handled = 0;
1154
1155
1156 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1157
1158 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1159 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1160
1161
1162 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1163 return weight;
1164
1165 if (handled < weight) {
1166 napi_complete_done(napi, handled);
1167 bgmac_chip_intrs_on(bgmac);
1168 }
1169
1170 return handled;
1171}
1172
1173
1174
1175
1176
1177static int bgmac_open(struct net_device *net_dev)
1178{
1179 struct bgmac *bgmac = netdev_priv(net_dev);
1180 int err = 0;
1181
1182 bgmac_chip_reset(bgmac);
1183
1184 err = bgmac_dma_init(bgmac);
1185 if (err)
1186 return err;
1187
1188
1189 bgmac_chip_init(bgmac);
1190
1191 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1192 net_dev->name, net_dev);
1193 if (err < 0) {
1194 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1195 bgmac_dma_cleanup(bgmac);
1196 return err;
1197 }
1198 napi_enable(&bgmac->napi);
1199
1200 phy_start(net_dev->phydev);
1201
1202 netif_start_queue(net_dev);
1203
1204 return 0;
1205}
1206
1207static int bgmac_stop(struct net_device *net_dev)
1208{
1209 struct bgmac *bgmac = netdev_priv(net_dev);
1210
1211 netif_carrier_off(net_dev);
1212
1213 phy_stop(net_dev->phydev);
1214
1215 napi_disable(&bgmac->napi);
1216 bgmac_chip_intrs_off(bgmac);
1217 free_irq(bgmac->irq, net_dev);
1218
1219 bgmac_chip_reset(bgmac);
1220 bgmac_dma_cleanup(bgmac);
1221
1222 return 0;
1223}
1224
1225static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1226 struct net_device *net_dev)
1227{
1228 struct bgmac *bgmac = netdev_priv(net_dev);
1229 struct bgmac_dma_ring *ring;
1230
1231
1232 ring = &bgmac->tx_ring[0];
1233 return bgmac_dma_tx_add(bgmac, ring, skb);
1234}
1235
1236static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1237{
1238 struct bgmac *bgmac = netdev_priv(net_dev);
1239 struct sockaddr *sa = addr;
1240 int ret;
1241
1242 ret = eth_prepare_mac_addr_change(net_dev, addr);
1243 if (ret < 0)
1244 return ret;
1245
1246 ether_addr_copy(net_dev->dev_addr, sa->sa_data);
1247 bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1248
1249 eth_commit_mac_addr_change(net_dev, addr);
1250 return 0;
1251}
1252
1253static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1254{
1255 if (!netif_running(net_dev))
1256 return -EINVAL;
1257
1258 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1259}
1260
1261static const struct net_device_ops bgmac_netdev_ops = {
1262 .ndo_open = bgmac_open,
1263 .ndo_stop = bgmac_stop,
1264 .ndo_start_xmit = bgmac_start_xmit,
1265 .ndo_set_rx_mode = bgmac_set_rx_mode,
1266 .ndo_set_mac_address = bgmac_set_mac_address,
1267 .ndo_validate_addr = eth_validate_addr,
1268 .ndo_do_ioctl = bgmac_ioctl,
1269};
1270
1271
1272
1273
1274
1275struct bgmac_stat {
1276 u8 size;
1277 u32 offset;
1278 const char *name;
1279};
1280
1281static struct bgmac_stat bgmac_get_strings_stats[] = {
1282 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1283 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1284 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1285 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1286 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1287 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1288 { 4, BGMAC_TX_LEN_64, "tx_64" },
1289 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1290 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1291 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1292 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1293 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1294 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1295 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1296 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1297 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1298 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1299 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1300 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1301 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1302 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1303 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1304 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1305 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1306 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1307 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1308 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1309 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1310 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1311 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1312 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1313 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1314 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1315 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1316 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1317 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1318 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1319 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1320 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1321 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1322 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1323 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1324 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1325 { 4, BGMAC_RX_LEN_64, "rx_64" },
1326 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1327 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1328 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1329 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1330 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1331 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1332 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1333 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1334 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1335 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1336 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1337 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1338 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1339 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1340 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1341 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1342 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1343 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1344 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1345 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1346 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1347 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1348};
1349
1350#define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1351
1352static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1353{
1354 switch (string_set) {
1355 case ETH_SS_STATS:
1356 return BGMAC_STATS_LEN;
1357 }
1358
1359 return -EOPNOTSUPP;
1360}
1361
1362static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1363 u8 *data)
1364{
1365 int i;
1366
1367 if (stringset != ETH_SS_STATS)
1368 return;
1369
1370 for (i = 0; i < BGMAC_STATS_LEN; i++)
1371 strlcpy(data + i * ETH_GSTRING_LEN,
1372 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1373}
1374
1375static void bgmac_get_ethtool_stats(struct net_device *dev,
1376 struct ethtool_stats *ss, uint64_t *data)
1377{
1378 struct bgmac *bgmac = netdev_priv(dev);
1379 const struct bgmac_stat *s;
1380 unsigned int i;
1381 u64 val;
1382
1383 if (!netif_running(dev))
1384 return;
1385
1386 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1387 s = &bgmac_get_strings_stats[i];
1388 val = 0;
1389 if (s->size == 8)
1390 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1391 val |= bgmac_read(bgmac, s->offset);
1392 data[i] = val;
1393 }
1394}
1395
1396static void bgmac_get_drvinfo(struct net_device *net_dev,
1397 struct ethtool_drvinfo *info)
1398{
1399 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1400 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1401}
1402
1403static const struct ethtool_ops bgmac_ethtool_ops = {
1404 .get_strings = bgmac_get_strings,
1405 .get_sset_count = bgmac_get_sset_count,
1406 .get_ethtool_stats = bgmac_get_ethtool_stats,
1407 .get_drvinfo = bgmac_get_drvinfo,
1408 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1409 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1410};
1411
1412
1413
1414
1415
1416void bgmac_adjust_link(struct net_device *net_dev)
1417{
1418 struct bgmac *bgmac = netdev_priv(net_dev);
1419 struct phy_device *phy_dev = net_dev->phydev;
1420 bool update = false;
1421
1422 if (phy_dev->link) {
1423 if (phy_dev->speed != bgmac->mac_speed) {
1424 bgmac->mac_speed = phy_dev->speed;
1425 update = true;
1426 }
1427
1428 if (phy_dev->duplex != bgmac->mac_duplex) {
1429 bgmac->mac_duplex = phy_dev->duplex;
1430 update = true;
1431 }
1432 }
1433
1434 if (update) {
1435 bgmac_mac_speed(bgmac);
1436 phy_print_status(phy_dev);
1437 }
1438}
1439EXPORT_SYMBOL_GPL(bgmac_adjust_link);
1440
1441int bgmac_phy_connect_direct(struct bgmac *bgmac)
1442{
1443 struct fixed_phy_status fphy_status = {
1444 .link = 1,
1445 .speed = SPEED_1000,
1446 .duplex = DUPLEX_FULL,
1447 };
1448 struct phy_device *phy_dev;
1449 int err;
1450
1451 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1452 if (!phy_dev || IS_ERR(phy_dev)) {
1453 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1454 return -ENODEV;
1455 }
1456
1457 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1458 PHY_INTERFACE_MODE_MII);
1459 if (err) {
1460 dev_err(bgmac->dev, "Connecting PHY failed\n");
1461 return err;
1462 }
1463
1464 return err;
1465}
1466EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
1467
1468struct bgmac *bgmac_alloc(struct device *dev)
1469{
1470 struct net_device *net_dev;
1471 struct bgmac *bgmac;
1472
1473
1474 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
1475 if (!net_dev)
1476 return NULL;
1477
1478 net_dev->netdev_ops = &bgmac_netdev_ops;
1479 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1480
1481 bgmac = netdev_priv(net_dev);
1482 bgmac->dev = dev;
1483 bgmac->net_dev = net_dev;
1484
1485 return bgmac;
1486}
1487EXPORT_SYMBOL_GPL(bgmac_alloc);
1488
1489int bgmac_enet_probe(struct bgmac *bgmac)
1490{
1491 struct net_device *net_dev = bgmac->net_dev;
1492 int err;
1493
1494 bgmac_chip_intrs_off(bgmac);
1495
1496 net_dev->irq = bgmac->irq;
1497 SET_NETDEV_DEV(net_dev, bgmac->dev);
1498 dev_set_drvdata(bgmac->dev, bgmac);
1499
1500 if (!is_valid_ether_addr(net_dev->dev_addr)) {
1501 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1502 net_dev->dev_addr);
1503 eth_hw_addr_random(net_dev);
1504 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1505 net_dev->dev_addr);
1506 }
1507
1508
1509
1510
1511 bgmac_clk_enable(bgmac, 0);
1512
1513
1514 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
1515 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1516 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1517 }
1518
1519 bgmac_chip_reset(bgmac);
1520
1521 err = bgmac_dma_alloc(bgmac);
1522 if (err) {
1523 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1524 goto err_out;
1525 }
1526
1527 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1528 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1529 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1530
1531 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1532
1533 err = bgmac_phy_connect(bgmac);
1534 if (err) {
1535 dev_err(bgmac->dev, "Cannot connect to phy\n");
1536 goto err_dma_free;
1537 }
1538
1539 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1540 net_dev->hw_features = net_dev->features;
1541 net_dev->vlan_features = net_dev->features;
1542
1543 err = register_netdev(bgmac->net_dev);
1544 if (err) {
1545 dev_err(bgmac->dev, "Cannot register net device\n");
1546 goto err_phy_disconnect;
1547 }
1548
1549 netif_carrier_off(net_dev);
1550
1551 return 0;
1552
1553err_phy_disconnect:
1554 phy_disconnect(net_dev->phydev);
1555err_dma_free:
1556 bgmac_dma_free(bgmac);
1557err_out:
1558
1559 return err;
1560}
1561EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1562
1563void bgmac_enet_remove(struct bgmac *bgmac)
1564{
1565 unregister_netdev(bgmac->net_dev);
1566 phy_disconnect(bgmac->net_dev->phydev);
1567 netif_napi_del(&bgmac->napi);
1568 bgmac_dma_free(bgmac);
1569 free_netdev(bgmac->net_dev);
1570}
1571EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1572
1573int bgmac_enet_suspend(struct bgmac *bgmac)
1574{
1575 if (!netif_running(bgmac->net_dev))
1576 return 0;
1577
1578 phy_stop(bgmac->net_dev->phydev);
1579
1580 netif_stop_queue(bgmac->net_dev);
1581
1582 napi_disable(&bgmac->napi);
1583
1584 netif_tx_lock(bgmac->net_dev);
1585 netif_device_detach(bgmac->net_dev);
1586 netif_tx_unlock(bgmac->net_dev);
1587
1588 bgmac_chip_intrs_off(bgmac);
1589 bgmac_chip_reset(bgmac);
1590 bgmac_dma_cleanup(bgmac);
1591
1592 return 0;
1593}
1594EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
1595
1596int bgmac_enet_resume(struct bgmac *bgmac)
1597{
1598 int rc;
1599
1600 if (!netif_running(bgmac->net_dev))
1601 return 0;
1602
1603 rc = bgmac_dma_init(bgmac);
1604 if (rc)
1605 return rc;
1606
1607 bgmac_chip_init(bgmac);
1608
1609 napi_enable(&bgmac->napi);
1610
1611 netif_tx_lock(bgmac->net_dev);
1612 netif_device_attach(bgmac->net_dev);
1613 netif_tx_unlock(bgmac->net_dev);
1614
1615 netif_start_queue(bgmac->net_dev);
1616
1617 phy_start(bgmac->net_dev->phydev);
1618
1619 return 0;
1620}
1621EXPORT_SYMBOL_GPL(bgmac_enet_resume);
1622
1623MODULE_AUTHOR("Rafał Miłecki");
1624MODULE_LICENSE("GPL");
1625
