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36#include <linux/pci.h>
37
38#include "t4vf_common.h"
39#include "t4vf_defs.h"
40
41#include "../cxgb4/t4_regs.h"
42#include "../cxgb4/t4_values.h"
43#include "../cxgb4/t4fw_api.h"
44
45
46
47
48
49
50int t4vf_wait_dev_ready(struct adapter *adapter)
51{
52 const u32 whoami = T4VF_PL_BASE_ADDR + PL_VF_WHOAMI;
53 const u32 notready1 = 0xffffffff;
54 const u32 notready2 = 0xeeeeeeee;
55 u32 val;
56
57 val = t4_read_reg(adapter, whoami);
58 if (val != notready1 && val != notready2)
59 return 0;
60 msleep(500);
61 val = t4_read_reg(adapter, whoami);
62 if (val != notready1 && val != notready2)
63 return 0;
64 else
65 return -EIO;
66}
67
68
69
70
71
72static void get_mbox_rpl(struct adapter *adapter, __be64 *rpl, int size,
73 u32 mbox_data)
74{
75 for ( ; size; size -= 8, mbox_data += 8)
76 *rpl++ = cpu_to_be64(t4_read_reg64(adapter, mbox_data));
77}
78
79
80
81
82
83
84
85
86
87static void t4vf_record_mbox(struct adapter *adapter, const __be64 *cmd,
88 int size, int access, int execute)
89{
90 struct mbox_cmd_log *log = adapter->mbox_log;
91 struct mbox_cmd *entry;
92 int i;
93
94 entry = mbox_cmd_log_entry(log, log->cursor++);
95 if (log->cursor == log->size)
96 log->cursor = 0;
97
98 for (i = 0; i < size / 8; i++)
99 entry->cmd[i] = be64_to_cpu(cmd[i]);
100 while (i < MBOX_LEN / 8)
101 entry->cmd[i++] = 0;
102 entry->timestamp = jiffies;
103 entry->seqno = log->seqno++;
104 entry->access = access;
105 entry->execute = execute;
106}
107
108
109
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125
126
127
128int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
129 void *rpl, bool sleep_ok)
130{
131 static const int delay[] = {
132 1, 1, 3, 5, 10, 10, 20, 50, 100
133 };
134
135 u16 access = 0, execute = 0;
136 u32 v, mbox_data;
137 int i, ms, delay_idx, ret;
138 const __be64 *p;
139 u32 mbox_ctl = T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL;
140 u32 cmd_op = FW_CMD_OP_G(be32_to_cpu(((struct fw_cmd_hdr *)cmd)->hi));
141 __be64 cmd_rpl[MBOX_LEN / 8];
142 struct mbox_list entry;
143
144
145
146
147 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
148 mbox_data = T4VF_MBDATA_BASE_ADDR;
149 else
150 mbox_data = T6VF_MBDATA_BASE_ADDR;
151
152
153
154
155
156 if ((size % 16) != 0 ||
157 size > NUM_CIM_VF_MAILBOX_DATA_INSTANCES * 4)
158 return -EINVAL;
159
160
161
162
163
164
165 spin_lock(&adapter->mbox_lock);
166 list_add_tail(&entry.list, &adapter->mlist.list);
167 spin_unlock(&adapter->mbox_lock);
168
169 delay_idx = 0;
170 ms = delay[0];
171
172 for (i = 0; ; i += ms) {
173
174
175
176
177
178 if (i > FW_CMD_MAX_TIMEOUT) {
179 spin_lock(&adapter->mbox_lock);
180 list_del(&entry.list);
181 spin_unlock(&adapter->mbox_lock);
182 ret = -EBUSY;
183 t4vf_record_mbox(adapter, cmd, size, access, ret);
184 return ret;
185 }
186
187
188
189
190 if (list_first_entry(&adapter->mlist.list, struct mbox_list,
191 list) == &entry)
192 break;
193
194
195 if (sleep_ok) {
196 ms = delay[delay_idx];
197 if (delay_idx < ARRAY_SIZE(delay) - 1)
198 delay_idx++;
199 msleep(ms);
200 } else {
201 mdelay(ms);
202 }
203 }
204
205
206
207
208
209 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
210 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
211 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
212 if (v != MBOX_OWNER_DRV) {
213 spin_lock(&adapter->mbox_lock);
214 list_del(&entry.list);
215 spin_unlock(&adapter->mbox_lock);
216 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
217 t4vf_record_mbox(adapter, cmd, size, access, ret);
218 return ret;
219 }
220
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231
232
233
234 if (cmd_op != FW_VI_STATS_CMD)
235 t4vf_record_mbox(adapter, cmd, size, access, 0);
236 for (i = 0, p = cmd; i < size; i += 8)
237 t4_write_reg64(adapter, mbox_data + i, be64_to_cpu(*p++));
238 t4_read_reg(adapter, mbox_data);
239
240 t4_write_reg(adapter, mbox_ctl,
241 MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
242 t4_read_reg(adapter, mbox_ctl);
243
244
245
246
247 delay_idx = 0;
248 ms = delay[0];
249
250 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
251 if (sleep_ok) {
252 ms = delay[delay_idx];
253 if (delay_idx < ARRAY_SIZE(delay) - 1)
254 delay_idx++;
255 msleep(ms);
256 } else
257 mdelay(ms);
258
259
260
261
262 v = t4_read_reg(adapter, mbox_ctl);
263 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
264
265
266
267
268 if ((v & MBMSGVALID_F) == 0) {
269 t4_write_reg(adapter, mbox_ctl,
270 MBOWNER_V(MBOX_OWNER_NONE));
271 continue;
272 }
273
274
275
276
277
278
279
280
281 get_mbox_rpl(adapter, cmd_rpl, size, mbox_data);
282
283
284 v = be64_to_cpu(cmd_rpl[0]);
285
286 if (rpl) {
287
288 WARN_ON((be32_to_cpu(*(const __be32 *)cmd)
289 & FW_CMD_REQUEST_F) == 0);
290 memcpy(rpl, cmd_rpl, size);
291 WARN_ON((be32_to_cpu(*(__be32 *)rpl)
292 & FW_CMD_REQUEST_F) != 0);
293 }
294 t4_write_reg(adapter, mbox_ctl,
295 MBOWNER_V(MBOX_OWNER_NONE));
296 execute = i + ms;
297 if (cmd_op != FW_VI_STATS_CMD)
298 t4vf_record_mbox(adapter, cmd_rpl, size, access,
299 execute);
300 spin_lock(&adapter->mbox_lock);
301 list_del(&entry.list);
302 spin_unlock(&adapter->mbox_lock);
303 return -FW_CMD_RETVAL_G(v);
304 }
305 }
306
307
308 ret = -ETIMEDOUT;
309 t4vf_record_mbox(adapter, cmd, size, access, ret);
310 spin_lock(&adapter->mbox_lock);
311 list_del(&entry.list);
312 spin_unlock(&adapter->mbox_lock);
313 return ret;
314}
315
316#define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
317 FW_PORT_CAP32_ANEG)
318
319
320
321
322
323
324
325static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
326{
327 fw_port_cap32_t caps32 = 0;
328
329 #define CAP16_TO_CAP32(__cap) \
330 do { \
331 if (caps16 & FW_PORT_CAP_##__cap) \
332 caps32 |= FW_PORT_CAP32_##__cap; \
333 } while (0)
334
335 CAP16_TO_CAP32(SPEED_100M);
336 CAP16_TO_CAP32(SPEED_1G);
337 CAP16_TO_CAP32(SPEED_25G);
338 CAP16_TO_CAP32(SPEED_10G);
339 CAP16_TO_CAP32(SPEED_40G);
340 CAP16_TO_CAP32(SPEED_100G);
341 CAP16_TO_CAP32(FC_RX);
342 CAP16_TO_CAP32(FC_TX);
343 CAP16_TO_CAP32(ANEG);
344 CAP16_TO_CAP32(MDIAUTO);
345 CAP16_TO_CAP32(MDISTRAIGHT);
346 CAP16_TO_CAP32(FEC_RS);
347 CAP16_TO_CAP32(FEC_BASER_RS);
348 CAP16_TO_CAP32(802_3_PAUSE);
349 CAP16_TO_CAP32(802_3_ASM_DIR);
350
351 #undef CAP16_TO_CAP32
352
353 return caps32;
354}
355
356
357static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
358{
359 enum cc_pause cc_pause = 0;
360
361 if (fw_pause & FW_PORT_CAP32_FC_RX)
362 cc_pause |= PAUSE_RX;
363 if (fw_pause & FW_PORT_CAP32_FC_TX)
364 cc_pause |= PAUSE_TX;
365
366 return cc_pause;
367}
368
369
370static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
371{
372 enum cc_fec cc_fec = 0;
373
374 if (fw_fec & FW_PORT_CAP32_FEC_RS)
375 cc_fec |= FEC_RS;
376 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
377 cc_fec |= FEC_BASER_RS;
378
379 return cc_fec;
380}
381
382
383
384
385static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
386{
387 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
388 do { \
389 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
390 return __speed; \
391 } while (0)
392
393 TEST_SPEED_RETURN(400G, 400000);
394 TEST_SPEED_RETURN(200G, 200000);
395 TEST_SPEED_RETURN(100G, 100000);
396 TEST_SPEED_RETURN(50G, 50000);
397 TEST_SPEED_RETURN(40G, 40000);
398 TEST_SPEED_RETURN(25G, 25000);
399 TEST_SPEED_RETURN(10G, 10000);
400 TEST_SPEED_RETURN(1G, 1000);
401 TEST_SPEED_RETURN(100M, 100);
402
403 #undef TEST_SPEED_RETURN
404
405 return 0;
406}
407
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411
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414
415
416static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
417{
418 #define TEST_SPEED_RETURN(__caps_speed) \
419 do { \
420 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
421 return FW_PORT_CAP32_SPEED_##__caps_speed; \
422 } while (0)
423
424 TEST_SPEED_RETURN(400G);
425 TEST_SPEED_RETURN(200G);
426 TEST_SPEED_RETURN(100G);
427 TEST_SPEED_RETURN(50G);
428 TEST_SPEED_RETURN(40G);
429 TEST_SPEED_RETURN(25G);
430 TEST_SPEED_RETURN(10G);
431 TEST_SPEED_RETURN(1G);
432 TEST_SPEED_RETURN(100M);
433
434 #undef TEST_SPEED_RETURN
435 return 0;
436}
437
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445
446
447static void init_link_config(struct link_config *lc,
448 fw_port_cap32_t pcaps,
449 fw_port_cap32_t acaps)
450{
451 lc->pcaps = pcaps;
452 lc->lpacaps = 0;
453 lc->speed_caps = 0;
454 lc->speed = 0;
455 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
456
457
458
459
460 lc->auto_fec = fwcap_to_cc_fec(acaps);
461 lc->requested_fec = FEC_AUTO;
462 lc->fec = lc->auto_fec;
463
464
465
466
467
468
469
470
471 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
472 lc->acaps = acaps & ADVERT_MASK;
473 lc->autoneg = AUTONEG_ENABLE;
474 lc->requested_fc |= PAUSE_AUTONEG;
475 } else {
476 lc->acaps = 0;
477 lc->autoneg = AUTONEG_DISABLE;
478 lc->speed_caps = fwcap_to_fwspeed(acaps);
479 }
480}
481
482
483
484
485
486
487int t4vf_port_init(struct adapter *adapter, int pidx)
488{
489 struct port_info *pi = adap2pinfo(adapter, pidx);
490 unsigned int fw_caps = adapter->params.fw_caps_support;
491 struct fw_vi_cmd vi_cmd, vi_rpl;
492 struct fw_port_cmd port_cmd, port_rpl;
493 enum fw_port_type port_type;
494 int mdio_addr;
495 fw_port_cap32_t pcaps, acaps;
496 int ret;
497
498
499
500
501
502
503
504 if (fw_caps == FW_CAPS_UNKNOWN) {
505 u32 param, val;
506
507 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
508 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
509 val = 1;
510 ret = t4vf_set_params(adapter, 1, ¶m, &val);
511 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
512 adapter->params.fw_caps_support = fw_caps;
513 }
514
515
516
517
518
519 memset(&vi_cmd, 0, sizeof(vi_cmd));
520 vi_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
521 FW_CMD_REQUEST_F |
522 FW_CMD_READ_F);
523 vi_cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(vi_cmd));
524 vi_cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(pi->viid));
525 ret = t4vf_wr_mbox(adapter, &vi_cmd, sizeof(vi_cmd), &vi_rpl);
526 if (ret != FW_SUCCESS)
527 return ret;
528
529 BUG_ON(pi->port_id != FW_VI_CMD_PORTID_G(vi_rpl.portid_pkd));
530 pi->rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(vi_rpl.rsssize_pkd));
531 t4_os_set_hw_addr(adapter, pidx, vi_rpl.mac);
532
533
534
535
536
537 if (!(adapter->params.vfres.r_caps & FW_CMD_CAP_PORT))
538 return 0;
539
540 memset(&port_cmd, 0, sizeof(port_cmd));
541 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
542 FW_CMD_REQUEST_F |
543 FW_CMD_READ_F |
544 FW_PORT_CMD_PORTID_V(pi->port_id));
545 port_cmd.action_to_len16 = cpu_to_be32(
546 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
547 ? FW_PORT_ACTION_GET_PORT_INFO
548 : FW_PORT_ACTION_GET_PORT_INFO32) |
549 FW_LEN16(port_cmd));
550 ret = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd), &port_rpl);
551 if (ret != FW_SUCCESS)
552 return ret;
553
554
555 if (fw_caps == FW_CAPS16) {
556 u32 lstatus = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype);
557
558 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
559 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
560 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
561 : -1);
562 pcaps = fwcaps16_to_caps32(be16_to_cpu(port_rpl.u.info.pcap));
563 acaps = fwcaps16_to_caps32(be16_to_cpu(port_rpl.u.info.acap));
564 } else {
565 u32 lstatus32 =
566 be32_to_cpu(port_rpl.u.info32.lstatus32_to_cbllen32);
567
568 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
569 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
570 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
571 : -1);
572 pcaps = be32_to_cpu(port_rpl.u.info32.pcaps32);
573 acaps = be32_to_cpu(port_rpl.u.info32.acaps32);
574 }
575
576 pi->port_type = port_type;
577 pi->mdio_addr = mdio_addr;
578 pi->mod_type = FW_PORT_MOD_TYPE_NA;
579
580 init_link_config(&pi->link_cfg, pcaps, acaps);
581 return 0;
582}
583
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590
591
592int t4vf_fw_reset(struct adapter *adapter)
593{
594 struct fw_reset_cmd cmd;
595
596 memset(&cmd, 0, sizeof(cmd));
597 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RESET_CMD) |
598 FW_CMD_WRITE_F);
599 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
600 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
601}
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611
612
613static int t4vf_query_params(struct adapter *adapter, unsigned int nparams,
614 const u32 *params, u32 *vals)
615{
616 int i, ret;
617 struct fw_params_cmd cmd, rpl;
618 struct fw_params_param *p;
619 size_t len16;
620
621 if (nparams > 7)
622 return -EINVAL;
623
624 memset(&cmd, 0, sizeof(cmd));
625 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
626 FW_CMD_REQUEST_F |
627 FW_CMD_READ_F);
628 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
629 param[nparams].mnem), 16);
630 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
631 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++)
632 p->mnem = htonl(*params++);
633
634 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
635 if (ret == 0)
636 for (i = 0, p = &rpl.param[0]; i < nparams; i++, p++)
637 *vals++ = be32_to_cpu(p->val);
638 return ret;
639}
640
641
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643
644
645
646
647
648
649
650
651int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
652 const u32 *params, const u32 *vals)
653{
654 int i;
655 struct fw_params_cmd cmd;
656 struct fw_params_param *p;
657 size_t len16;
658
659 if (nparams > 7)
660 return -EINVAL;
661
662 memset(&cmd, 0, sizeof(cmd));
663 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
664 FW_CMD_REQUEST_F |
665 FW_CMD_WRITE_F);
666 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
667 param[nparams]), 16);
668 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
669 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++) {
670 p->mnem = cpu_to_be32(*params++);
671 p->val = cpu_to_be32(*vals++);
672 }
673
674 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
675}
676
677
678
679
680
681
682
683
684
685
686
687
688int t4vf_fl_pkt_align(struct adapter *adapter)
689{
690 u32 sge_control, sge_control2;
691 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
692
693 sge_control = adapter->params.sge.sge_control;
694
695
696
697
698
699
700
701
702
703
704
705
706
707 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
708 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
709 else
710 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
711
712 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
713
714 fl_align = ingpadboundary;
715 if (!is_t4(adapter->params.chip)) {
716
717
718
719 sge_control2 = adapter->params.sge.sge_control2;
720 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
721 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
722 ingpackboundary = 16;
723 else
724 ingpackboundary = 1 << (ingpackboundary +
725 INGPACKBOUNDARY_SHIFT_X);
726
727 fl_align = max(ingpadboundary, ingpackboundary);
728 }
729 return fl_align;
730}
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756
757int t4vf_bar2_sge_qregs(struct adapter *adapter,
758 unsigned int qid,
759 enum t4_bar2_qtype qtype,
760 u64 *pbar2_qoffset,
761 unsigned int *pbar2_qid)
762{
763 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
764 u64 bar2_page_offset, bar2_qoffset;
765 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
766
767
768
769 if (is_t4(adapter->params.chip))
770 return -EINVAL;
771
772
773
774 page_shift = adapter->params.sge.sge_vf_hps + 10;
775 page_size = 1 << page_shift;
776
777
778
779 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
780 ? adapter->params.sge.sge_vf_eq_qpp
781 : adapter->params.sge.sge_vf_iq_qpp);
782 qpp_mask = (1 << qpp_shift) - 1;
783
784
785
786
787
788
789 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
790 bar2_qid = qid & qpp_mask;
791 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809 bar2_qoffset = bar2_page_offset;
810 bar2_qinferred = (bar2_qid_offset < page_size);
811 if (bar2_qinferred) {
812 bar2_qoffset += bar2_qid_offset;
813 bar2_qid = 0;
814 }
815
816 *pbar2_qoffset = bar2_qoffset;
817 *pbar2_qid = bar2_qid;
818 return 0;
819}
820
821unsigned int t4vf_get_pf_from_vf(struct adapter *adapter)
822{
823 u32 whoami;
824
825 whoami = t4_read_reg(adapter, T4VF_PL_BASE_ADDR + PL_VF_WHOAMI_A);
826 return (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
827 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami));
828}
829
830
831
832
833
834
835
836
837
838int t4vf_get_sge_params(struct adapter *adapter)
839{
840 struct sge_params *sge_params = &adapter->params.sge;
841 u32 params[7], vals[7];
842 int v;
843
844 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
845 FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL_A));
846 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
847 FW_PARAMS_PARAM_XYZ_V(SGE_HOST_PAGE_SIZE_A));
848 params[2] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
849 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE0_A));
850 params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
851 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A));
852 params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
853 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1_A));
854 params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
855 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3_A));
856 params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
857 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5_A));
858 v = t4vf_query_params(adapter, 7, params, vals);
859 if (v)
860 return v;
861 sge_params->sge_control = vals[0];
862 sge_params->sge_host_page_size = vals[1];
863 sge_params->sge_fl_buffer_size[0] = vals[2];
864 sge_params->sge_fl_buffer_size[1] = vals[3];
865 sge_params->sge_timer_value_0_and_1 = vals[4];
866 sge_params->sge_timer_value_2_and_3 = vals[5];
867 sge_params->sge_timer_value_4_and_5 = vals[6];
868
869
870
871
872
873
874
875
876
877
878
879 if (!is_t4(adapter->params.chip)) {
880 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
881 FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL2_A));
882 v = t4vf_query_params(adapter, 1, params, vals);
883 if (v != FW_SUCCESS) {
884 dev_err(adapter->pdev_dev,
885 "Unable to get SGE Control2; "
886 "probably old firmware.\n");
887 return v;
888 }
889 sge_params->sge_control2 = vals[0];
890 }
891
892 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
893 FW_PARAMS_PARAM_XYZ_V(SGE_INGRESS_RX_THRESHOLD_A));
894 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
895 FW_PARAMS_PARAM_XYZ_V(SGE_CONM_CTRL_A));
896 v = t4vf_query_params(adapter, 2, params, vals);
897 if (v)
898 return v;
899 sge_params->sge_ingress_rx_threshold = vals[0];
900 sge_params->sge_congestion_control = vals[1];
901
902
903
904
905
906 if (!is_t4(adapter->params.chip)) {
907 unsigned int pf, s_hps, s_qpp;
908
909 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
910 FW_PARAMS_PARAM_XYZ_V(
911 SGE_EGRESS_QUEUES_PER_PAGE_VF_A));
912 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
913 FW_PARAMS_PARAM_XYZ_V(
914 SGE_INGRESS_QUEUES_PER_PAGE_VF_A));
915 v = t4vf_query_params(adapter, 2, params, vals);
916 if (v != FW_SUCCESS) {
917 dev_warn(adapter->pdev_dev,
918 "Unable to get VF SGE Queues/Page; "
919 "probably old firmware.\n");
920 return v;
921 }
922 sge_params->sge_egress_queues_per_page = vals[0];
923 sge_params->sge_ingress_queues_per_page = vals[1];
924
925
926
927
928
929
930 pf = t4vf_get_pf_from_vf(adapter);
931 s_hps = (HOSTPAGESIZEPF0_S +
932 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * pf);
933 sge_params->sge_vf_hps =
934 ((sge_params->sge_host_page_size >> s_hps)
935 & HOSTPAGESIZEPF0_M);
936
937 s_qpp = (QUEUESPERPAGEPF0_S +
938 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * pf);
939 sge_params->sge_vf_eq_qpp =
940 ((sge_params->sge_egress_queues_per_page >> s_qpp)
941 & QUEUESPERPAGEPF0_M);
942 sge_params->sge_vf_iq_qpp =
943 ((sge_params->sge_ingress_queues_per_page >> s_qpp)
944 & QUEUESPERPAGEPF0_M);
945 }
946
947 return 0;
948}
949
950
951
952
953
954
955
956
957int t4vf_get_vpd_params(struct adapter *adapter)
958{
959 struct vpd_params *vpd_params = &adapter->params.vpd;
960 u32 params[7], vals[7];
961 int v;
962
963 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
964 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
965 v = t4vf_query_params(adapter, 1, params, vals);
966 if (v)
967 return v;
968 vpd_params->cclk = vals[0];
969
970 return 0;
971}
972
973
974
975
976
977
978
979
980int t4vf_get_dev_params(struct adapter *adapter)
981{
982 struct dev_params *dev_params = &adapter->params.dev;
983 u32 params[7], vals[7];
984 int v;
985
986 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
987 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWREV));
988 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
989 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPREV));
990 v = t4vf_query_params(adapter, 2, params, vals);
991 if (v)
992 return v;
993 dev_params->fwrev = vals[0];
994 dev_params->tprev = vals[1];
995
996 return 0;
997}
998
999
1000
1001
1002
1003
1004
1005
1006int t4vf_get_rss_glb_config(struct adapter *adapter)
1007{
1008 struct rss_params *rss = &adapter->params.rss;
1009 struct fw_rss_glb_config_cmd cmd, rpl;
1010 int v;
1011
1012
1013
1014
1015
1016 memset(&cmd, 0, sizeof(cmd));
1017 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
1018 FW_CMD_REQUEST_F |
1019 FW_CMD_READ_F);
1020 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1021 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1022 if (v)
1023 return v;
1024
1025
1026
1027
1028
1029
1030
1031 rss->mode = FW_RSS_GLB_CONFIG_CMD_MODE_G(
1032 be32_to_cpu(rpl.u.manual.mode_pkd));
1033 switch (rss->mode) {
1034 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
1035 u32 word = be32_to_cpu(
1036 rpl.u.basicvirtual.synmapen_to_hashtoeplitz);
1037
1038 rss->u.basicvirtual.synmapen =
1039 ((word & FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F) != 0);
1040 rss->u.basicvirtual.syn4tupenipv6 =
1041 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F) != 0);
1042 rss->u.basicvirtual.syn2tupenipv6 =
1043 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F) != 0);
1044 rss->u.basicvirtual.syn4tupenipv4 =
1045 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F) != 0);
1046 rss->u.basicvirtual.syn2tupenipv4 =
1047 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F) != 0);
1048
1049 rss->u.basicvirtual.ofdmapen =
1050 ((word & FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F) != 0);
1051
1052 rss->u.basicvirtual.tnlmapen =
1053 ((word & FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F) != 0);
1054 rss->u.basicvirtual.tnlalllookup =
1055 ((word & FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F) != 0);
1056
1057 rss->u.basicvirtual.hashtoeplitz =
1058 ((word & FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F) != 0);
1059
1060
1061 if (!rss->u.basicvirtual.tnlmapen)
1062 return -EINVAL;
1063 break;
1064 }
1065
1066 default:
1067
1068 return -EINVAL;
1069 }
1070
1071 return 0;
1072}
1073
1074
1075
1076
1077
1078
1079
1080
1081int t4vf_get_vfres(struct adapter *adapter)
1082{
1083 struct vf_resources *vfres = &adapter->params.vfres;
1084 struct fw_pfvf_cmd cmd, rpl;
1085 int v;
1086 u32 word;
1087
1088
1089
1090
1091
1092 memset(&cmd, 0, sizeof(cmd));
1093 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
1094 FW_CMD_REQUEST_F |
1095 FW_CMD_READ_F);
1096 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1097 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1098 if (v)
1099 return v;
1100
1101
1102
1103
1104 word = be32_to_cpu(rpl.niqflint_niq);
1105 vfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
1106 vfres->niq = FW_PFVF_CMD_NIQ_G(word);
1107
1108 word = be32_to_cpu(rpl.type_to_neq);
1109 vfres->neq = FW_PFVF_CMD_NEQ_G(word);
1110 vfres->pmask = FW_PFVF_CMD_PMASK_G(word);
1111
1112 word = be32_to_cpu(rpl.tc_to_nexactf);
1113 vfres->tc = FW_PFVF_CMD_TC_G(word);
1114 vfres->nvi = FW_PFVF_CMD_NVI_G(word);
1115 vfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
1116
1117 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
1118 vfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
1119 vfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
1120 vfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
1121
1122 return 0;
1123}
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134int t4vf_read_rss_vi_config(struct adapter *adapter, unsigned int viid,
1135 union rss_vi_config *config)
1136{
1137 struct fw_rss_vi_config_cmd cmd, rpl;
1138 int v;
1139
1140 memset(&cmd, 0, sizeof(cmd));
1141 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
1142 FW_CMD_REQUEST_F |
1143 FW_CMD_READ_F |
1144 FW_RSS_VI_CONFIG_CMD_VIID(viid));
1145 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1146 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1147 if (v)
1148 return v;
1149
1150 switch (adapter->params.rss.mode) {
1151 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
1152 u32 word = be32_to_cpu(rpl.u.basicvirtual.defaultq_to_udpen);
1153
1154 config->basicvirtual.ip6fourtupen =
1155 ((word & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) != 0);
1156 config->basicvirtual.ip6twotupen =
1157 ((word & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F) != 0);
1158 config->basicvirtual.ip4fourtupen =
1159 ((word & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) != 0);
1160 config->basicvirtual.ip4twotupen =
1161 ((word & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F) != 0);
1162 config->basicvirtual.udpen =
1163 ((word & FW_RSS_VI_CONFIG_CMD_UDPEN_F) != 0);
1164 config->basicvirtual.defaultq =
1165 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(word);
1166 break;
1167 }
1168
1169 default:
1170 return -EINVAL;
1171 }
1172
1173 return 0;
1174}
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185int t4vf_write_rss_vi_config(struct adapter *adapter, unsigned int viid,
1186 union rss_vi_config *config)
1187{
1188 struct fw_rss_vi_config_cmd cmd, rpl;
1189
1190 memset(&cmd, 0, sizeof(cmd));
1191 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
1192 FW_CMD_REQUEST_F |
1193 FW_CMD_WRITE_F |
1194 FW_RSS_VI_CONFIG_CMD_VIID(viid));
1195 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1196 switch (adapter->params.rss.mode) {
1197 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
1198 u32 word = 0;
1199
1200 if (config->basicvirtual.ip6fourtupen)
1201 word |= FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F;
1202 if (config->basicvirtual.ip6twotupen)
1203 word |= FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F;
1204 if (config->basicvirtual.ip4fourtupen)
1205 word |= FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F;
1206 if (config->basicvirtual.ip4twotupen)
1207 word |= FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F;
1208 if (config->basicvirtual.udpen)
1209 word |= FW_RSS_VI_CONFIG_CMD_UDPEN_F;
1210 word |= FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(
1211 config->basicvirtual.defaultq);
1212 cmd.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(word);
1213 break;
1214 }
1215
1216 default:
1217 return -EINVAL;
1218 }
1219
1220 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1221}
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238int t4vf_config_rss_range(struct adapter *adapter, unsigned int viid,
1239 int start, int n, const u16 *rspq, int nrspq)
1240{
1241 const u16 *rsp = rspq;
1242 const u16 *rsp_end = rspq+nrspq;
1243 struct fw_rss_ind_tbl_cmd cmd;
1244
1245
1246
1247
1248 memset(&cmd, 0, sizeof(cmd));
1249 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
1250 FW_CMD_REQUEST_F |
1251 FW_CMD_WRITE_F |
1252 FW_RSS_IND_TBL_CMD_VIID_V(viid));
1253 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1254
1255
1256
1257
1258
1259
1260
1261 while (n > 0) {
1262 __be32 *qp = &cmd.iq0_to_iq2;
1263 int nq = min(n, 32);
1264 int ret;
1265
1266
1267
1268
1269
1270 cmd.niqid = cpu_to_be16(nq);
1271 cmd.startidx = cpu_to_be16(start);
1272
1273
1274
1275
1276 start += nq;
1277 n -= nq;
1278
1279
1280
1281
1282
1283
1284 while (nq > 0) {
1285
1286
1287
1288
1289
1290
1291 u16 qbuf[3];
1292 u16 *qbp = qbuf;
1293 int nqbuf = min(3, nq);
1294
1295 nq -= nqbuf;
1296 qbuf[0] = qbuf[1] = qbuf[2] = 0;
1297 while (nqbuf) {
1298 nqbuf--;
1299 *qbp++ = *rsp++;
1300 if (rsp >= rsp_end)
1301 rsp = rspq;
1302 }
1303 *qp++ = cpu_to_be32(FW_RSS_IND_TBL_CMD_IQ0_V(qbuf[0]) |
1304 FW_RSS_IND_TBL_CMD_IQ1_V(qbuf[1]) |
1305 FW_RSS_IND_TBL_CMD_IQ2_V(qbuf[2]));
1306 }
1307
1308
1309
1310
1311
1312 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1313 if (ret)
1314 return ret;
1315 }
1316 return 0;
1317}
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328int t4vf_alloc_vi(struct adapter *adapter, int port_id)
1329{
1330 struct fw_vi_cmd cmd, rpl;
1331 int v;
1332
1333
1334
1335
1336
1337 memset(&cmd, 0, sizeof(cmd));
1338 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
1339 FW_CMD_REQUEST_F |
1340 FW_CMD_WRITE_F |
1341 FW_CMD_EXEC_F);
1342 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
1343 FW_VI_CMD_ALLOC_F);
1344 cmd.portid_pkd = FW_VI_CMD_PORTID_V(port_id);
1345 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1346 if (v)
1347 return v;
1348
1349 return FW_VI_CMD_VIID_G(be16_to_cpu(rpl.type_viid));
1350}
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360int t4vf_free_vi(struct adapter *adapter, int viid)
1361{
1362 struct fw_vi_cmd cmd;
1363
1364
1365
1366
1367 memset(&cmd, 0, sizeof(cmd));
1368 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
1369 FW_CMD_REQUEST_F |
1370 FW_CMD_EXEC_F);
1371 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
1372 FW_VI_CMD_FREE_F);
1373 cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
1374 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1375}
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386int t4vf_enable_vi(struct adapter *adapter, unsigned int viid,
1387 bool rx_en, bool tx_en)
1388{
1389 struct fw_vi_enable_cmd cmd;
1390
1391 memset(&cmd, 0, sizeof(cmd));
1392 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
1393 FW_CMD_REQUEST_F |
1394 FW_CMD_EXEC_F |
1395 FW_VI_ENABLE_CMD_VIID_V(viid));
1396 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
1397 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
1398 FW_LEN16(cmd));
1399 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1400}
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414int t4vf_enable_pi(struct adapter *adapter, struct port_info *pi,
1415 bool rx_en, bool tx_en)
1416{
1417 int ret = t4vf_enable_vi(adapter, pi->viid, rx_en, tx_en);
1418
1419 if (ret)
1420 return ret;
1421 t4vf_os_link_changed(adapter, pi->pidx,
1422 rx_en && tx_en && pi->link_cfg.link_ok);
1423 return 0;
1424}
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434int t4vf_identify_port(struct adapter *adapter, unsigned int viid,
1435 unsigned int nblinks)
1436{
1437 struct fw_vi_enable_cmd cmd;
1438
1439 memset(&cmd, 0, sizeof(cmd));
1440 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
1441 FW_CMD_REQUEST_F |
1442 FW_CMD_EXEC_F |
1443 FW_VI_ENABLE_CMD_VIID_V(viid));
1444 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F |
1445 FW_LEN16(cmd));
1446 cmd.blinkdur = cpu_to_be16(nblinks);
1447 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1448}
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463int t4vf_set_rxmode(struct adapter *adapter, unsigned int viid,
1464 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1465 bool sleep_ok)
1466{
1467 struct fw_vi_rxmode_cmd cmd;
1468
1469
1470 if (mtu < 0)
1471 mtu = FW_VI_RXMODE_CMD_MTU_M;
1472 if (promisc < 0)
1473 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
1474 if (all_multi < 0)
1475 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
1476 if (bcast < 0)
1477 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
1478 if (vlanex < 0)
1479 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
1480
1481 memset(&cmd, 0, sizeof(cmd));
1482 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
1483 FW_CMD_REQUEST_F |
1484 FW_CMD_WRITE_F |
1485 FW_VI_RXMODE_CMD_VIID_V(viid));
1486 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1487 cmd.mtu_to_vlanexen =
1488 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
1489 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
1490 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
1491 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
1492 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
1493 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1494}
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
1518 unsigned int naddr, const u8 **addr, u16 *idx,
1519 u64 *hash, bool sleep_ok)
1520{
1521 int offset, ret = 0;
1522 unsigned nfilters = 0;
1523 unsigned int rem = naddr;
1524 struct fw_vi_mac_cmd cmd, rpl;
1525 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1526
1527 if (naddr > max_naddr)
1528 return -EINVAL;
1529
1530 for (offset = 0; offset < naddr; ) {
1531 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact)
1532 ? rem
1533 : ARRAY_SIZE(cmd.u.exact));
1534 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1535 u.exact[fw_naddr]), 16);
1536 struct fw_vi_mac_exact *p;
1537 int i;
1538
1539 memset(&cmd, 0, sizeof(cmd));
1540 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1541 FW_CMD_REQUEST_F |
1542 FW_CMD_WRITE_F |
1543 (free ? FW_CMD_EXEC_F : 0) |
1544 FW_VI_MAC_CMD_VIID_V(viid));
1545 cmd.freemacs_to_len16 =
1546 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
1547 FW_CMD_LEN16_V(len16));
1548
1549 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1550 p->valid_to_idx = cpu_to_be16(
1551 FW_VI_MAC_CMD_VALID_F |
1552 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
1553 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1554 }
1555
1556
1557 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &rpl,
1558 sleep_ok);
1559 if (ret && ret != -ENOMEM)
1560 break;
1561
1562 for (i = 0, p = rpl.u.exact; i < fw_naddr; i++, p++) {
1563 u16 index = FW_VI_MAC_CMD_IDX_G(
1564 be16_to_cpu(p->valid_to_idx));
1565
1566 if (idx)
1567 idx[offset+i] =
1568 (index >= max_naddr
1569 ? 0xffff
1570 : index);
1571 if (index < max_naddr)
1572 nfilters++;
1573 else if (hash)
1574 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
1575 }
1576
1577 free = false;
1578 offset += fw_naddr;
1579 rem -= fw_naddr;
1580 }
1581
1582
1583
1584
1585
1586 if (ret == 0 || ret == -ENOMEM)
1587 ret = nfilters;
1588 return ret;
1589}
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603int t4vf_free_mac_filt(struct adapter *adapter, unsigned int viid,
1604 unsigned int naddr, const u8 **addr, bool sleep_ok)
1605{
1606 int offset, ret = 0;
1607 struct fw_vi_mac_cmd cmd;
1608 unsigned int nfilters = 0;
1609 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1610 unsigned int rem = naddr;
1611
1612 if (naddr > max_naddr)
1613 return -EINVAL;
1614
1615 for (offset = 0; offset < (int)naddr ; ) {
1616 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact) ?
1617 rem : ARRAY_SIZE(cmd.u.exact));
1618 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1619 u.exact[fw_naddr]), 16);
1620 struct fw_vi_mac_exact *p;
1621 int i;
1622
1623 memset(&cmd, 0, sizeof(cmd));
1624 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1625 FW_CMD_REQUEST_F |
1626 FW_CMD_WRITE_F |
1627 FW_CMD_EXEC_V(0) |
1628 FW_VI_MAC_CMD_VIID_V(viid));
1629 cmd.freemacs_to_len16 =
1630 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
1631 FW_CMD_LEN16_V(len16));
1632
1633 for (i = 0, p = cmd.u.exact; i < (int)fw_naddr; i++, p++) {
1634 p->valid_to_idx = cpu_to_be16(
1635 FW_VI_MAC_CMD_VALID_F |
1636 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
1637 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1638 }
1639
1640 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &cmd,
1641 sleep_ok);
1642 if (ret)
1643 break;
1644
1645 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1646 u16 index = FW_VI_MAC_CMD_IDX_G(
1647 be16_to_cpu(p->valid_to_idx));
1648
1649 if (index < max_naddr)
1650 nfilters++;
1651 }
1652
1653 offset += fw_naddr;
1654 rem -= fw_naddr;
1655 }
1656
1657 if (ret == 0)
1658 ret = nfilters;
1659 return ret;
1660}
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
1681 int idx, const u8 *addr, bool persist)
1682{
1683 int ret;
1684 struct fw_vi_mac_cmd cmd, rpl;
1685 struct fw_vi_mac_exact *p = &cmd.u.exact[0];
1686 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1687 u.exact[1]), 16);
1688 unsigned int max_mac_addr = adapter->params.arch.mps_tcam_size;
1689
1690
1691
1692
1693
1694 if (idx < 0)
1695 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
1696
1697 memset(&cmd, 0, sizeof(cmd));
1698 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1699 FW_CMD_REQUEST_F |
1700 FW_CMD_WRITE_F |
1701 FW_VI_MAC_CMD_VIID_V(viid));
1702 cmd.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
1703 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
1704 FW_VI_MAC_CMD_IDX_V(idx));
1705 memcpy(p->macaddr, addr, sizeof(p->macaddr));
1706
1707 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1708 if (ret == 0) {
1709 p = &rpl.u.exact[0];
1710 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
1711 if (ret >= max_mac_addr)
1712 ret = -ENOMEM;
1713 }
1714 return ret;
1715}
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727int t4vf_set_addr_hash(struct adapter *adapter, unsigned int viid,
1728 bool ucast, u64 vec, bool sleep_ok)
1729{
1730 struct fw_vi_mac_cmd cmd;
1731 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1732 u.exact[0]), 16);
1733
1734 memset(&cmd, 0, sizeof(cmd));
1735 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1736 FW_CMD_REQUEST_F |
1737 FW_CMD_WRITE_F |
1738 FW_VI_ENABLE_CMD_VIID_V(viid));
1739 cmd.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
1740 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
1741 FW_CMD_LEN16_V(len16));
1742 cmd.u.hash.hashvec = cpu_to_be64(vec);
1743 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1744}
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754int t4vf_get_port_stats(struct adapter *adapter, int pidx,
1755 struct t4vf_port_stats *s)
1756{
1757 struct port_info *pi = adap2pinfo(adapter, pidx);
1758 struct fw_vi_stats_vf fwstats;
1759 unsigned int rem = VI_VF_NUM_STATS;
1760 __be64 *fwsp = (__be64 *)&fwstats;
1761
1762
1763
1764
1765
1766
1767 while (rem) {
1768 unsigned int ix = VI_VF_NUM_STATS - rem;
1769 unsigned int nstats = min(6U, rem);
1770 struct fw_vi_stats_cmd cmd, rpl;
1771 size_t len = (offsetof(struct fw_vi_stats_cmd, u) +
1772 sizeof(struct fw_vi_stats_ctl));
1773 size_t len16 = DIV_ROUND_UP(len, 16);
1774 int ret;
1775
1776 memset(&cmd, 0, sizeof(cmd));
1777 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_STATS_CMD) |
1778 FW_VI_STATS_CMD_VIID_V(pi->viid) |
1779 FW_CMD_REQUEST_F |
1780 FW_CMD_READ_F);
1781 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
1782 cmd.u.ctl.nstats_ix =
1783 cpu_to_be16(FW_VI_STATS_CMD_IX_V(ix) |
1784 FW_VI_STATS_CMD_NSTATS_V(nstats));
1785 ret = t4vf_wr_mbox_ns(adapter, &cmd, len, &rpl);
1786 if (ret)
1787 return ret;
1788
1789 memcpy(fwsp, &rpl.u.ctl.stat0, sizeof(__be64) * nstats);
1790
1791 rem -= nstats;
1792 fwsp += nstats;
1793 }
1794
1795
1796
1797
1798 s->tx_bcast_bytes = be64_to_cpu(fwstats.tx_bcast_bytes);
1799 s->tx_bcast_frames = be64_to_cpu(fwstats.tx_bcast_frames);
1800 s->tx_mcast_bytes = be64_to_cpu(fwstats.tx_mcast_bytes);
1801 s->tx_mcast_frames = be64_to_cpu(fwstats.tx_mcast_frames);
1802 s->tx_ucast_bytes = be64_to_cpu(fwstats.tx_ucast_bytes);
1803 s->tx_ucast_frames = be64_to_cpu(fwstats.tx_ucast_frames);
1804 s->tx_drop_frames = be64_to_cpu(fwstats.tx_drop_frames);
1805 s->tx_offload_bytes = be64_to_cpu(fwstats.tx_offload_bytes);
1806 s->tx_offload_frames = be64_to_cpu(fwstats.tx_offload_frames);
1807
1808 s->rx_bcast_bytes = be64_to_cpu(fwstats.rx_bcast_bytes);
1809 s->rx_bcast_frames = be64_to_cpu(fwstats.rx_bcast_frames);
1810 s->rx_mcast_bytes = be64_to_cpu(fwstats.rx_mcast_bytes);
1811 s->rx_mcast_frames = be64_to_cpu(fwstats.rx_mcast_frames);
1812 s->rx_ucast_bytes = be64_to_cpu(fwstats.rx_ucast_bytes);
1813 s->rx_ucast_frames = be64_to_cpu(fwstats.rx_ucast_frames);
1814
1815 s->rx_err_frames = be64_to_cpu(fwstats.rx_err_frames);
1816
1817 return 0;
1818}
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830int t4vf_iq_free(struct adapter *adapter, unsigned int iqtype,
1831 unsigned int iqid, unsigned int fl0id, unsigned int fl1id)
1832{
1833 struct fw_iq_cmd cmd;
1834
1835 memset(&cmd, 0, sizeof(cmd));
1836 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) |
1837 FW_CMD_REQUEST_F |
1838 FW_CMD_EXEC_F);
1839 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F |
1840 FW_LEN16(cmd));
1841 cmd.type_to_iqandstindex =
1842 cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
1843
1844 cmd.iqid = cpu_to_be16(iqid);
1845 cmd.fl0id = cpu_to_be16(fl0id);
1846 cmd.fl1id = cpu_to_be16(fl1id);
1847 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1848}
1849
1850
1851
1852
1853
1854
1855
1856
1857int t4vf_eth_eq_free(struct adapter *adapter, unsigned int eqid)
1858{
1859 struct fw_eq_eth_cmd cmd;
1860
1861 memset(&cmd, 0, sizeof(cmd));
1862 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
1863 FW_CMD_REQUEST_F |
1864 FW_CMD_EXEC_F);
1865 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F |
1866 FW_LEN16(cmd));
1867 cmd.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
1868 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1869}
1870
1871
1872
1873
1874
1875
1876
1877static const char *t4vf_link_down_rc_str(unsigned char link_down_rc)
1878{
1879 static const char * const reason[] = {
1880 "Link Down",
1881 "Remote Fault",
1882 "Auto-negotiation Failure",
1883 "Reserved",
1884 "Insufficient Airflow",
1885 "Unable To Determine Reason",
1886 "No RX Signal Detected",
1887 "Reserved",
1888 };
1889
1890 if (link_down_rc >= ARRAY_SIZE(reason))
1891 return "Bad Reason Code";
1892
1893 return reason[link_down_rc];
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903static void t4vf_handle_get_port_info(struct port_info *pi,
1904 const struct fw_port_cmd *cmd)
1905{
1906 int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
1907 struct adapter *adapter = pi->adapter;
1908 struct link_config *lc = &pi->link_cfg;
1909 int link_ok, linkdnrc;
1910 enum fw_port_type port_type;
1911 enum fw_port_module_type mod_type;
1912 unsigned int speed, fc, fec;
1913 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
1914
1915
1916 switch (action) {
1917 case FW_PORT_ACTION_GET_PORT_INFO: {
1918 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
1919
1920 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
1921 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
1922 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
1923 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
1924 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
1925 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
1926 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
1927
1928
1929
1930
1931
1932 linkattr = 0;
1933 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
1934 linkattr |= FW_PORT_CAP32_FC_RX;
1935 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
1936 linkattr |= FW_PORT_CAP32_FC_TX;
1937 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
1938 linkattr |= FW_PORT_CAP32_SPEED_100M;
1939 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
1940 linkattr |= FW_PORT_CAP32_SPEED_1G;
1941 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
1942 linkattr |= FW_PORT_CAP32_SPEED_10G;
1943 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
1944 linkattr |= FW_PORT_CAP32_SPEED_25G;
1945 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
1946 linkattr |= FW_PORT_CAP32_SPEED_40G;
1947 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
1948 linkattr |= FW_PORT_CAP32_SPEED_100G;
1949
1950 break;
1951 }
1952
1953 case FW_PORT_ACTION_GET_PORT_INFO32: {
1954 u32 lstatus32;
1955
1956 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
1957 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
1958 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
1959 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
1960 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
1961 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
1962 acaps = be32_to_cpu(cmd->u.info32.acaps32);
1963 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
1964 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
1965 break;
1966 }
1967
1968 default:
1969 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
1970 be32_to_cpu(cmd->action_to_len16));
1971 return;
1972 }
1973
1974 fec = fwcap_to_cc_fec(acaps);
1975 fc = fwcap_to_cc_pause(linkattr);
1976 speed = fwcap_to_speed(linkattr);
1977
1978 if (mod_type != pi->mod_type) {
1979
1980
1981
1982
1983
1984
1985
1986 lc->auto_fec = fec;
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998 pi->port_type = port_type;
1999
2000 pi->mod_type = mod_type;
2001 t4vf_os_portmod_changed(adapter, pi->pidx);
2002 }
2003
2004 if (link_ok != lc->link_ok || speed != lc->speed ||
2005 fc != lc->fc || fec != lc->fec) {
2006 if (!link_ok && lc->link_ok) {
2007 lc->link_down_rc = linkdnrc;
2008 dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
2009 pi->port_id, t4vf_link_down_rc_str(linkdnrc));
2010 }
2011 lc->link_ok = link_ok;
2012 lc->speed = speed;
2013 lc->fc = fc;
2014 lc->fec = fec;
2015
2016 lc->pcaps = pcaps;
2017 lc->lpacaps = lpacaps;
2018 lc->acaps = acaps & ADVERT_MASK;
2019
2020
2021
2022
2023
2024
2025 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
2026 lc->autoneg = AUTONEG_DISABLE;
2027 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
2028 lc->autoneg = AUTONEG_ENABLE;
2029 } else {
2030
2031
2032
2033
2034 lc->acaps = 0;
2035 lc->speed_caps = fwcap_to_speed(acaps);
2036 lc->autoneg = AUTONEG_DISABLE;
2037 }
2038
2039 t4vf_os_link_changed(adapter, pi->pidx, link_ok);
2040 }
2041}
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051int t4vf_update_port_info(struct port_info *pi)
2052{
2053 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
2054 struct fw_port_cmd port_cmd;
2055 int ret;
2056
2057 memset(&port_cmd, 0, sizeof(port_cmd));
2058 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
2059 FW_CMD_REQUEST_F | FW_CMD_READ_F |
2060 FW_PORT_CMD_PORTID_V(pi->port_id));
2061 port_cmd.action_to_len16 = cpu_to_be32(
2062 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
2063 ? FW_PORT_ACTION_GET_PORT_INFO
2064 : FW_PORT_ACTION_GET_PORT_INFO32) |
2065 FW_LEN16(port_cmd));
2066 ret = t4vf_wr_mbox(pi->adapter, &port_cmd, sizeof(port_cmd),
2067 &port_cmd);
2068 if (ret)
2069 return ret;
2070 t4vf_handle_get_port_info(pi, &port_cmd);
2071 return 0;
2072}
2073
2074
2075
2076
2077
2078
2079
2080
2081int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
2082{
2083 const struct fw_cmd_hdr *cmd_hdr = (const struct fw_cmd_hdr *)rpl;
2084 u8 opcode = FW_CMD_OP_G(be32_to_cpu(cmd_hdr->hi));
2085
2086 switch (opcode) {
2087 case FW_PORT_CMD: {
2088
2089
2090
2091 const struct fw_port_cmd *port_cmd =
2092 (const struct fw_port_cmd *)rpl;
2093 int action = FW_PORT_CMD_ACTION_G(
2094 be32_to_cpu(port_cmd->action_to_len16));
2095 int port_id, pidx;
2096
2097 if (action != FW_PORT_ACTION_GET_PORT_INFO &&
2098 action != FW_PORT_ACTION_GET_PORT_INFO32) {
2099 dev_err(adapter->pdev_dev,
2100 "Unknown firmware PORT reply action %x\n",
2101 action);
2102 break;
2103 }
2104
2105 port_id = FW_PORT_CMD_PORTID_G(
2106 be32_to_cpu(port_cmd->op_to_portid));
2107 for_each_port(adapter, pidx) {
2108 struct port_info *pi = adap2pinfo(adapter, pidx);
2109
2110 if (pi->port_id != port_id)
2111 continue;
2112 t4vf_handle_get_port_info(pi, port_cmd);
2113 }
2114 break;
2115 }
2116
2117 default:
2118 dev_err(adapter->pdev_dev, "Unknown firmware reply %X\n",
2119 opcode);
2120 }
2121 return 0;
2122}
2123
2124
2125
2126int t4vf_prep_adapter(struct adapter *adapter)
2127{
2128 int err;
2129 unsigned int chipid;
2130
2131
2132
2133 err = t4vf_wait_dev_ready(adapter);
2134 if (err)
2135 return err;
2136
2137
2138
2139
2140 adapter->params.nports = 1;
2141 adapter->params.vfres.pmask = 1;
2142 adapter->params.vpd.cclk = 50000;
2143
2144 adapter->params.chip = 0;
2145 switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) {
2146 case CHELSIO_T4:
2147 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
2148 adapter->params.arch.sge_fl_db = DBPRIO_F;
2149 adapter->params.arch.mps_tcam_size =
2150 NUM_MPS_CLS_SRAM_L_INSTANCES;
2151 break;
2152
2153 case CHELSIO_T5:
2154 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
2155 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
2156 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
2157 adapter->params.arch.mps_tcam_size =
2158 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
2159 break;
2160
2161 case CHELSIO_T6:
2162 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
2163 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, chipid);
2164 adapter->params.arch.sge_fl_db = 0;
2165 adapter->params.arch.mps_tcam_size =
2166 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
2167 break;
2168 }
2169
2170 return 0;
2171}
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184int t4vf_get_vf_mac_acl(struct adapter *adapter, unsigned int pf,
2185 unsigned int *naddr, u8 *addr)
2186{
2187 struct fw_acl_mac_cmd cmd;
2188 int ret;
2189
2190 memset(&cmd, 0, sizeof(cmd));
2191 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
2192 FW_CMD_REQUEST_F |
2193 FW_CMD_READ_F);
2194 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
2195 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &cmd);
2196 if (ret)
2197 return ret;
2198
2199 if (cmd.nmac < *naddr)
2200 *naddr = cmd.nmac;
2201
2202 switch (pf) {
2203 case 3:
2204 memcpy(addr, cmd.macaddr3, sizeof(cmd.macaddr3));
2205 break;
2206 case 2:
2207 memcpy(addr, cmd.macaddr2, sizeof(cmd.macaddr2));
2208 break;
2209 case 1:
2210 memcpy(addr, cmd.macaddr1, sizeof(cmd.macaddr1));
2211 break;
2212 case 0:
2213 memcpy(addr, cmd.macaddr0, sizeof(cmd.macaddr0));
2214 break;
2215 }
2216
2217 return ret;
2218}
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228int t4vf_get_vf_vlan_acl(struct adapter *adapter)
2229{
2230 struct fw_acl_vlan_cmd cmd;
2231 int vlan = 0;
2232 int ret = 0;
2233
2234 cmd.op_to_vfn = htonl(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
2235 FW_CMD_REQUEST_F | FW_CMD_READ_F);
2236
2237
2238 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
2239
2240 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &cmd);
2241
2242 if (!ret)
2243 vlan = be16_to_cpu(cmd.vlanid[0]);
2244
2245 return vlan;
2246}
2247