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16#ifndef HINIC_HW_WQE_H
17#define HINIC_HW_WQE_H
18
19#include "hinic_common.h"
20
21#define HINIC_CMDQ_CTRL_PI_SHIFT 0
22#define HINIC_CMDQ_CTRL_CMD_SHIFT 16
23#define HINIC_CMDQ_CTRL_MOD_SHIFT 24
24#define HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT 29
25#define HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT 31
26
27#define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF
28#define HINIC_CMDQ_CTRL_CMD_MASK 0xFF
29#define HINIC_CMDQ_CTRL_MOD_MASK 0x1F
30#define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3
31#define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1
32
33#define HINIC_CMDQ_CTRL_SET(val, member) \
34 (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \
35 << HINIC_CMDQ_CTRL_##member##_SHIFT)
36
37#define HINIC_CMDQ_CTRL_GET(val, member) \
38 (((val) >> HINIC_CMDQ_CTRL_##member##_SHIFT) \
39 & HINIC_CMDQ_CTRL_##member##_MASK)
40
41#define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0
42#define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT 15
43#define HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT 22
44#define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT 23
45#define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT 27
46#define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT 29
47#define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT 31
48
49#define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF
50#define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1
51#define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1
52#define HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK 0x1
53#define HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK 0x3
54#define HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK 0x3
55#define HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK 0x1
56
57#define HINIC_CMDQ_WQE_HEADER_SET(val, member) \
58 (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \
59 << HINIC_CMDQ_WQE_HEADER_##member##_SHIFT)
60
61#define HINIC_CMDQ_WQE_HEADER_GET(val, member) \
62 (((val) >> HINIC_CMDQ_WQE_HEADER_##member##_SHIFT) \
63 & HINIC_CMDQ_WQE_HEADER_##member##_MASK)
64
65#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
66#define HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT 16
67#define HINIC_SQ_CTRL_DATA_FORMAT_SHIFT 22
68#define HINIC_SQ_CTRL_LEN_SHIFT 29
69
70#define HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
71#define HINIC_SQ_CTRL_TASKSECT_LEN_MASK 0x1F
72#define HINIC_SQ_CTRL_DATA_FORMAT_MASK 0x1
73#define HINIC_SQ_CTRL_LEN_MASK 0x3
74
75#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13
76
77#define HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFF
78
79#define HINIC_SQ_CTRL_SET(val, member) \
80 (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \
81 << HINIC_SQ_CTRL_##member##_SHIFT)
82
83#define HINIC_SQ_CTRL_GET(val, member) \
84 (((val) >> HINIC_SQ_CTRL_##member##_SHIFT) \
85 & HINIC_SQ_CTRL_##member##_MASK)
86
87#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0
88#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT 8
89#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10
90#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12
91#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13
92
93#define HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT 15
94#define HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT 16
95
96#define HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFF
97#define HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK 0x3
98#define HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3
99#define HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1
100#define HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1
101
102#define HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK 0x1
103#define HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFF
104
105#define HINIC_SQ_TASK_INFO0_SET(val, member) \
106 (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \
107 HINIC_SQ_TASK_INFO0_##member##_SHIFT)
108
109
110#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT 8
111#define HINIC_SQ_TASK_INFO1_INNER_L4_LEN_SHIFT 16
112#define HINIC_SQ_TASK_INFO1_INNER_L3_LEN_SHIFT 24
113
114
115#define HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK 0xFF
116#define HINIC_SQ_TASK_INFO1_INNER_L4_LEN_MASK 0xFF
117#define HINIC_SQ_TASK_INFO1_INNER_L3_LEN_MASK 0xFF
118
119#define HINIC_SQ_TASK_INFO1_SET(val, member) \
120 (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \
121 HINIC_SQ_TASK_INFO1_##member##_SHIFT)
122
123#define HINIC_SQ_TASK_INFO2_TUNNEL_L4_LEN_SHIFT 0
124#define HINIC_SQ_TASK_INFO2_OUTER_L3_LEN_SHIFT 12
125#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 19
126
127#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 22
128
129
130#define HINIC_SQ_TASK_INFO2_TUNNEL_L4_LEN_MASK 0xFFF
131#define HINIC_SQ_TASK_INFO2_OUTER_L3_LEN_MASK 0x7F
132#define HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x3
133
134#define HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3
135
136
137#define HINIC_SQ_TASK_INFO2_SET(val, member) \
138 (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \
139 HINIC_SQ_TASK_INFO2_##member##_SHIFT)
140
141
142#define HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT 31
143
144
145#define HINIC_SQ_TASK_INFO4_L2TYPE_MASK 0x1
146
147#define HINIC_SQ_TASK_INFO4_SET(val, member) \
148 (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \
149 HINIC_SQ_TASK_INFO4_##member##_SHIFT)
150
151#define HINIC_RQ_CQE_STATUS_RXDONE_SHIFT 31
152
153#define HINIC_RQ_CQE_STATUS_RXDONE_MASK 0x1
154
155#define HINIC_RQ_CQE_STATUS_GET(val, member) \
156 (((val) >> HINIC_RQ_CQE_STATUS_##member##_SHIFT) & \
157 HINIC_RQ_CQE_STATUS_##member##_MASK)
158
159#define HINIC_RQ_CQE_STATUS_CLEAR(val, member) \
160 ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \
161 HINIC_RQ_CQE_STATUS_##member##_SHIFT)))
162
163#define HINIC_RQ_CQE_SGE_LEN_SHIFT 16
164
165#define HINIC_RQ_CQE_SGE_LEN_MASK 0xFFFF
166
167#define HINIC_RQ_CQE_SGE_GET(val, member) \
168 (((val) >> HINIC_RQ_CQE_SGE_##member##_SHIFT) & \
169 HINIC_RQ_CQE_SGE_##member##_MASK)
170
171#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
172#define HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT 15
173#define HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT 27
174#define HINIC_RQ_CTRL_LEN_SHIFT 29
175
176#define HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFF
177#define HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK 0x1
178#define HINIC_RQ_CTRL_COMPLETE_LEN_MASK 0x3
179#define HINIC_RQ_CTRL_LEN_MASK 0x3
180
181#define HINIC_RQ_CTRL_SET(val, member) \
182 (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \
183 HINIC_RQ_CTRL_##member##_SHIFT)
184
185#define HINIC_SQ_WQE_SIZE(nr_sges) \
186 (sizeof(struct hinic_sq_ctrl) + \
187 sizeof(struct hinic_sq_task) + \
188 (nr_sges) * sizeof(struct hinic_sq_bufdesc))
189
190#define HINIC_SCMD_DATA_LEN 16
191
192#define HINIC_MAX_SQ_BUFDESCS 17
193
194#define HINIC_SQ_WQE_MAX_SIZE 320
195#define HINIC_RQ_WQE_SIZE 32
196
197enum hinic_l4offload_type {
198 HINIC_L4_OFF_DISABLE = 0,
199 HINIC_TCP_OFFLOAD_ENABLE = 1,
200 HINIC_SCTP_OFFLOAD_ENABLE = 2,
201 HINIC_UDP_OFFLOAD_ENABLE = 3,
202};
203
204enum hinic_vlan_offload {
205 HINIC_VLAN_OFF_DISABLE = 0,
206 HINIC_VLAN_OFF_ENABLE = 1,
207};
208
209enum hinic_pkt_parsed {
210 HINIC_PKT_NOT_PARSED = 0,
211 HINIC_PKT_PARSED = 1,
212};
213
214enum hinic_outer_l3type {
215 HINIC_OUTER_L3TYPE_UNKNOWN = 0,
216 HINIC_OUTER_L3TYPE_IPV6 = 1,
217 HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM = 2,
218 HINIC_OUTER_L3TYPE_IPV4_CHKSUM = 3,
219};
220
221enum hinic_media_type {
222 HINIC_MEDIA_UNKNOWN = 0,
223};
224
225enum hinic_l2type {
226 HINIC_L2TYPE_ETH = 0,
227};
228
229enum hinc_tunnel_l4type {
230 HINIC_TUNNEL_L4TYPE_UNKNOWN = 0,
231};
232
233struct hinic_cmdq_header {
234 u32 header_info;
235 u32 saved_data;
236};
237
238struct hinic_status {
239 u32 status_info;
240};
241
242struct hinic_ctrl {
243 u32 ctrl_info;
244};
245
246struct hinic_sge_resp {
247 struct hinic_sge sge;
248 u32 rsvd;
249};
250
251struct hinic_cmdq_completion {
252
253 union {
254 struct hinic_sge_resp sge_resp;
255 u64 direct_resp;
256 };
257};
258
259struct hinic_scmd_bufdesc {
260 u32 buf_len;
261 u32 rsvd;
262 u8 data[HINIC_SCMD_DATA_LEN];
263};
264
265struct hinic_lcmd_bufdesc {
266 struct hinic_sge sge;
267 u32 rsvd1;
268 u64 rsvd2;
269 u64 rsvd3;
270};
271
272struct hinic_cmdq_wqe_scmd {
273 struct hinic_cmdq_header header;
274 u64 rsvd;
275 struct hinic_status status;
276 struct hinic_ctrl ctrl;
277 struct hinic_cmdq_completion completion;
278 struct hinic_scmd_bufdesc buf_desc;
279};
280
281struct hinic_cmdq_wqe_lcmd {
282 struct hinic_cmdq_header header;
283 struct hinic_status status;
284 struct hinic_ctrl ctrl;
285 struct hinic_cmdq_completion completion;
286 struct hinic_lcmd_bufdesc buf_desc;
287};
288
289struct hinic_cmdq_direct_wqe {
290 struct hinic_cmdq_wqe_scmd wqe_scmd;
291};
292
293struct hinic_cmdq_wqe {
294
295 union {
296 struct hinic_cmdq_direct_wqe direct_wqe;
297 struct hinic_cmdq_wqe_lcmd wqe_lcmd;
298 };
299};
300
301struct hinic_sq_ctrl {
302 u32 ctrl_info;
303 u32 queue_info;
304};
305
306struct hinic_sq_task {
307 u32 pkt_info0;
308 u32 pkt_info1;
309 u32 pkt_info2;
310 u32 ufo_v6_identify;
311 u32 pkt_info4;
312 u32 zero_pad;
313};
314
315struct hinic_sq_bufdesc {
316 struct hinic_sge sge;
317 u32 rsvd;
318};
319
320struct hinic_sq_wqe {
321 struct hinic_sq_ctrl ctrl;
322 struct hinic_sq_task task;
323 struct hinic_sq_bufdesc buf_descs[HINIC_MAX_SQ_BUFDESCS];
324};
325
326struct hinic_rq_cqe {
327 u32 status;
328 u32 len;
329
330 u32 rsvd2;
331 u32 rsvd3;
332 u32 rsvd4;
333 u32 rsvd5;
334 u32 rsvd6;
335 u32 rsvd7;
336};
337
338struct hinic_rq_ctrl {
339 u32 ctrl_info;
340};
341
342struct hinic_rq_cqe_sect {
343 struct hinic_sge sge;
344 u32 rsvd;
345};
346
347struct hinic_rq_bufdesc {
348 u32 hi_addr;
349 u32 lo_addr;
350};
351
352struct hinic_rq_wqe {
353 struct hinic_rq_ctrl ctrl;
354 u32 rsvd;
355 struct hinic_rq_cqe_sect cqe_sect;
356 struct hinic_rq_bufdesc buf_desc;
357};
358
359struct hinic_hw_wqe {
360
361 union {
362 struct hinic_cmdq_wqe cmdq_wqe;
363 struct hinic_sq_wqe sq_wqe;
364 struct hinic_rq_wqe rq_wqe;
365 };
366};
367
368#endif
369
