LXR linux/drivers/net/ethernet/intel/i40evf/i40e_adminq

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4#ifndef _I40E_ADMINQ_CMD_H_
   5#define _I40E_ADMINQ_CMD_H_
   6
   7/* This header file defines the i40e Admin Queue commands and is shared between
   8 * i40e Firmware and Software.
   9 *
  10 * This file needs to comply with the Linux Kernel coding style.
  11 */
  12
  13#define I40E_FW_API_VERSION_MAJOR       0x0001
  14#define I40E_FW_API_VERSION_MINOR_X722  0x0005
  15#define I40E_FW_API_VERSION_MINOR_X710  0x0007
  16
  17#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
  18                                        I40E_FW_API_VERSION_MINOR_X710 : \
  19                                        I40E_FW_API_VERSION_MINOR_X722)
  20
  21/* API version 1.7 implements additional link and PHY-specific APIs  */
  22#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
  23
  24struct i40e_aq_desc {
  25        __le16 flags;
  26        __le16 opcode;
  27        __le16 datalen;
  28        __le16 retval;
  29        __le32 cookie_high;
  30        __le32 cookie_low;
  31        union {
  32                struct {
  33                        __le32 param0;
  34                        __le32 param1;
  35                        __le32 param2;
  36                        __le32 param3;
  37                } internal;
  38                struct {
  39                        __le32 param0;
  40                        __le32 param1;
  41                        __le32 addr_high;
  42                        __le32 addr_low;
  43                } external;
  44                u8 raw[16];
  45        } params;
  46};
  47
  48/* Flags sub-structure
  49 * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  50 * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  51 */
  52
  53/* command flags and offsets*/
  54#define I40E_AQ_FLAG_DD_SHIFT   0
  55#define I40E_AQ_FLAG_CMP_SHIFT  1
  56#define I40E_AQ_FLAG_ERR_SHIFT  2
  57#define I40E_AQ_FLAG_VFE_SHIFT  3
  58#define I40E_AQ_FLAG_LB_SHIFT   9
  59#define I40E_AQ_FLAG_RD_SHIFT   10
  60#define I40E_AQ_FLAG_VFC_SHIFT  11
  61#define I40E_AQ_FLAG_BUF_SHIFT  12
  62#define I40E_AQ_FLAG_SI_SHIFT   13
  63#define I40E_AQ_FLAG_EI_SHIFT   14
  64#define I40E_AQ_FLAG_FE_SHIFT   15
  65
  66#define I40E_AQ_FLAG_DD         BIT(I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  67#define I40E_AQ_FLAG_CMP        BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  68#define I40E_AQ_FLAG_ERR        BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
  69#define I40E_AQ_FLAG_VFE        BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
  70#define I40E_AQ_FLAG_LB         BIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
  71#define I40E_AQ_FLAG_RD         BIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
  72#define I40E_AQ_FLAG_VFC        BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
  73#define I40E_AQ_FLAG_BUF        BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  74#define I40E_AQ_FLAG_SI         BIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
  75#define I40E_AQ_FLAG_EI         BIT(I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
  76#define I40E_AQ_FLAG_FE         BIT(I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
  77
  78/* error codes */
  79enum i40e_admin_queue_err {
  80        I40E_AQ_RC_OK           = 0,  /* success */
  81        I40E_AQ_RC_EPERM        = 1,  /* Operation not permitted */
  82        I40E_AQ_RC_ENOENT       = 2,  /* No such element */
  83        I40E_AQ_RC_ESRCH        = 3,  /* Bad opcode */
  84        I40E_AQ_RC_EINTR        = 4,  /* operation interrupted */
  85        I40E_AQ_RC_EIO          = 5,  /* I/O error */
  86        I40E_AQ_RC_ENXIO        = 6,  /* No such resource */
  87        I40E_AQ_RC_E2BIG        = 7,  /* Arg too long */
  88        I40E_AQ_RC_EAGAIN       = 8,  /* Try again */
  89        I40E_AQ_RC_ENOMEM       = 9,  /* Out of memory */
  90        I40E_AQ_RC_EACCES       = 10, /* Permission denied */
  91        I40E_AQ_RC_EFAULT       = 11, /* Bad address */
  92        I40E_AQ_RC_EBUSY        = 12, /* Device or resource busy */
  93        I40E_AQ_RC_EEXIST       = 13, /* object already exists */
  94        I40E_AQ_RC_EINVAL       = 14, /* Invalid argument */
  95        I40E_AQ_RC_ENOTTY       = 15, /* Not a typewriter */
  96        I40E_AQ_RC_ENOSPC       = 16, /* No space left or alloc failure */
  97        I40E_AQ_RC_ENOSYS       = 17, /* Function not implemented */
  98        I40E_AQ_RC_ERANGE       = 18, /* Parameter out of range */
  99        I40E_AQ_RC_EFLUSHED     = 19, /* Cmd flushed due to prev cmd error */
 100        I40E_AQ_RC_BAD_ADDR     = 20, /* Descriptor contains a bad pointer */
 101        I40E_AQ_RC_EMODE        = 21, /* Op not allowed in current dev mode */
 102        I40E_AQ_RC_EFBIG        = 22, /* File too large */
 103};
 104
 105/* Admin Queue command opcodes */
 106enum i40e_admin_queue_opc {
 107        /* aq commands */
 108        i40e_aqc_opc_get_version        = 0x0001,
 109        i40e_aqc_opc_driver_version     = 0x0002,
 110        i40e_aqc_opc_queue_shutdown     = 0x0003,
 111        i40e_aqc_opc_set_pf_context     = 0x0004,
 112
 113        /* resource ownership */
 114        i40e_aqc_opc_request_resource   = 0x0008,
 115        i40e_aqc_opc_release_resource   = 0x0009,
 116
 117        i40e_aqc_opc_list_func_capabilities     = 0x000A,
 118        i40e_aqc_opc_list_dev_capabilities      = 0x000B,
 119
 120        /* Proxy commands */
 121        i40e_aqc_opc_set_proxy_config           = 0x0104,
 122        i40e_aqc_opc_set_ns_proxy_table_entry   = 0x0105,
 123
 124        /* LAA */
 125        i40e_aqc_opc_mac_address_read   = 0x0107,
 126        i40e_aqc_opc_mac_address_write  = 0x0108,
 127
 128        /* PXE */
 129        i40e_aqc_opc_clear_pxe_mode     = 0x0110,
 130
 131        /* WoL commands */
 132        i40e_aqc_opc_set_wol_filter     = 0x0120,
 133        i40e_aqc_opc_get_wake_reason    = 0x0121,
 134
 135        /* internal switch commands */
 136        i40e_aqc_opc_get_switch_config          = 0x0200,
 137        i40e_aqc_opc_add_statistics             = 0x0201,
 138        i40e_aqc_opc_remove_statistics          = 0x0202,
 139        i40e_aqc_opc_set_port_parameters        = 0x0203,
 140        i40e_aqc_opc_get_switch_resource_alloc  = 0x0204,
 141        i40e_aqc_opc_set_switch_config          = 0x0205,
 142        i40e_aqc_opc_rx_ctl_reg_read            = 0x0206,
 143        i40e_aqc_opc_rx_ctl_reg_write           = 0x0207,
 144
 145        i40e_aqc_opc_add_vsi                    = 0x0210,
 146        i40e_aqc_opc_update_vsi_parameters      = 0x0211,
 147        i40e_aqc_opc_get_vsi_parameters         = 0x0212,
 148
 149        i40e_aqc_opc_add_pv                     = 0x0220,
 150        i40e_aqc_opc_update_pv_parameters       = 0x0221,
 151        i40e_aqc_opc_get_pv_parameters          = 0x0222,
 152
 153        i40e_aqc_opc_add_veb                    = 0x0230,
 154        i40e_aqc_opc_update_veb_parameters      = 0x0231,
 155        i40e_aqc_opc_get_veb_parameters         = 0x0232,
 156
 157        i40e_aqc_opc_delete_element             = 0x0243,
 158
 159        i40e_aqc_opc_add_macvlan                = 0x0250,
 160        i40e_aqc_opc_remove_macvlan             = 0x0251,
 161        i40e_aqc_opc_add_vlan                   = 0x0252,
 162        i40e_aqc_opc_remove_vlan                = 0x0253,
 163        i40e_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
 164        i40e_aqc_opc_add_tag                    = 0x0255,
 165        i40e_aqc_opc_remove_tag                 = 0x0256,
 166        i40e_aqc_opc_add_multicast_etag         = 0x0257,
 167        i40e_aqc_opc_remove_multicast_etag      = 0x0258,
 168        i40e_aqc_opc_update_tag                 = 0x0259,
 169        i40e_aqc_opc_add_control_packet_filter  = 0x025A,
 170        i40e_aqc_opc_remove_control_packet_filter       = 0x025B,
 171        i40e_aqc_opc_add_cloud_filters          = 0x025C,
 172        i40e_aqc_opc_remove_cloud_filters       = 0x025D,
 173        i40e_aqc_opc_clear_wol_switch_filters   = 0x025E,
 174
 175        i40e_aqc_opc_add_mirror_rule    = 0x0260,
 176        i40e_aqc_opc_delete_mirror_rule = 0x0261,
 177
 178        /* Dynamic Device Personalization */
 179        i40e_aqc_opc_write_personalization_profile      = 0x0270,
 180        i40e_aqc_opc_get_personalization_profile_list   = 0x0271,
 181
 182        /* DCB commands */
 183        i40e_aqc_opc_dcb_ignore_pfc     = 0x0301,
 184        i40e_aqc_opc_dcb_updated        = 0x0302,
 185        i40e_aqc_opc_set_dcb_parameters = 0x0303,
 186
 187        /* TX scheduler */
 188        i40e_aqc_opc_configure_vsi_bw_limit             = 0x0400,
 189        i40e_aqc_opc_configure_vsi_ets_sla_bw_limit     = 0x0406,
 190        i40e_aqc_opc_configure_vsi_tc_bw                = 0x0407,
 191        i40e_aqc_opc_query_vsi_bw_config                = 0x0408,
 192        i40e_aqc_opc_query_vsi_ets_sla_config           = 0x040A,
 193        i40e_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
 194
 195        i40e_aqc_opc_enable_switching_comp_ets                  = 0x0413,
 196        i40e_aqc_opc_modify_switching_comp_ets                  = 0x0414,
 197        i40e_aqc_opc_disable_switching_comp_ets                 = 0x0415,
 198        i40e_aqc_opc_configure_switching_comp_ets_bw_limit      = 0x0416,
 199        i40e_aqc_opc_configure_switching_comp_bw_config         = 0x0417,
 200        i40e_aqc_opc_query_switching_comp_ets_config            = 0x0418,
 201        i40e_aqc_opc_query_port_ets_config                      = 0x0419,
 202        i40e_aqc_opc_query_switching_comp_bw_config             = 0x041A,
 203        i40e_aqc_opc_suspend_port_tx                            = 0x041B,
 204        i40e_aqc_opc_resume_port_tx                             = 0x041C,
 205        i40e_aqc_opc_configure_partition_bw                     = 0x041D,
 206        /* hmc */
 207        i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
 208        i40e_aqc_opc_set_hmc_resource_profile   = 0x0501,
 209
 210        /* phy commands*/
 211        i40e_aqc_opc_get_phy_abilities          = 0x0600,
 212        i40e_aqc_opc_set_phy_config             = 0x0601,
 213        i40e_aqc_opc_set_mac_config             = 0x0603,
 214        i40e_aqc_opc_set_link_restart_an        = 0x0605,
 215        i40e_aqc_opc_get_link_status            = 0x0607,
 216        i40e_aqc_opc_set_phy_int_mask           = 0x0613,
 217        i40e_aqc_opc_get_local_advt_reg         = 0x0614,
 218        i40e_aqc_opc_set_local_advt_reg         = 0x0615,
 219        i40e_aqc_opc_get_partner_advt           = 0x0616,
 220        i40e_aqc_opc_set_lb_modes               = 0x0618,
 221        i40e_aqc_opc_get_phy_wol_caps           = 0x0621,
 222        i40e_aqc_opc_set_phy_debug              = 0x0622,
 223        i40e_aqc_opc_upload_ext_phy_fm          = 0x0625,
 224        i40e_aqc_opc_run_phy_activity           = 0x0626,
 225        i40e_aqc_opc_set_phy_register           = 0x0628,
 226        i40e_aqc_opc_get_phy_register           = 0x0629,
 227
 228        /* NVM commands */
 229        i40e_aqc_opc_nvm_read                   = 0x0701,
 230        i40e_aqc_opc_nvm_erase                  = 0x0702,
 231        i40e_aqc_opc_nvm_update                 = 0x0703,
 232        i40e_aqc_opc_nvm_config_read            = 0x0704,
 233        i40e_aqc_opc_nvm_config_write           = 0x0705,
 234        i40e_aqc_opc_oem_post_update            = 0x0720,
 235        i40e_aqc_opc_thermal_sensor             = 0x0721,
 236
 237        /* virtualization commands */
 238        i40e_aqc_opc_send_msg_to_pf             = 0x0801,
 239        i40e_aqc_opc_send_msg_to_vf             = 0x0802,
 240        i40e_aqc_opc_send_msg_to_peer           = 0x0803,
 241
 242        /* alternate structure */
 243        i40e_aqc_opc_alternate_write            = 0x0900,
 244        i40e_aqc_opc_alternate_write_indirect   = 0x0901,
 245        i40e_aqc_opc_alternate_read             = 0x0902,
 246        i40e_aqc_opc_alternate_read_indirect    = 0x0903,
 247        i40e_aqc_opc_alternate_write_done       = 0x0904,
 248        i40e_aqc_opc_alternate_set_mode         = 0x0905,
 249        i40e_aqc_opc_alternate_clear_port       = 0x0906,
 250
 251        /* LLDP commands */
 252        i40e_aqc_opc_lldp_get_mib       = 0x0A00,
 253        i40e_aqc_opc_lldp_update_mib    = 0x0A01,
 254        i40e_aqc_opc_lldp_add_tlv       = 0x0A02,
 255        i40e_aqc_opc_lldp_update_tlv    = 0x0A03,
 256        i40e_aqc_opc_lldp_delete_tlv    = 0x0A04,
 257        i40e_aqc_opc_lldp_stop          = 0x0A05,
 258        i40e_aqc_opc_lldp_start         = 0x0A06,
 259
 260        /* Tunnel commands */
 261        i40e_aqc_opc_add_udp_tunnel     = 0x0B00,
 262        i40e_aqc_opc_del_udp_tunnel     = 0x0B01,
 263        i40e_aqc_opc_set_rss_key        = 0x0B02,
 264        i40e_aqc_opc_set_rss_lut        = 0x0B03,
 265        i40e_aqc_opc_get_rss_key        = 0x0B04,
 266        i40e_aqc_opc_get_rss_lut        = 0x0B05,
 267
 268        /* Async Events */
 269        i40e_aqc_opc_event_lan_overflow         = 0x1001,
 270
 271        /* OEM commands */
 272        i40e_aqc_opc_oem_parameter_change       = 0xFE00,
 273        i40e_aqc_opc_oem_device_status_change   = 0xFE01,
 274        i40e_aqc_opc_oem_ocsd_initialize        = 0xFE02,
 275        i40e_aqc_opc_oem_ocbb_initialize        = 0xFE03,
 276
 277        /* debug commands */
 278        i40e_aqc_opc_debug_read_reg             = 0xFF03,
 279        i40e_aqc_opc_debug_write_reg            = 0xFF04,
 280        i40e_aqc_opc_debug_modify_reg           = 0xFF07,
 281        i40e_aqc_opc_debug_dump_internals       = 0xFF08,
 282};
 283
 284/* command structures and indirect data structures */
 285
 286/* Structure naming conventions:
 287 * - no suffix for direct command descriptor structures
 288 * - _data for indirect sent data
 289 * - _resp for indirect return data (data which is both will use _data)
 290 * - _completion for direct return data
 291 * - _element_ for repeated elements (may also be _data or _resp)
 292 *
 293 * Command structures are expected to overlay the params.raw member of the basic
 294 * descriptor, and as such cannot exceed 16 bytes in length.
 295 */
 296
 297/* This macro is used to generate a compilation error if a structure
 298 * is not exactly the correct length. It gives a divide by zero error if the
 299 * structure is not of the correct size, otherwise it creates an enum that is
 300 * never used.
 301 */
 302#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
 303        { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 304
 305/* This macro is used extensively to ensure that command structures are 16
 306 * bytes in length as they have to map to the raw array of that size.
 307 */
 308#define I40E_CHECK_CMD_LENGTH(X)        I40E_CHECK_STRUCT_LEN(16, X)
 309
 310/* internal (0x00XX) commands */
 311
 312/* Get version (direct 0x0001) */
 313struct i40e_aqc_get_version {
 314        __le32 rom_ver;
 315        __le32 fw_build;
 316        __le16 fw_major;
 317        __le16 fw_minor;
 318        __le16 api_major;
 319        __le16 api_minor;
 320};
 321
 322I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
 323
 324/* Send driver version (indirect 0x0002) */
 325struct i40e_aqc_driver_version {
 326        u8      driver_major_ver;
 327        u8      driver_minor_ver;
 328        u8      driver_build_ver;
 329        u8      driver_subbuild_ver;
 330        u8      reserved[4];
 331        __le32  address_high;
 332        __le32  address_low;
 333};
 334
 335I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
 336
 337/* Queue Shutdown (direct 0x0003) */
 338struct i40e_aqc_queue_shutdown {
 339        __le32  driver_unloading;
 340#define I40E_AQ_DRIVER_UNLOADING        0x1
 341        u8      reserved[12];
 342};
 343
 344I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
 345
 346/* Set PF context (0x0004, direct) */
 347struct i40e_aqc_set_pf_context {
 348        u8      pf_id;
 349        u8      reserved[15];
 350};
 351
 352I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
 353
 354/* Request resource ownership (direct 0x0008)
 355 * Release resource ownership (direct 0x0009)
 356 */
 357#define I40E_AQ_RESOURCE_NVM                    1
 358#define I40E_AQ_RESOURCE_SDP                    2
 359#define I40E_AQ_RESOURCE_ACCESS_READ            1
 360#define I40E_AQ_RESOURCE_ACCESS_WRITE           2
 361#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT       3000
 362#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT      180000
 363
 364struct i40e_aqc_request_resource {
 365        __le16  resource_id;
 366        __le16  access_type;
 367        __le32  timeout;
 368        __le32  resource_number;
 369        u8      reserved[4];
 370};
 371
 372I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
 373
 374/* Get function capabilities (indirect 0x000A)
 375 * Get device capabilities (indirect 0x000B)
 376 */
 377struct i40e_aqc_list_capabilites {
 378        u8 command_flags;
 379#define I40E_AQ_LIST_CAP_PF_INDEX_EN    1
 380        u8 pf_index;
 381        u8 reserved[2];
 382        __le32 count;
 383        __le32 addr_high;
 384        __le32 addr_low;
 385};
 386
 387I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
 388
 389struct i40e_aqc_list_capabilities_element_resp {
 390        __le16  id;
 391        u8      major_rev;
 392        u8      minor_rev;
 393        __le32  number;
 394        __le32  logical_id;
 395        __le32  phys_id;
 396        u8      reserved[16];
 397};
 398
 399/* list of caps */
 400
 401#define I40E_AQ_CAP_ID_SWITCH_MODE      0x0001
 402#define I40E_AQ_CAP_ID_MNG_MODE         0x0002
 403#define I40E_AQ_CAP_ID_NPAR_ACTIVE      0x0003
 404#define I40E_AQ_CAP_ID_OS2BMC_CAP       0x0004
 405#define I40E_AQ_CAP_ID_FUNCTIONS_VALID  0x0005
 406#define I40E_AQ_CAP_ID_ALTERNATE_RAM    0x0006
 407#define I40E_AQ_CAP_ID_WOL_AND_PROXY    0x0008
 408#define I40E_AQ_CAP_ID_SRIOV            0x0012
 409#define I40E_AQ_CAP_ID_VF               0x0013
 410#define I40E_AQ_CAP_ID_VMDQ             0x0014
 411#define I40E_AQ_CAP_ID_8021QBG          0x0015
 412#define I40E_AQ_CAP_ID_8021QBR          0x0016
 413#define I40E_AQ_CAP_ID_VSI              0x0017
 414#define I40E_AQ_CAP_ID_DCB              0x0018
 415#define I40E_AQ_CAP_ID_FCOE             0x0021
 416#define I40E_AQ_CAP_ID_ISCSI            0x0022
 417#define I40E_AQ_CAP_ID_RSS              0x0040
 418#define I40E_AQ_CAP_ID_RXQ              0x0041
 419#define I40E_AQ_CAP_ID_TXQ              0x0042
 420#define I40E_AQ_CAP_ID_MSIX             0x0043
 421#define I40E_AQ_CAP_ID_VF_MSIX          0x0044
 422#define I40E_AQ_CAP_ID_FLOW_DIRECTOR    0x0045
 423#define I40E_AQ_CAP_ID_1588             0x0046
 424#define I40E_AQ_CAP_ID_IWARP            0x0051
 425#define I40E_AQ_CAP_ID_LED              0x0061
 426#define I40E_AQ_CAP_ID_SDP              0x0062
 427#define I40E_AQ_CAP_ID_MDIO             0x0063
 428#define I40E_AQ_CAP_ID_WSR_PROT         0x0064
 429#define I40E_AQ_CAP_ID_NVM_MGMT         0x0080
 430#define I40E_AQ_CAP_ID_FLEX10           0x00F1
 431#define I40E_AQ_CAP_ID_CEM              0x00F2
 432
 433/* Set CPPM Configuration (direct 0x0103) */
 434struct i40e_aqc_cppm_configuration {
 435        __le16  command_flags;
 436#define I40E_AQ_CPPM_EN_LTRC    0x0800
 437#define I40E_AQ_CPPM_EN_DMCTH   0x1000
 438#define I40E_AQ_CPPM_EN_DMCTLX  0x2000
 439#define I40E_AQ_CPPM_EN_HPTC    0x4000
 440#define I40E_AQ_CPPM_EN_DMARC   0x8000
 441        __le16  ttlx;
 442        __le32  dmacr;
 443        __le16  dmcth;
 444        u8      hptc;
 445        u8      reserved;
 446        __le32  pfltrc;
 447};
 448
 449I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
 450
 451/* Set ARP Proxy command / response (indirect 0x0104) */
 452struct i40e_aqc_arp_proxy_data {
 453        __le16  command_flags;
 454#define I40E_AQ_ARP_INIT_IPV4   0x0800
 455#define I40E_AQ_ARP_UNSUP_CTL   0x1000
 456#define I40E_AQ_ARP_ENA         0x2000
 457#define I40E_AQ_ARP_ADD_IPV4    0x4000
 458#define I40E_AQ_ARP_DEL_IPV4    0x8000
 459        __le16  table_id;
 460        __le32  enabled_offloads;
 461#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE     0x00000020
 462#define I40E_AQ_ARP_OFFLOAD_ENABLE              0x00000800
 463        __le32  ip_addr;
 464        u8      mac_addr[6];
 465        u8      reserved[2];
 466};
 467
 468I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
 469
 470/* Set NS Proxy Table Entry Command (indirect 0x0105) */
 471struct i40e_aqc_ns_proxy_data {
 472        __le16  table_idx_mac_addr_0;
 473        __le16  table_idx_mac_addr_1;
 474        __le16  table_idx_ipv6_0;
 475        __le16  table_idx_ipv6_1;
 476        __le16  control;
 477#define I40E_AQ_NS_PROXY_ADD_0          0x0001
 478#define I40E_AQ_NS_PROXY_DEL_0          0x0002
 479#define I40E_AQ_NS_PROXY_ADD_1          0x0004
 480#define I40E_AQ_NS_PROXY_DEL_1          0x0008
 481#define I40E_AQ_NS_PROXY_ADD_IPV6_0     0x0010
 482#define I40E_AQ_NS_PROXY_DEL_IPV6_0     0x0020
 483#define I40E_AQ_NS_PROXY_ADD_IPV6_1     0x0040
 484#define I40E_AQ_NS_PROXY_DEL_IPV6_1     0x0080
 485#define I40E_AQ_NS_PROXY_COMMAND_SEQ    0x0100
 486#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL  0x0200
 487#define I40E_AQ_NS_PROXY_INIT_MAC_TBL   0x0400
 488#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
 489#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE        0x1000
 490        u8      mac_addr_0[6];
 491        u8      mac_addr_1[6];
 492        u8      local_mac_addr[6];
 493        u8      ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
 494        u8      ipv6_addr_1[16];
 495};
 496
 497I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
 498
 499/* Manage LAA Command (0x0106) - obsolete */
 500struct i40e_aqc_mng_laa {
 501        __le16  command_flags;
 502#define I40E_AQ_LAA_FLAG_WR     0x8000
 503        u8      reserved[2];
 504        __le32  sal;
 505        __le16  sah;
 506        u8      reserved2[6];
 507};
 508
 509I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
 510
 511/* Manage MAC Address Read Command (indirect 0x0107) */
 512struct i40e_aqc_mac_address_read {
 513        __le16  command_flags;
 514#define I40E_AQC_LAN_ADDR_VALID         0x10
 515#define I40E_AQC_SAN_ADDR_VALID         0x20
 516#define I40E_AQC_PORT_ADDR_VALID        0x40
 517#define I40E_AQC_WOL_ADDR_VALID         0x80
 518#define I40E_AQC_MC_MAG_EN_VALID        0x100
 519#define I40E_AQC_ADDR_VALID_MASK        0x3F0
 520        u8      reserved[6];
 521        __le32  addr_high;
 522        __le32  addr_low;
 523};
 524
 525I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
 526
 527struct i40e_aqc_mac_address_read_data {
 528        u8 pf_lan_mac[6];
 529        u8 pf_san_mac[6];
 530        u8 port_mac[6];
 531        u8 pf_wol_mac[6];
 532};
 533
 534I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
 535
 536/* Manage MAC Address Write Command (0x0108) */
 537struct i40e_aqc_mac_address_write {
 538        __le16  command_flags;
 539#define I40E_AQC_WRITE_TYPE_LAA_ONLY    0x0000
 540#define I40E_AQC_WRITE_TYPE_LAA_WOL     0x4000
 541#define I40E_AQC_WRITE_TYPE_PORT        0x8000
 542#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG       0xC000
 543#define I40E_AQC_WRITE_TYPE_MASK        0xC000
 544
 545        __le16  mac_sah;
 546        __le32  mac_sal;
 547        u8      reserved[8];
 548};
 549
 550I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
 551
 552/* PXE commands (0x011x) */
 553
 554/* Clear PXE Command and response  (direct 0x0110) */
 555struct i40e_aqc_clear_pxe {
 556        u8      rx_cnt;
 557        u8      reserved[15];
 558};
 559
 560I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
 561
 562/* Set WoL Filter (0x0120) */
 563
 564struct i40e_aqc_set_wol_filter {
 565        __le16 filter_index;
 566#define I40E_AQC_MAX_NUM_WOL_FILTERS    8
 567#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT        15
 568#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
 569                I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
 570
 571#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT             0
 572#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK      (0x7 << \
 573                I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
 574        __le16 cmd_flags;
 575#define I40E_AQC_SET_WOL_FILTER                         0x8000
 576#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL              0x4000
 577#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR     0x2000
 578#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR            0
 579#define I40E_AQC_SET_WOL_FILTER_ACTION_SET              1
 580        __le16 valid_flags;
 581#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID            0x8000
 582#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID     0x4000
 583        u8 reserved[2];
 584        __le32  address_high;
 585        __le32  address_low;
 586};
 587
 588I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
 589
 590struct i40e_aqc_set_wol_filter_data {
 591        u8 filter[128];
 592        u8 mask[16];
 593};
 594
 595I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
 596
 597/* Get Wake Reason (0x0121) */
 598
 599struct i40e_aqc_get_wake_reason_completion {
 600        u8 reserved_1[2];
 601        __le16 wake_reason;
 602#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT      0
 603#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
 604                I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
 605#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT   8
 606#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK    (0xFF << \
 607                I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
 608        u8 reserved_2[12];
 609};
 610
 611I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
 612
 613/* Switch configuration commands (0x02xx) */
 614
 615/* Used by many indirect commands that only pass an seid and a buffer in the
 616 * command
 617 */
 618struct i40e_aqc_switch_seid {
 619        __le16  seid;
 620        u8      reserved[6];
 621        __le32  addr_high;
 622        __le32  addr_low;
 623};
 624
 625I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
 626
 627/* Get Switch Configuration command (indirect 0x0200)
 628 * uses i40e_aqc_switch_seid for the descriptor
 629 */
 630struct i40e_aqc_get_switch_config_header_resp {
 631        __le16  num_reported;
 632        __le16  num_total;
 633        u8      reserved[12];
 634};
 635
 636I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
 637
 638struct i40e_aqc_switch_config_element_resp {
 639        u8      element_type;
 640#define I40E_AQ_SW_ELEM_TYPE_MAC        1
 641#define I40E_AQ_SW_ELEM_TYPE_PF         2
 642#define I40E_AQ_SW_ELEM_TYPE_VF         3
 643#define I40E_AQ_SW_ELEM_TYPE_EMP        4
 644#define I40E_AQ_SW_ELEM_TYPE_BMC        5
 645#define I40E_AQ_SW_ELEM_TYPE_PV         16
 646#define I40E_AQ_SW_ELEM_TYPE_VEB        17
 647#define I40E_AQ_SW_ELEM_TYPE_PA         18
 648#define I40E_AQ_SW_ELEM_TYPE_VSI        19
 649        u8      revision;
 650#define I40E_AQ_SW_ELEM_REV_1           1
 651        __le16  seid;
 652        __le16  uplink_seid;
 653        __le16  downlink_seid;
 654        u8      reserved[3];
 655        u8      connection_type;
 656#define I40E_AQ_CONN_TYPE_REGULAR       0x1
 657#define I40E_AQ_CONN_TYPE_DEFAULT       0x2
 658#define I40E_AQ_CONN_TYPE_CASCADED      0x3
 659        __le16  scheduler_id;
 660        __le16  element_info;
 661};
 662
 663I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
 664
 665/* Get Switch Configuration (indirect 0x0200)
 666 *    an array of elements are returned in the response buffer
 667 *    the first in the array is the header, remainder are elements
 668 */
 669struct i40e_aqc_get_switch_config_resp {
 670        struct i40e_aqc_get_switch_config_header_resp   header;
 671        struct i40e_aqc_switch_config_element_resp      element[1];
 672};
 673
 674I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
 675
 676/* Add Statistics (direct 0x0201)
 677 * Remove Statistics (direct 0x0202)
 678 */
 679struct i40e_aqc_add_remove_statistics {
 680        __le16  seid;
 681        __le16  vlan;
 682        __le16  stat_index;
 683        u8      reserved[10];
 684};
 685
 686I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
 687
 688/* Set Port Parameters command (direct 0x0203) */
 689struct i40e_aqc_set_port_parameters {
 690        __le16  command_flags;
 691#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS   1
 692#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS  2 /* must set! */
 693#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA    4
 694        __le16  bad_frame_vsi;
 695#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT  0x0
 696#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK   0x3FF
 697        __le16  default_seid;        /* reserved for command */
 698        u8      reserved[10];
 699};
 700
 701I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
 702
 703/* Get Switch Resource Allocation (indirect 0x0204) */
 704struct i40e_aqc_get_switch_resource_alloc {
 705        u8      num_entries;         /* reserved for command */
 706        u8      reserved[7];
 707        __le32  addr_high;
 708        __le32  addr_low;
 709};
 710
 711I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
 712
 713/* expect an array of these structs in the response buffer */
 714struct i40e_aqc_switch_resource_alloc_element_resp {
 715        u8      resource_type;
 716#define I40E_AQ_RESOURCE_TYPE_VEB               0x0
 717#define I40E_AQ_RESOURCE_TYPE_VSI               0x1
 718#define I40E_AQ_RESOURCE_TYPE_MACADDR           0x2
 719#define I40E_AQ_RESOURCE_TYPE_STAG              0x3
 720#define I40E_AQ_RESOURCE_TYPE_ETAG              0x4
 721#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH    0x5
 722#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH      0x6
 723#define I40E_AQ_RESOURCE_TYPE_VLAN              0x7
 724#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY    0x8
 725#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY   0x9
 726#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL    0xA
 727#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE       0xB
 728#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS        0xC
 729#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS      0xD
 730#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
 731#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS        0x10
 732#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS       0x11
 733#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS          0x12
 734#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS      0x13
 735        u8      reserved1;
 736        __le16  guaranteed;
 737        __le16  total;
 738        __le16  used;
 739        __le16  total_unalloced;
 740        u8      reserved2[6];
 741};
 742
 743I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
 744
 745/* Set Switch Configuration (direct 0x0205) */
 746struct i40e_aqc_set_switch_config {
 747        __le16  flags;
 748/* flags used for both fields below */
 749#define I40E_AQ_SET_SWITCH_CFG_PROMISC          0x0001
 750#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER        0x0002
 751        __le16  valid_flags;
 752        /* The ethertype in switch_tag is dropped on ingress and used
 753         * internally by the switch. Set this to zero for the default
 754         * of 0x88a8 (802.1ad). Should be zero for firmware API
 755         * versions lower than 1.7.
 756         */
 757        __le16  switch_tag;
 758        /* The ethertypes in first_tag and second_tag are used to
 759         * match the outer and inner VLAN tags (respectively) when HW
 760         * double VLAN tagging is enabled via the set port parameters
 761         * AQ command. Otherwise these are both ignored. Set them to
 762         * zero for their defaults of 0x8100 (802.1Q). Should be zero
 763         * for firmware API versions lower than 1.7.
 764         */
 765        __le16  first_tag;
 766        __le16  second_tag;
 767        u8      reserved[6];
 768};
 769
 770I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
 771
 772/* Read Receive control registers  (direct 0x0206)
 773 * Write Receive control registers (direct 0x0207)
 774 *     used for accessing Rx control registers that can be
 775 *     slow and need special handling when under high Rx load
 776 */
 777struct i40e_aqc_rx_ctl_reg_read_write {
 778        __le32 reserved1;
 779        __le32 address;
 780        __le32 reserved2;
 781        __le32 value;
 782};
 783
 784I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
 785
 786/* Add VSI (indirect 0x0210)
 787 *    this indirect command uses struct i40e_aqc_vsi_properties_data
 788 *    as the indirect buffer (128 bytes)
 789 *
 790 * Update VSI (indirect 0x211)
 791 *     uses the same data structure as Add VSI
 792 *
 793 * Get VSI (indirect 0x0212)
 794 *     uses the same completion and data structure as Add VSI
 795 */
 796struct i40e_aqc_add_get_update_vsi {
 797        __le16  uplink_seid;
 798        u8      connection_type;
 799#define I40E_AQ_VSI_CONN_TYPE_NORMAL    0x1
 800#define I40E_AQ_VSI_CONN_TYPE_DEFAULT   0x2
 801#define I40E_AQ_VSI_CONN_TYPE_CASCADED  0x3
 802        u8      reserved1;
 803        u8      vf_id;
 804        u8      reserved2;
 805        __le16  vsi_flags;
 806#define I40E_AQ_VSI_TYPE_SHIFT          0x0
 807#define I40E_AQ_VSI_TYPE_MASK           (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
 808#define I40E_AQ_VSI_TYPE_VF             0x0
 809#define I40E_AQ_VSI_TYPE_VMDQ2          0x1
 810#define I40E_AQ_VSI_TYPE_PF             0x2
 811#define I40E_AQ_VSI_TYPE_EMP_MNG        0x3
 812#define I40E_AQ_VSI_FLAG_CASCADED_PV    0x4
 813        __le32  addr_high;
 814        __le32  addr_low;
 815};
 816
 817I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
 818
 819struct i40e_aqc_add_get_update_vsi_completion {
 820        __le16 seid;
 821        __le16 vsi_number;
 822        __le16 vsi_used;
 823        __le16 vsi_free;
 824        __le32 addr_high;
 825        __le32 addr_low;
 826};
 827
 828I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
 829
 830struct i40e_aqc_vsi_properties_data {
 831        /* first 96 byte are written by SW */
 832        __le16  valid_sections;
 833#define I40E_AQ_VSI_PROP_SWITCH_VALID           0x0001
 834#define I40E_AQ_VSI_PROP_SECURITY_VALID         0x0002
 835#define I40E_AQ_VSI_PROP_VLAN_VALID             0x0004
 836#define I40E_AQ_VSI_PROP_CAS_PV_VALID           0x0008
 837#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID       0x0010
 838#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID        0x0020
 839#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID        0x0040
 840#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID        0x0080
 841#define I40E_AQ_VSI_PROP_OUTER_UP_VALID         0x0100
 842#define I40E_AQ_VSI_PROP_SCHED_VALID            0x0200
 843        /* switch section */
 844        __le16  switch_id; /* 12bit id combined with flags below */
 845#define I40E_AQ_VSI_SW_ID_SHIFT         0x0000
 846#define I40E_AQ_VSI_SW_ID_MASK          (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
 847#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
 848#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
 849#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
 850        u8      sw_reserved[2];
 851        /* security section */
 852        u8      sec_flags;
 853#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
 854#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
 855#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04
 856        u8      sec_reserved;
 857        /* VLAN section */
 858        __le16  pvid; /* VLANS include priority bits */
 859        __le16  fcoe_pvid;
 860        u8      port_vlan_flags;
 861#define I40E_AQ_VSI_PVLAN_MODE_SHIFT    0x00
 862#define I40E_AQ_VSI_PVLAN_MODE_MASK     (0x03 << \
 863                                         I40E_AQ_VSI_PVLAN_MODE_SHIFT)
 864#define I40E_AQ_VSI_PVLAN_MODE_TAGGED   0x01
 865#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
 866#define I40E_AQ_VSI_PVLAN_MODE_ALL      0x03
 867#define I40E_AQ_VSI_PVLAN_INSERT_PVID   0x04
 868#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
 869#define I40E_AQ_VSI_PVLAN_EMOD_MASK     (0x3 << \
 870                                         I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
 871#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
 872#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
 873#define I40E_AQ_VSI_PVLAN_EMOD_STR      0x10
 874#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
 875        u8      pvlan_reserved[3];
 876        /* ingress egress up sections */
 877        __le32  ingress_table; /* bitmap, 3 bits per up */
 878#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT  0
 879#define I40E_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
 880                                         I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
 881#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT  3
 882#define I40E_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
 883                                         I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
 884#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT  6
 885#define I40E_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
 886                                         I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
 887#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT  9
 888#define I40E_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
 889                                         I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
 890#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT  12
 891#define I40E_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
 892                                         I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
 893#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT  15
 894#define I40E_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
 895                                         I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
 896#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT  18
 897#define I40E_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
 898                                         I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
 899#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT  21
 900#define I40E_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
 901                                         I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
 902        __le32  egress_table;   /* same defines as for ingress table */
 903        /* cascaded PV section */
 904        __le16  cas_pv_tag;
 905        u8      cas_pv_flags;
 906#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT           0x00
 907#define I40E_AQ_VSI_CAS_PV_TAGX_MASK            (0x03 << \
 908                                                 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
 909#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE           0x00
 910#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE          0x01
 911#define I40E_AQ_VSI_CAS_PV_TAGX_COPY            0x02
 912#define I40E_AQ_VSI_CAS_PV_INSERT_TAG           0x10
 913#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE           0x20
 914#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG      0x40
 915        u8      cas_pv_reserved;
 916        /* queue mapping section */
 917        __le16  mapping_flags;
 918#define I40E_AQ_VSI_QUE_MAP_CONTIG      0x0
 919#define I40E_AQ_VSI_QUE_MAP_NONCONTIG   0x1
 920        __le16  queue_mapping[16];
 921#define I40E_AQ_VSI_QUEUE_SHIFT         0x0
 922#define I40E_AQ_VSI_QUEUE_MASK          (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
 923        __le16  tc_mapping[8];
 924#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
 925#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
 926                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 927#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
 928#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
 929                                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 930        /* queueing option section */
 931        u8      queueing_opt_flags;
 932#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
 933#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA     0x08
 934#define I40E_AQ_VSI_QUE_OPT_TCP_ENA     0x10
 935#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
 936#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
 937#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
 938        u8      queueing_opt_reserved[3];
 939        /* scheduler section */
 940        u8      up_enable_bits;
 941        u8      sched_reserved;
 942        /* outer up section */
 943        __le32  outer_up_table; /* same structure and defines as ingress tbl */
 944        u8      cmd_reserved[8];
 945        /* last 32 bytes are written by FW */
 946        __le16  qs_handle[8];
 947#define I40E_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
 948        __le16  stat_counter_idx;
 949        __le16  sched_id;
 950        u8      resp_reserved[12];
 951};
 952
 953I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
 954
 955/* Add Port Virtualizer (direct 0x0220)
 956 * also used for update PV (direct 0x0221) but only flags are used
 957 * (IS_CTRL_PORT only works on add PV)
 958 */
 959struct i40e_aqc_add_update_pv {
 960        __le16  command_flags;
 961#define I40E_AQC_PV_FLAG_PV_TYPE                0x1
 962#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN    0x2
 963#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN    0x4
 964#define I40E_AQC_PV_FLAG_IS_CTRL_PORT           0x8
 965        __le16  uplink_seid;
 966        __le16  connected_seid;
 967        u8      reserved[10];
 968};
 969
 970I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
 971
 972struct i40e_aqc_add_update_pv_completion {
 973        /* reserved for update; for add also encodes error if rc == ENOSPC */
 974        __le16  pv_seid;
 975#define I40E_AQC_PV_ERR_FLAG_NO_PV      0x1
 976#define I40E_AQC_PV_ERR_FLAG_NO_SCHED   0x2
 977#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
 978#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY   0x8
 979        u8      reserved[14];
 980};
 981
 982I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
 983
 984/* Get PV Params (direct 0x0222)
 985 * uses i40e_aqc_switch_seid for the descriptor
 986 */
 987
 988struct i40e_aqc_get_pv_params_completion {
 989        __le16  seid;
 990        __le16  default_stag;
 991        __le16  pv_flags; /* same flags as add_pv */
 992#define I40E_AQC_GET_PV_PV_TYPE                 0x1
 993#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG       0x2
 994#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG       0x4
 995        u8      reserved[8];
 996        __le16  default_port_seid;
 997};
 998
 999I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1000

1001/* Add VEB (direct 0x0230) */
1002struct i40e_aqc_add_veb {
1003        __le16  uplink_seid;
1004        __le16  downlink_seid;
1005        __le16  veb_flags;
1006#define I40E_AQC_ADD_VEB_FLOATING               0x1
1007#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT        1
1008#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK         (0x3 << \
1009                                        I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1010#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT      0x2
1011#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA         0x4
1012#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER       0x8     /* deprecated */
1013#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS   0x10
1014        u8      enable_tcs;
1015        u8      reserved[9];
1016};
1017
1018I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1019
1020struct i40e_aqc_add_veb_completion {
1021        u8      reserved[6];
1022        __le16  switch_seid;
1023        /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1024        __le16  veb_seid;
1025#define I40E_AQC_VEB_ERR_FLAG_NO_VEB            0x1
1026#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED          0x2
1027#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER        0x4
1028#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY          0x8
1029        __le16  statistic_index;
1030        __le16  vebs_used;
1031        __le16  vebs_free;
1032};
1033
1034I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1035
1036/* Get VEB Parameters (direct 0x0232)
1037 * uses i40e_aqc_switch_seid for the descriptor
1038 */
1039struct i40e_aqc_get_veb_parameters_completion {
1040        __le16  seid;
1041        __le16  switch_id;
1042        __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
1043        __le16  statistic_index;
1044        __le16  vebs_used;
1045        __le16  vebs_free;
1046        u8      reserved[4];
1047};
1048
1049I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1050
1051/* Delete Element (direct 0x0243)
1052 * uses the generic i40e_aqc_switch_seid
1053 */
1054
1055/* Add MAC-VLAN (indirect 0x0250) */
1056
1057/* used for the command for most vlan commands */
1058struct i40e_aqc_macvlan {
1059        __le16  num_addresses;
1060        __le16  seid[3];
1061#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT     0
1062#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK      (0x3FF << \
1063                                        I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1064#define I40E_AQC_MACVLAN_CMD_SEID_VALID         0x8000
1065        __le32  addr_high;
1066        __le32  addr_low;
1067};
1068
1069I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1070
1071/* indirect data for command and response */
1072struct i40e_aqc_add_macvlan_element_data {
1073        u8      mac_addr[6];
1074        __le16  vlan_tag;
1075        __le16  flags;
1076#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH      0x0001
1077#define I40E_AQC_MACVLAN_ADD_HASH_MATCH         0x0002
1078#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN        0x0004
1079#define I40E_AQC_MACVLAN_ADD_TO_QUEUE           0x0008
1080#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC     0x0010
1081        __le16  queue_number;
1082#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT        0
1083#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK         (0x7FF << \
1084                                        I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1085        /* response section */
1086        u8      match_method;
1087#define I40E_AQC_MM_PERFECT_MATCH       0x01
1088#define I40E_AQC_MM_HASH_MATCH          0x02
1089#define I40E_AQC_MM_ERR_NO_RES          0xFF
1090        u8      reserved1[3];
1091};
1092
1093struct i40e_aqc_add_remove_macvlan_completion {
1094        __le16 perfect_mac_used;
1095        __le16 perfect_mac_free;
1096        __le16 unicast_hash_free;
1097        __le16 multicast_hash_free;
1098        __le32 addr_high;
1099        __le32 addr_low;
1100};
1101
1102I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1103
1104/* Remove MAC-VLAN (indirect 0x0251)
1105 * uses i40e_aqc_macvlan for the descriptor
1106 * data points to an array of num_addresses of elements
1107 */
1108
1109struct i40e_aqc_remove_macvlan_element_data {
1110        u8      mac_addr[6];
1111        __le16  vlan_tag;
1112        u8      flags;
1113#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH      0x01
1114#define I40E_AQC_MACVLAN_DEL_HASH_MATCH         0x02
1115#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN        0x08
1116#define I40E_AQC_MACVLAN_DEL_ALL_VSIS           0x10
1117        u8      reserved[3];
1118        /* reply section */
1119        u8      error_code;
1120#define I40E_AQC_REMOVE_MACVLAN_SUCCESS         0x0
1121#define I40E_AQC_REMOVE_MACVLAN_FAIL            0xFF
1122        u8      reply_reserved[3];
1123};
1124
1125/* Add VLAN (indirect 0x0252)
1126 * Remove VLAN (indirect 0x0253)
1127 * use the generic i40e_aqc_macvlan for the command
1128 */
1129struct i40e_aqc_add_remove_vlan_element_data {
1130        __le16  vlan_tag;
1131        u8      vlan_flags;
1132/* flags for add VLAN */
1133#define I40E_AQC_ADD_VLAN_LOCAL                 0x1
1134#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT           1
1135#define I40E_AQC_ADD_PVLAN_TYPE_MASK    (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1136#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR         0x0
1137#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY         0x2
1138#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY       0x4
1139#define I40E_AQC_VLAN_PTYPE_SHIFT               3
1140#define I40E_AQC_VLAN_PTYPE_MASK        (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1141#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI         0x0
1142#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI         0x8
1143#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI       0x10
1144#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI        0x18
1145/* flags for remove VLAN */
1146#define I40E_AQC_REMOVE_VLAN_ALL        0x1
1147        u8      reserved;
1148        u8      result;
1149/* flags for add VLAN */
1150#define I40E_AQC_ADD_VLAN_SUCCESS       0x0
1151#define I40E_AQC_ADD_VLAN_FAIL_REQUEST  0xFE
1152#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1153/* flags for remove VLAN */
1154#define I40E_AQC_REMOVE_VLAN_SUCCESS    0x0
1155#define I40E_AQC_REMOVE_VLAN_FAIL       0xFF
1156        u8      reserved1[3];
1157};
1158
1159struct i40e_aqc_add_remove_vlan_completion {
1160        u8      reserved[4];
1161        __le16  vlans_used;
1162        __le16  vlans_free;
1163        __le32  addr_high;
1164        __le32  addr_low;
1165};
1166
1167/* Set VSI Promiscuous Modes (direct 0x0254) */
1168struct i40e_aqc_set_vsi_promiscuous_modes {
1169        __le16  promiscuous_flags;
1170        __le16  valid_flags;
1171/* flags used for both fields above */
1172#define I40E_AQC_SET_VSI_PROMISC_UNICAST        0x01
1173#define I40E_AQC_SET_VSI_PROMISC_MULTICAST      0x02
1174#define I40E_AQC_SET_VSI_PROMISC_BROADCAST      0x04
1175#define I40E_AQC_SET_VSI_DEFAULT                0x08
1176#define I40E_AQC_SET_VSI_PROMISC_VLAN           0x10
1177#define I40E_AQC_SET_VSI_PROMISC_TX             0x8000
1178        __le16  seid;
1179#define I40E_AQC_VSI_PROM_CMD_SEID_MASK         0x3FF
1180        __le16  vlan_tag;
1181#define I40E_AQC_SET_VSI_VLAN_MASK              0x0FFF
1182#define I40E_AQC_SET_VSI_VLAN_VALID             0x8000
1183        u8      reserved[8];
1184};
1185
1186I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1187
1188/* Add S/E-tag command (direct 0x0255)
1189 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1190 */
1191struct i40e_aqc_add_tag {
1192        __le16  flags;
1193#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE          0x0001
1194        __le16  seid;
1195#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT     0
1196#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK      (0x3FF << \
1197                                        I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1198        __le16  tag;
1199        __le16  queue_number;
1200        u8      reserved[8];
1201};
1202
1203I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1204
1205struct i40e_aqc_add_remove_tag_completion {
1206        u8      reserved[12];
1207        __le16  tags_used;
1208        __le16  tags_free;
1209};
1210
1211I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1212
1213/* Remove S/E-tag command (direct 0x0256)
1214 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1215 */
1216struct i40e_aqc_remove_tag {
1217        __le16  seid;
1218#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT  0
1219#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1220                                        I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1221        __le16  tag;
1222        u8      reserved[12];
1223};
1224
1225I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1226
1227/* Add multicast E-Tag (direct 0x0257)
1228 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1229 * and no external data
1230 */
1231struct i40e_aqc_add_remove_mcast_etag {
1232        __le16  pv_seid;
1233        __le16  etag;
1234        u8      num_unicast_etags;
1235        u8      reserved[3];
1236        __le32  addr_high;          /* address of array of 2-byte s-tags */
1237        __le32  addr_low;
1238};
1239
1240I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1241
1242struct i40e_aqc_add_remove_mcast_etag_completion {
1243        u8      reserved[4];
1244        __le16  mcast_etags_used;
1245        __le16  mcast_etags_free;
1246        __le32  addr_high;
1247        __le32  addr_low;
1248
1249};
1250
1251I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1252
1253/* Update S/E-Tag (direct 0x0259) */
1254struct i40e_aqc_update_tag {
1255        __le16  seid;
1256#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT  0
1257#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1258                                        I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1259        __le16  old_tag;
1260        __le16  new_tag;
1261        u8      reserved[10];
1262};
1263
1264I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1265
1266struct i40e_aqc_update_tag_completion {
1267        u8      reserved[12];
1268        __le16  tags_used;
1269        __le16  tags_free;
1270};
1271
1272I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1273
1274/* Add Control Packet filter (direct 0x025A)
1275 * Remove Control Packet filter (direct 0x025B)
1276 * uses the i40e_aqc_add_oveb_cloud,
1277 * and the generic direct completion structure
1278 */
1279struct i40e_aqc_add_remove_control_packet_filter {
1280        u8      mac[6];
1281        __le16  etype;
1282        __le16  flags;
1283#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC    0x0001
1284#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP          0x0002
1285#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE      0x0004
1286#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX            0x0008
1287#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX            0x0000
1288        __le16  seid;
1289#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT  0
1290#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK   (0x3FF << \
1291                                I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1292        __le16  queue;
1293        u8      reserved[2];
1294};
1295
1296I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1297
1298struct i40e_aqc_add_remove_control_packet_filter_completion {
1299        __le16  mac_etype_used;
1300        __le16  etype_used;
1301        __le16  mac_etype_free;
1302        __le16  etype_free;
1303        u8      reserved[8];
1304};
1305
1306I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1307
1308/* Add Cloud filters (indirect 0x025C)
1309 * Remove Cloud filters (indirect 0x025D)
1310 * uses the i40e_aqc_add_remove_cloud_filters,
1311 * and the generic indirect completion structure
1312 */
1313struct i40e_aqc_add_remove_cloud_filters {
1314        u8      num_filters;
1315        u8      reserved;
1316        __le16  seid;
1317#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT   0
1318#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK    (0x3FF << \
1319                                        I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1320        u8      big_buffer_flag;
1321#define I40E_AQC_ADD_CLOUD_CMD_BB       1
1322        u8      reserved2[3];
1323        __le32  addr_high;
1324        __le32  addr_low;
1325};
1326
1327I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1328
1329struct i40e_aqc_cloud_filters_element_data {
1330        u8      outer_mac[6];
1331        u8      inner_mac[6];
1332        __le16  inner_vlan;
1333        union {
1334                struct {
1335                        u8 reserved[12];
1336                        u8 data[4];
1337                } v4;
1338                struct {
1339                        u8 data[16];
1340                } v6;
1341                struct {
1342                        __le16 data[8];
1343                } raw_v6;
1344        } ipaddr;
1345        __le16  flags;
1346#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT                 0
1347#define I40E_AQC_ADD_CLOUD_FILTER_MASK  (0x3F << \
1348                                        I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1349/* 0x0000 reserved */
1350#define I40E_AQC_ADD_CLOUD_FILTER_OIP                   0x0001
1351/* 0x0002 reserved */
1352#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN            0x0003
1353#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID     0x0004
1354/* 0x0005 reserved */
1355#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID           0x0006
1356/* 0x0007 reserved */
1357/* 0x0008 reserved */
1358#define I40E_AQC_ADD_CLOUD_FILTER_OMAC                  0x0009
1359#define I40E_AQC_ADD_CLOUD_FILTER_IMAC                  0x000A
1360#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC      0x000B
1361#define I40E_AQC_ADD_CLOUD_FILTER_IIP                   0x000C
1362/* 0x0010 to 0x0017 is for custom filters */
1363#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT               0x0010 /* Dest IP + L4 Port */
1364#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT              0x0011 /* Dest MAC + L4 Port */
1365#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT         0x0012 /* Dest MAC + VLAN + L4 Port */
1366
1367#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE               0x0080
1368#define I40E_AQC_ADD_CLOUD_VNK_SHIFT                    6
1369#define I40E_AQC_ADD_CLOUD_VNK_MASK                     0x00C0
1370#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4                   0
1371#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6                   0x0100
1372
1373#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT               9
1374#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK                0x1E00
1375#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN               0
1376#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC          1
1377#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE              2
1378#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP                  3
1379#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED            4
1380#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE           5
1381
1382#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC       0x2000
1383#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC       0x4000
1384#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP        0x8000
1385
1386        __le32  tenant_id;
1387        u8      reserved[4];
1388        __le16  queue_number;
1389#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT          0
1390#define I40E_AQC_ADD_CLOUD_QUEUE_MASK           (0x7FF << \
1391                                                 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1392        u8      reserved2[14];
1393        /* response section */
1394        u8      allocation_result;
1395#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS       0x0
1396#define I40E_AQC_ADD_CLOUD_FILTER_FAIL          0xFF
1397        u8      response_reserved[7];
1398};
1399
1400I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1401
1402/* i40e_aqc_cloud_filters_element_bb is used when
1403 * I40E_AQC_ADD_CLOUD_CMD_BB flag is set.
1404 */
1405struct i40e_aqc_cloud_filters_element_bb {
1406        struct i40e_aqc_cloud_filters_element_data element;
1407        u16     general_fields[32];
1408#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0    0
1409#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1    1
1410#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2    2
1411#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0    3
1412#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1    4
1413#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2    5
1414#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0    6
1415#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1    7
1416#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2    8
1417#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0    9
1418#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1    10
1419#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2    11
1420#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0    12
1421#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1    13
1422#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2    14
1423#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0    15
1424#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1    16
1425#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2    17
1426#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3    18
1427#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4    19
1428#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5    20
1429#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6    21
1430#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7    22
1431#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0    23
1432#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1    24
1433#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2    25
1434#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3    26
1435#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4    27
1436#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5    28
1437#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6    29
1438#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7    30
1439};
1440
1441I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1442
1443struct i40e_aqc_remove_cloud_filters_completion {
1444        __le16 perfect_ovlan_used;
1445        __le16 perfect_ovlan_free;
1446        __le16 vlan_used;
1447        __le16 vlan_free;
1448        __le32 addr_high;
1449        __le32 addr_low;
1450};
1451
1452I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1453
1454/* Replace filter Command 0x025F
1455 * uses the i40e_aqc_replace_cloud_filters,
1456 * and the generic indirect completion structure
1457 */
1458struct i40e_filter_data {
1459        u8 filter_type;
1460        u8 input[3];
1461};
1462
1463I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1464
1465struct i40e_aqc_replace_cloud_filters_cmd {
1466        u8      valid_flags;
1467#define I40E_AQC_REPLACE_L1_FILTER              0x0
1468#define I40E_AQC_REPLACE_CLOUD_FILTER           0x1
1469#define I40E_AQC_GET_CLOUD_FILTERS              0x2
1470#define I40E_AQC_MIRROR_CLOUD_FILTER            0x4
1471#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER     0x8
1472        u8      old_filter_type;
1473        u8      new_filter_type;
1474        u8      tr_bit;
1475        u8      reserved[4];
1476        __le32 addr_high;
1477        __le32 addr_low;
1478};
1479
1480I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1481
1482struct i40e_aqc_replace_cloud_filters_cmd_buf {
1483        u8      data[32];
1484/* Filter type INPUT codes*/
1485#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX    3
1486#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED      BIT(7)
1487
1488/* Field Vector offsets */
1489#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA      0
1490#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH    6
1491#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG        7
1492#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN        8
1493#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN  9
1494#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN  10
1495#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY  11
1496#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC        12
1497/* big FLU */
1498#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA       14
1499/* big FLU */
1500#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA      15
1501
1502#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN  37
1503        struct i40e_filter_data filters[8];
1504};
1505
1506I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1507
1508/* Add Mirror Rule (indirect or direct 0x0260)
1509 * Delete Mirror Rule (indirect or direct 0x0261)
1510 * note: some rule types (4,5) do not use an external buffer.
1511 *       take care to set the flags correctly.
1512 */
1513struct i40e_aqc_add_delete_mirror_rule {
1514        __le16 seid;
1515        __le16 rule_type;
1516#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT         0
1517#define I40E_AQC_MIRROR_RULE_TYPE_MASK          (0x7 << \
1518                                                I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1519#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1520#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS  2
1521#define I40E_AQC_MIRROR_RULE_TYPE_VLAN          3
1522#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS   4
1523#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS    5
1524        __le16 num_entries;
1525        __le16 destination;  /* VSI for add, rule id for delete */
1526        __le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1527        __le32 addr_low;
1528};
1529
1530I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1531
1532struct i40e_aqc_add_delete_mirror_rule_completion {
1533        u8      reserved[2];
1534        __le16  rule_id;  /* only used on add */
1535        __le16  mirror_rules_used;
1536        __le16  mirror_rules_free;
1537        __le32  addr_high;
1538        __le32  addr_low;
1539};
1540
1541I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1542
1543/* Dynamic Device Personalization */
1544struct i40e_aqc_write_personalization_profile {
1545        u8      flags;
1546        u8      reserved[3];
1547        __le32  profile_track_id;
1548        __le32  addr_high;
1549        __le32  addr_low;
1550};
1551
1552I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1553
1554struct i40e_aqc_write_ddp_resp {
1555        __le32 error_offset;
1556        __le32 error_info;
1557        __le32 addr_high;
1558        __le32 addr_low;
1559};
1560
1561struct i40e_aqc_get_applied_profiles {
1562        u8      flags;
1563#define I40E_AQC_GET_DDP_GET_CONF       0x1
1564#define I40E_AQC_GET_DDP_GET_RDPU_CONF  0x2
1565        u8      rsv[3];
1566        __le32  reserved;
1567        __le32  addr_high;
1568        __le32  addr_low;
1569};
1570
1571I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1572
1573/* DCB 0x03xx*/
1574
1575/* PFC Ignore (direct 0x0301)
1576 *    the command and response use the same descriptor structure
1577 */
1578struct i40e_aqc_pfc_ignore {
1579        u8      tc_bitmap;
1580        u8      command_flags; /* unused on response */
1581#define I40E_AQC_PFC_IGNORE_SET         0x80
1582#define I40E_AQC_PFC_IGNORE_CLEAR       0x0
1583        u8      reserved[14];
1584};
1585
1586I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1587
1588/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1589 * with no parameters
1590 */
1591
1592/* TX scheduler 0x04xx */
1593
1594/* Almost all the indirect commands use
1595 * this generic struct to pass the SEID in param0
1596 */
1597struct i40e_aqc_tx_sched_ind {
1598        __le16  vsi_seid;
1599        u8      reserved[6];
1600        __le32  addr_high;
1601        __le32  addr_low;
1602};
1603
1604I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1605
1606/* Several commands respond with a set of queue set handles */
1607struct i40e_aqc_qs_handles_resp {
1608        __le16 qs_handles[8];
1609};
1610
1611/* Configure VSI BW limits (direct 0x0400) */
1612struct i40e_aqc_configure_vsi_bw_limit {
1613        __le16  vsi_seid;
1614        u8      reserved[2];
1615        __le16  credit;
1616        u8      reserved1[2];
1617        u8      max_credit; /* 0-3, limit = 2^max */
1618        u8      reserved2[7];
1619};
1620
1621I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1622
1623/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1624 *    responds with i40e_aqc_qs_handles_resp
1625 */
1626struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1627        u8      tc_valid_bits;
1628        u8      reserved[15];
1629        __le16  tc_bw_credits[8]; /* FW writesback QS handles here */
1630
1631        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1632        __le16  tc_bw_max[2];
1633        u8      reserved1[28];
1634};
1635
1636I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1637
1638/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1639 *    responds with i40e_aqc_qs_handles_resp
1640 */
1641struct i40e_aqc_configure_vsi_tc_bw_data {
1642        u8      tc_valid_bits;
1643        u8      reserved[3];
1644        u8      tc_bw_credits[8];
1645        u8      reserved1[4];
1646        __le16  qs_handles[8];
1647};
1648
1649I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1650
1651/* Query vsi bw configuration (indirect 0x0408) */
1652struct i40e_aqc_query_vsi_bw_config_resp {
1653        u8      tc_valid_bits;
1654        u8      tc_suspended_bits;
1655        u8      reserved[14];
1656        __le16  qs_handles[8];
1657        u8      reserved1[4];
1658        __le16  port_bw_limit;
1659        u8      reserved2[2];
1660        u8      max_bw; /* 0-3, limit = 2^max */
1661        u8      reserved3[23];
1662};
1663
1664I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1665
1666/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1667struct i40e_aqc_query_vsi_ets_sla_config_resp {
1668        u8      tc_valid_bits;
1669        u8      reserved[3];
1670        u8      share_credits[8];
1671        __le16  credits[8];
1672
1673        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1674        __le16  tc_bw_max[2];
1675};
1676
1677I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1678
1679/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1680struct i40e_aqc_configure_switching_comp_bw_limit {
1681        __le16  seid;
1682        u8      reserved[2];
1683        __le16  credit;
1684        u8      reserved1[2];
1685        u8      max_bw; /* 0-3, limit = 2^max */
1686        u8      reserved2[7];
1687};
1688
1689I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1690
1691/* Enable  Physical Port ETS (indirect 0x0413)
1692 * Modify  Physical Port ETS (indirect 0x0414)
1693 * Disable Physical Port ETS (indirect 0x0415)
1694 */
1695struct i40e_aqc_configure_switching_comp_ets_data {
1696        u8      reserved[4];
1697        u8      tc_valid_bits;
1698        u8      seepage;
1699#define I40E_AQ_ETS_SEEPAGE_EN_MASK     0x1
1700        u8      tc_strict_priority_flags;
1701        u8      reserved1[17];
1702        u8      tc_bw_share_credits[8];
1703        u8      reserved2[96];
1704};
1705
1706I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1707
1708/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1709struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1710        u8      tc_valid_bits;
1711        u8      reserved[15];
1712        __le16  tc_bw_credit[8];
1713
1714        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1715        __le16  tc_bw_max[2];
1716        u8      reserved1[28];
1717};
1718
1719I40E_CHECK_STRUCT_LEN(0x40,
1720                      i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1721
1722/* Configure Switching Component Bandwidth Allocation per Tc
1723 * (indirect 0x0417)
1724 */
1725struct i40e_aqc_configure_switching_comp_bw_config_data {
1726        u8      tc_valid_bits;
1727        u8      reserved[2];
1728        u8      absolute_credits; /* bool */
1729        u8      tc_bw_share_credits[8];
1730        u8      reserved1[20];
1731};
1732
1733I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1734
1735/* Query Switching Component Configuration (indirect 0x0418) */
1736struct i40e_aqc_query_switching_comp_ets_config_resp {
1737        u8      tc_valid_bits;
1738        u8      reserved[35];
1739        __le16  port_bw_limit;
1740        u8      reserved1[2];
1741        u8      tc_bw_max; /* 0-3, limit = 2^max */
1742        u8      reserved2[23];
1743};
1744
1745I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1746
1747/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1748struct i40e_aqc_query_port_ets_config_resp {
1749        u8      reserved[4];
1750        u8      tc_valid_bits;
1751        u8      reserved1;
1752        u8      tc_strict_priority_bits;
1753        u8      reserved2;
1754        u8      tc_bw_share_credits[8];
1755        __le16  tc_bw_limits[8];
1756
1757        /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1758        __le16  tc_bw_max[2];
1759        u8      reserved3[32];
1760};
1761
1762I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1763
1764/* Query Switching Component Bandwidth Allocation per Traffic Type
1765 * (indirect 0x041A)
1766 */
1767struct i40e_aqc_query_switching_comp_bw_config_resp {
1768        u8      tc_valid_bits;
1769        u8      reserved[2];
1770        u8      absolute_credits_enable; /* bool */
1771        u8      tc_bw_share_credits[8];
1772        __le16  tc_bw_limits[8];
1773
1774        /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1775        __le16  tc_bw_max[2];
1776};
1777
1778I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1779
1780/* Suspend/resume port TX traffic
1781 * (direct 0x041B and 0x041C) uses the generic SEID struct
1782 */
1783
1784/* Configure partition BW
1785 * (indirect 0x041D)
1786 */
1787struct i40e_aqc_configure_partition_bw_data {
1788        __le16  pf_valid_bits;
1789        u8      min_bw[16];      /* guaranteed bandwidth */
1790        u8      max_bw[16];      /* bandwidth limit */
1791};
1792
1793I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1794
1795/* Get and set the active HMC resource profile and status.
1796 * (direct 0x0500) and (direct 0x0501)
1797 */
1798struct i40e_aq_get_set_hmc_resource_profile {
1799        u8      pm_profile;
1800        u8      pe_vf_enabled;
1801        u8      reserved[14];
1802};
1803
1804I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1805
1806enum i40e_aq_hmc_profile {
1807        /* I40E_HMC_PROFILE_NO_CHANGE   = 0, reserved */
1808        I40E_HMC_PROFILE_DEFAULT        = 1,
1809        I40E_HMC_PROFILE_FAVOR_VF       = 2,
1810        I40E_HMC_PROFILE_EQUAL          = 3,
1811};
1812
1813/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1814
1815/* set in param0 for get phy abilities to report qualified modules */
1816#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES    0x0001
1817#define I40E_AQ_PHY_REPORT_INITIAL_VALUES       0x0002
1818
1819enum i40e_aq_phy_type {
1820        I40E_PHY_TYPE_SGMII                     = 0x0,
1821        I40E_PHY_TYPE_1000BASE_KX               = 0x1,
1822        I40E_PHY_TYPE_10GBASE_KX4               = 0x2,
1823        I40E_PHY_TYPE_10GBASE_KR                = 0x3,
1824        I40E_PHY_TYPE_40GBASE_KR4               = 0x4,
1825        I40E_PHY_TYPE_XAUI                      = 0x5,
1826        I40E_PHY_TYPE_XFI                       = 0x6,
1827        I40E_PHY_TYPE_SFI                       = 0x7,
1828        I40E_PHY_TYPE_XLAUI                     = 0x8,
1829        I40E_PHY_TYPE_XLPPI                     = 0x9,
1830        I40E_PHY_TYPE_40GBASE_CR4_CU            = 0xA,
1831        I40E_PHY_TYPE_10GBASE_CR1_CU            = 0xB,
1832        I40E_PHY_TYPE_10GBASE_AOC               = 0xC,
1833        I40E_PHY_TYPE_40GBASE_AOC               = 0xD,
1834        I40E_PHY_TYPE_UNRECOGNIZED              = 0xE,
1835        I40E_PHY_TYPE_UNSUPPORTED               = 0xF,
1836        I40E_PHY_TYPE_100BASE_TX                = 0x11,
1837        I40E_PHY_TYPE_1000BASE_T                = 0x12,
1838        I40E_PHY_TYPE_10GBASE_T                 = 0x13,
1839        I40E_PHY_TYPE_10GBASE_SR                = 0x14,
1840        I40E_PHY_TYPE_10GBASE_LR                = 0x15,
1841        I40E_PHY_TYPE_10GBASE_SFPP_CU           = 0x16,
1842        I40E_PHY_TYPE_10GBASE_CR1               = 0x17,
1843        I40E_PHY_TYPE_40GBASE_CR4               = 0x18,
1844        I40E_PHY_TYPE_40GBASE_SR4               = 0x19,
1845        I40E_PHY_TYPE_40GBASE_LR4               = 0x1A,
1846        I40E_PHY_TYPE_1000BASE_SX               = 0x1B,
1847        I40E_PHY_TYPE_1000BASE_LX               = 0x1C,
1848        I40E_PHY_TYPE_1000BASE_T_OPTICAL        = 0x1D,
1849        I40E_PHY_TYPE_20GBASE_KR2               = 0x1E,
1850        I40E_PHY_TYPE_25GBASE_KR                = 0x1F,
1851        I40E_PHY_TYPE_25GBASE_CR                = 0x20,
1852        I40E_PHY_TYPE_25GBASE_SR                = 0x21,
1853        I40E_PHY_TYPE_25GBASE_LR                = 0x22,
1854        I40E_PHY_TYPE_25GBASE_AOC               = 0x23,
1855        I40E_PHY_TYPE_25GBASE_ACC               = 0x24,
1856        I40E_PHY_TYPE_MAX,
1857        I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP   = 0xFD,
1858        I40E_PHY_TYPE_EMPTY                     = 0xFE,
1859        I40E_PHY_TYPE_DEFAULT                   = 0xFF,
1860};
1861
1862#define I40E_LINK_SPEED_100MB_SHIFT     0x1
1863#define I40E_LINK_SPEED_1000MB_SHIFT    0x2
1864#define I40E_LINK_SPEED_10GB_SHIFT      0x3
1865#define I40E_LINK_SPEED_40GB_SHIFT      0x4
1866#define I40E_LINK_SPEED_20GB_SHIFT      0x5
1867#define I40E_LINK_SPEED_25GB_SHIFT      0x6
1868
1869enum i40e_aq_link_speed {
1870        I40E_LINK_SPEED_UNKNOWN = 0,
1871        I40E_LINK_SPEED_100MB   = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1872        I40E_LINK_SPEED_1GB     = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1873        I40E_LINK_SPEED_10GB    = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1874        I40E_LINK_SPEED_40GB    = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1875        I40E_LINK_SPEED_20GB    = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1876        I40E_LINK_SPEED_25GB    = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1877};
1878
1879struct i40e_aqc_module_desc {
1880        u8 oui[3];
1881        u8 reserved1;
1882        u8 part_number[16];
1883        u8 revision[4];
1884        u8 reserved2[8];
1885};
1886
1887I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1888
1889struct i40e_aq_get_phy_abilities_resp {
1890        __le32  phy_type;       /* bitmap using the above enum for offsets */
1891        u8      link_speed;     /* bitmap using the above enum bit patterns */
1892        u8      abilities;
1893#define I40E_AQ_PHY_FLAG_PAUSE_TX       0x01
1894#define I40E_AQ_PHY_FLAG_PAUSE_RX       0x02
1895#define I40E_AQ_PHY_FLAG_LOW_POWER      0x04
1896#define I40E_AQ_PHY_LINK_ENABLED        0x08
1897#define I40E_AQ_PHY_AN_ENABLED          0x10
1898#define I40E_AQ_PHY_FLAG_MODULE_QUAL    0x20
1899#define I40E_AQ_PHY_FEC_ABILITY_KR      0x40
1900#define I40E_AQ_PHY_FEC_ABILITY_RS      0x80
1901        __le16  eee_capability;
1902#define I40E_AQ_EEE_100BASE_TX          0x0002
1903#define I40E_AQ_EEE_1000BASE_T          0x0004
1904#define I40E_AQ_EEE_10GBASE_T           0x0008
1905#define I40E_AQ_EEE_1000BASE_KX         0x0010
1906#define I40E_AQ_EEE_10GBASE_KX4         0x0020
1907#define I40E_AQ_EEE_10GBASE_KR          0x0040
1908        __le32  eeer_val;
1909        u8      d3_lpan;
1910#define I40E_AQ_SET_PHY_D3_LPAN_ENA     0x01
1911        u8      phy_type_ext;
1912#define I40E_AQ_PHY_TYPE_EXT_25G_KR     0X01
1913#define I40E_AQ_PHY_TYPE_EXT_25G_CR     0X02
1914#define I40E_AQ_PHY_TYPE_EXT_25G_SR     0x04
1915#define I40E_AQ_PHY_TYPE_EXT_25G_LR     0x08
1916#define I40E_AQ_PHY_TYPE_EXT_25G_AOC    0x10
1917#define I40E_AQ_PHY_TYPE_EXT_25G_ACC    0x20
1918        u8      fec_cfg_curr_mod_ext_info;
1919#define I40E_AQ_ENABLE_FEC_KR           0x01
1920#define I40E_AQ_ENABLE_FEC_RS           0x02
1921#define I40E_AQ_REQUEST_FEC_KR          0x04
1922#define I40E_AQ_REQUEST_FEC_RS          0x08
1923#define I40E_AQ_ENABLE_FEC_AUTO         0x10
1924#define I40E_AQ_FEC
1925#define I40E_AQ_MODULE_TYPE_EXT_MASK    0xE0
1926#define I40E_AQ_MODULE_TYPE_EXT_SHIFT   5
1927
1928        u8      ext_comp_code;
1929        u8      phy_id[4];
1930        u8      module_type[3];
1931        u8      qualified_module_count;
1932#define I40E_AQ_PHY_MAX_QMS             16
1933        struct i40e_aqc_module_desc     qualified_module[I40E_AQ_PHY_MAX_QMS];
1934};
1935
1936I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1937
1938/* Set PHY Config (direct 0x0601) */
1939struct i40e_aq_set_phy_config { /* same bits as above in all */
1940        __le32  phy_type;
1941        u8      link_speed;
1942        u8      abilities;
1943/* bits 0-2 use the values from get_phy_abilities_resp */
1944#define I40E_AQ_PHY_ENABLE_LINK         0x08
1945#define I40E_AQ_PHY_ENABLE_AN           0x10
1946#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK  0x20
1947        __le16  eee_capability;
1948        __le32  eeer;
1949        u8      low_power_ctrl;
1950        u8      phy_type_ext;
1951#define I40E_AQ_PHY_TYPE_EXT_25G_KR     0X01
1952#define I40E_AQ_PHY_TYPE_EXT_25G_CR     0X02
1953#define I40E_AQ_PHY_TYPE_EXT_25G_SR     0x04
1954#define I40E_AQ_PHY_TYPE_EXT_25G_LR     0x08
1955        u8      fec_config;
1956#define I40E_AQ_SET_FEC_ABILITY_KR      BIT(0)
1957#define I40E_AQ_SET_FEC_ABILITY_RS      BIT(1)
1958#define I40E_AQ_SET_FEC_REQUEST_KR      BIT(2)
1959#define I40E_AQ_SET_FEC_REQUEST_RS      BIT(3)
1960#define I40E_AQ_SET_FEC_AUTO            BIT(4)
1961#define I40E_AQ_PHY_FEC_CONFIG_SHIFT    0x0
1962#define I40E_AQ_PHY_FEC_CONFIG_MASK     (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1963        u8      reserved;
1964};
1965
1966I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1967
1968/* Set MAC Config command data structure (direct 0x0603) */
1969struct i40e_aq_set_mac_config {
1970        __le16  max_frame_size;
1971        u8      params;
1972#define I40E_AQ_SET_MAC_CONFIG_CRC_EN           0x04
1973#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK      0x78
1974#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT     3
1975#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE      0x0
1976#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX   0xF
1977#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX   0x9
1978#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX   0x8
1979#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX   0x7
1980#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX   0x6
1981#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX   0x5
1982#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX   0x4
1983#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX   0x3
1984#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX   0x2
1985#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX   0x1
1986        u8      tx_timer_priority; /* bitmap */
1987        __le16  tx_timer_value;
1988        __le16  fc_refresh_threshold;
1989        u8      reserved[8];
1990};
1991
1992I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1993
1994/* Restart Auto-Negotiation (direct 0x605) */
1995struct i40e_aqc_set_link_restart_an {
1996        u8      command;
1997#define I40E_AQ_PHY_RESTART_AN  0x02
1998#define I40E_AQ_PHY_LINK_ENABLE 0x04
1999        u8      reserved[15];
2000};

2001
2002I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2003
2004/* Get Link Status cmd & response data structure (direct 0x0607) */
2005struct i40e_aqc_get_link_status {
2006        __le16  command_flags; /* only field set on command */
2007#define I40E_AQ_LSE_MASK                0x3
2008#define I40E_AQ_LSE_NOP                 0x0
2009#define I40E_AQ_LSE_DISABLE             0x2
2010#define I40E_AQ_LSE_ENABLE              0x3
2011/* only response uses this flag */
2012#define I40E_AQ_LSE_IS_ENABLED          0x1
2013        u8      phy_type;    /* i40e_aq_phy_type   */
2014        u8      link_speed;  /* i40e_aq_link_speed */
2015        u8      link_info;
2016#define I40E_AQ_LINK_UP                 0x01    /* obsolete */
2017#define I40E_AQ_LINK_UP_FUNCTION        0x01
2018#define I40E_AQ_LINK_FAULT              0x02
2019#define I40E_AQ_LINK_FAULT_TX           0x04
2020#define I40E_AQ_LINK_FAULT_RX           0x08
2021#define I40E_AQ_LINK_FAULT_REMOTE       0x10
2022#define I40E_AQ_LINK_UP_PORT            0x20
2023#define I40E_AQ_MEDIA_AVAILABLE         0x40
2024#define I40E_AQ_SIGNAL_DETECT           0x80
2025        u8      an_info;
2026#define I40E_AQ_AN_COMPLETED            0x01
2027#define I40E_AQ_LP_AN_ABILITY           0x02
2028#define I40E_AQ_PD_FAULT                0x04
2029#define I40E_AQ_FEC_EN                  0x08
2030#define I40E_AQ_PHY_LOW_POWER           0x10
2031#define I40E_AQ_LINK_PAUSE_TX           0x20
2032#define I40E_AQ_LINK_PAUSE_RX           0x40
2033#define I40E_AQ_QUALIFIED_MODULE        0x80
2034        u8      ext_info;
2035#define I40E_AQ_LINK_PHY_TEMP_ALARM     0x01
2036#define I40E_AQ_LINK_XCESSIVE_ERRORS    0x02
2037#define I40E_AQ_LINK_TX_SHIFT           0x02
2038#define I40E_AQ_LINK_TX_MASK            (0x03 << I40E_AQ_LINK_TX_SHIFT)
2039#define I40E_AQ_LINK_TX_ACTIVE          0x00
2040#define I40E_AQ_LINK_TX_DRAINED         0x01
2041#define I40E_AQ_LINK_TX_FLUSHED         0x03
2042#define I40E_AQ_LINK_FORCED_40G         0x10
2043/* 25G Error Codes */
2044#define I40E_AQ_25G_NO_ERR              0X00
2045#define I40E_AQ_25G_NOT_PRESENT         0X01
2046#define I40E_AQ_25G_NVM_CRC_ERR         0X02
2047#define I40E_AQ_25G_SBUS_UCODE_ERR      0X03
2048#define I40E_AQ_25G_SERDES_UCODE_ERR    0X04
2049#define I40E_AQ_25G_NIMB_UCODE_ERR      0X05
2050        u8      loopback; /* use defines from i40e_aqc_set_lb_mode */
2051/* Since firmware API 1.7 loopback field keeps power class info as well */
2052#define I40E_AQ_LOOPBACK_MASK           0x07
2053#define I40E_AQ_PWR_CLASS_SHIFT_LB      6
2054#define I40E_AQ_PWR_CLASS_MASK_LB       (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2055        __le16  max_frame_size;
2056        u8      config;
2057#define I40E_AQ_CONFIG_FEC_KR_ENA       0x01
2058#define I40E_AQ_CONFIG_FEC_RS_ENA       0x02
2059#define I40E_AQ_CONFIG_CRC_ENA          0x04
2060#define I40E_AQ_CONFIG_PACING_MASK      0x78
2061        union {
2062                struct {
2063                        u8      power_desc;
2064#define I40E_AQ_LINK_POWER_CLASS_1      0x00
2065#define I40E_AQ_LINK_POWER_CLASS_2      0x01
2066#define I40E_AQ_LINK_POWER_CLASS_3      0x02
2067#define I40E_AQ_LINK_POWER_CLASS_4      0x03
2068#define I40E_AQ_PWR_CLASS_MASK          0x03
2069                        u8      reserved[4];
2070                };
2071                struct {
2072                        u8      link_type[4];
2073                        u8      link_type_ext;
2074                };
2075        };
2076};
2077
2078I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2079
2080/* Set event mask command (direct 0x613) */
2081struct i40e_aqc_set_phy_int_mask {
2082        u8      reserved[8];
2083        __le16  event_mask;
2084#define I40E_AQ_EVENT_LINK_UPDOWN       0x0002
2085#define I40E_AQ_EVENT_MEDIA_NA          0x0004
2086#define I40E_AQ_EVENT_LINK_FAULT        0x0008
2087#define I40E_AQ_EVENT_PHY_TEMP_ALARM    0x0010
2088#define I40E_AQ_EVENT_EXCESSIVE_ERRORS  0x0020
2089#define I40E_AQ_EVENT_SIGNAL_DETECT     0x0040
2090#define I40E_AQ_EVENT_AN_COMPLETED      0x0080
2091#define I40E_AQ_EVENT_MODULE_QUAL_FAIL  0x0100
2092#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2093        u8      reserved1[6];
2094};
2095
2096I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2097
2098/* Get Local AN advt register (direct 0x0614)
2099 * Set Local AN advt register (direct 0x0615)
2100 * Get Link Partner AN advt register (direct 0x0616)
2101 */
2102struct i40e_aqc_an_advt_reg {
2103        __le32  local_an_reg0;
2104        __le16  local_an_reg1;
2105        u8      reserved[10];
2106};
2107
2108I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2109
2110/* Set Loopback mode (0x0618) */
2111struct i40e_aqc_set_lb_mode {
2112        __le16  lb_mode;
2113#define I40E_AQ_LB_PHY_LOCAL    0x01
2114#define I40E_AQ_LB_PHY_REMOTE   0x02
2115#define I40E_AQ_LB_MAC_LOCAL    0x04
2116        u8      reserved[14];
2117};
2118
2119I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2120
2121/* Set PHY Debug command (0x0622) */
2122struct i40e_aqc_set_phy_debug {
2123        u8      command_flags;
2124#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL        0x02
2125#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT  2
2126#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK   (0x03 << \
2127                                        I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2128#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE   0x00
2129#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD   0x01
2130#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT   0x02
2131#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW       0x10
2132        u8      reserved[15];
2133};
2134
2135I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2136
2137enum i40e_aq_phy_reg_type {
2138        I40E_AQC_PHY_REG_INTERNAL       = 0x1,
2139        I40E_AQC_PHY_REG_EXERNAL_BASET  = 0x2,
2140        I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2141};
2142
2143/* Run PHY Activity (0x0626) */
2144struct i40e_aqc_run_phy_activity {
2145        __le16  activity_id;
2146        u8      flags;
2147        u8      reserved1;
2148        __le32  control;
2149        __le32  data;
2150        u8      reserved2[4];
2151};
2152
2153I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2154
2155/* Set PHY Register command (0x0628) */
2156/* Get PHY Register command (0x0629) */
2157struct i40e_aqc_phy_register_access {
2158        u8      phy_interface;
2159#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2160#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2161#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE  2
2162        u8      dev_address;
2163        u8      reserved1[2];
2164        __le32  reg_address;
2165        __le32  reg_value;
2166        u8      reserved2[4];
2167};
2168
2169I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2170
2171/* NVM Read command (indirect 0x0701)
2172 * NVM Erase commands (direct 0x0702)
2173 * NVM Update commands (indirect 0x0703)
2174 */
2175struct i40e_aqc_nvm_update {
2176        u8      command_flags;
2177#define I40E_AQ_NVM_LAST_CMD                    0x01
2178#define I40E_AQ_NVM_REARRANGE_TO_FLAT           0x20
2179#define I40E_AQ_NVM_REARRANGE_TO_STRUCT         0x40
2180#define I40E_AQ_NVM_FLASH_ONLY                  0x80
2181#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT    1
2182#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK     0x03
2183#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2184#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL      0x01
2185        u8      module_pointer;
2186        __le16  length;
2187        __le32  offset;
2188        __le32  addr_high;
2189        __le32  addr_low;
2190};
2191
2192I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2193
2194/* NVM Config Read (indirect 0x0704) */
2195struct i40e_aqc_nvm_config_read {
2196        __le16  cmd_flags;
2197#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK   1
2198#define I40E_AQ_ANVM_READ_SINGLE_FEATURE                0
2199#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES             1
2200        __le16  element_count;
2201        __le16  element_id;     /* Feature/field ID */
2202        __le16  element_id_msw; /* MSWord of field ID */
2203        __le32  address_high;
2204        __le32  address_low;
2205};
2206
2207I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2208
2209/* NVM Config Write (indirect 0x0705) */
2210struct i40e_aqc_nvm_config_write {
2211        __le16  cmd_flags;
2212        __le16  element_count;
2213        u8      reserved[4];
2214        __le32  address_high;
2215        __le32  address_low;
2216};
2217
2218I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2219
2220/* Used for 0x0704 as well as for 0x0705 commands */
2221#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT         1
2222#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2223                                BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2224#define I40E_AQ_ANVM_FEATURE            0
2225#define I40E_AQ_ANVM_IMMEDIATE_FIELD    BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2226struct i40e_aqc_nvm_config_data_feature {
2227        __le16 feature_id;
2228#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY            0x01
2229#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP           0x08
2230#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR             0x10
2231        __le16 feature_options;
2232        __le16 feature_selection;
2233};
2234
2235I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2236
2237struct i40e_aqc_nvm_config_data_immediate_field {
2238        __le32 field_id;
2239        __le32 field_value;
2240        __le16 field_options;
2241        __le16 reserved;
2242};
2243
2244I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2245
2246/* OEM Post Update (indirect 0x0720)
2247 * no command data struct used
2248 */
2249 struct i40e_aqc_nvm_oem_post_update {
2250#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA       0x01
2251        u8 sel_data;
2252        u8 reserved[7];
2253};
2254
2255I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2256
2257struct i40e_aqc_nvm_oem_post_update_buffer {
2258        u8 str_len;
2259        u8 dev_addr;
2260        __le16 eeprom_addr;
2261        u8 data[36];
2262};
2263
2264I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2265
2266/* Thermal Sensor (indirect 0x0721)
2267 *     read or set thermal sensor configs and values
2268 *     takes a sensor and command specific data buffer, not detailed here
2269 */
2270struct i40e_aqc_thermal_sensor {
2271        u8 sensor_action;
2272#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG      0
2273#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG       1
2274#define I40E_AQ_THERMAL_SENSOR_READ_TEMP        2
2275        u8 reserved[7];
2276        __le32  addr_high;
2277        __le32  addr_low;
2278};
2279
2280I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2281
2282/* Send to PF command (indirect 0x0801) id is only used by PF
2283 * Send to VF command (indirect 0x0802) id is only used by PF
2284 * Send to Peer PF command (indirect 0x0803)
2285 */
2286struct i40e_aqc_pf_vf_message {
2287        __le32  id;
2288        u8      reserved[4];
2289        __le32  addr_high;
2290        __le32  addr_low;
2291};
2292
2293I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2294
2295/* Alternate structure */
2296
2297/* Direct write (direct 0x0900)
2298 * Direct read (direct 0x0902)
2299 */
2300struct i40e_aqc_alternate_write {
2301        __le32 address0;
2302        __le32 data0;
2303        __le32 address1;
2304        __le32 data1;
2305};
2306
2307I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2308
2309/* Indirect write (indirect 0x0901)
2310 * Indirect read (indirect 0x0903)
2311 */
2312
2313struct i40e_aqc_alternate_ind_write {
2314        __le32 address;
2315        __le32 length;
2316        __le32 addr_high;
2317        __le32 addr_low;
2318};
2319
2320I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2321
2322/* Done alternate write (direct 0x0904)
2323 * uses i40e_aq_desc
2324 */
2325struct i40e_aqc_alternate_write_done {
2326        __le16  cmd_flags;
2327#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK        1
2328#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY      0
2329#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI        1
2330#define I40E_AQ_ALTERNATE_RESET_NEEDED          2
2331        u8      reserved[14];
2332};
2333
2334I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2335
2336/* Set OEM mode (direct 0x0905) */
2337struct i40e_aqc_alternate_set_mode {
2338        __le32  mode;
2339#define I40E_AQ_ALTERNATE_MODE_NONE     0
2340#define I40E_AQ_ALTERNATE_MODE_OEM      1
2341        u8      reserved[12];
2342};
2343
2344I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2345
2346/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2347
2348/* async events 0x10xx */
2349
2350/* Lan Queue Overflow Event (direct, 0x1001) */
2351struct i40e_aqc_lan_overflow {
2352        __le32  prtdcb_rupto;
2353        __le32  otx_ctl;
2354        u8      reserved[8];
2355};
2356
2357I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2358
2359/* Get LLDP MIB (indirect 0x0A00) */
2360struct i40e_aqc_lldp_get_mib {
2361        u8      type;
2362        u8      reserved1;
2363#define I40E_AQ_LLDP_MIB_TYPE_MASK              0x3
2364#define I40E_AQ_LLDP_MIB_LOCAL                  0x0
2365#define I40E_AQ_LLDP_MIB_REMOTE                 0x1
2366#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE       0x2
2367#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK           0xC
2368#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT          0x2
2369#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2370#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR       0x1
2371#define I40E_AQ_LLDP_TX_SHIFT                   0x4
2372#define I40E_AQ_LLDP_TX_MASK                    (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2373/* TX pause flags use I40E_AQ_LINK_TX_* above */
2374        __le16  local_len;
2375        __le16  remote_len;
2376        u8      reserved2[2];
2377        __le32  addr_high;
2378        __le32  addr_low;
2379};
2380
2381I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2382
2383/* Configure LLDP MIB Change Event (direct 0x0A01)
2384 * also used for the event (with type in the command field)
2385 */
2386struct i40e_aqc_lldp_update_mib {
2387        u8      command;
2388#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE  0x0
2389#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2390        u8      reserved[7];
2391        __le32  addr_high;
2392        __le32  addr_low;
2393};
2394
2395I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2396
2397/* Add LLDP TLV (indirect 0x0A02)
2398 * Delete LLDP TLV (indirect 0x0A04)
2399 */
2400struct i40e_aqc_lldp_add_tlv {
2401        u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2402        u8      reserved1[1];
2403        __le16  len;
2404        u8      reserved2[4];
2405        __le32  addr_high;
2406        __le32  addr_low;
2407};
2408
2409I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2410
2411/* Update LLDP TLV (indirect 0x0A03) */
2412struct i40e_aqc_lldp_update_tlv {
2413        u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2414        u8      reserved;
2415        __le16  old_len;
2416        __le16  new_offset;
2417        __le16  new_len;
2418        __le32  addr_high;
2419        __le32  addr_low;
2420};
2421
2422I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2423
2424/* Stop LLDP (direct 0x0A05) */
2425struct i40e_aqc_lldp_stop {
2426        u8      command;
2427#define I40E_AQ_LLDP_AGENT_STOP         0x0
2428#define I40E_AQ_LLDP_AGENT_SHUTDOWN     0x1
2429        u8      reserved[15];
2430};
2431
2432I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2433
2434/* Start LLDP (direct 0x0A06) */
2435
2436struct i40e_aqc_lldp_start {
2437        u8      command;
2438#define I40E_AQ_LLDP_AGENT_START        0x1
2439        u8      reserved[15];
2440};
2441
2442I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2443
2444/* Set DCB (direct 0x0303) */
2445struct i40e_aqc_set_dcb_parameters {
2446        u8 command;
2447#define I40E_AQ_DCB_SET_AGENT   0x1
2448#define I40E_DCB_VALID          0x1
2449        u8 valid_flags;
2450        u8 reserved[14];
2451};
2452
2453I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2454
2455/* Apply MIB changes (0x0A07)
2456 * uses the generic struc as it contains no data
2457 */
2458
2459/* Add Udp Tunnel command and completion (direct 0x0B00) */
2460struct i40e_aqc_add_udp_tunnel {
2461        __le16  udp_port;
2462        u8      reserved0[3];
2463        u8      protocol_type;
2464#define I40E_AQC_TUNNEL_TYPE_VXLAN      0x00
2465#define I40E_AQC_TUNNEL_TYPE_NGE        0x01
2466#define I40E_AQC_TUNNEL_TYPE_TEREDO     0x10
2467#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE  0x11
2468        u8      reserved1[10];
2469};
2470
2471I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2472
2473struct i40e_aqc_add_udp_tunnel_completion {
2474        __le16 udp_port;
2475        u8      filter_entry_index;
2476        u8      multiple_pfs;
2477#define I40E_AQC_SINGLE_PF              0x0
2478#define I40E_AQC_MULTIPLE_PFS           0x1
2479        u8      total_filters;
2480        u8      reserved[11];
2481};
2482
2483I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2484
2485/* remove UDP Tunnel command (0x0B01) */
2486struct i40e_aqc_remove_udp_tunnel {
2487        u8      reserved[2];
2488        u8      index; /* 0 to 15 */
2489        u8      reserved2[13];
2490};
2491
2492I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2493
2494struct i40e_aqc_del_udp_tunnel_completion {
2495        __le16  udp_port;
2496        u8      index; /* 0 to 15 */
2497        u8      multiple_pfs;
2498        u8      total_filters_used;
2499        u8      reserved1[11];
2500};
2501
2502I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2503
2504struct i40e_aqc_get_set_rss_key {
2505#define I40E_AQC_SET_RSS_KEY_VSI_VALID          BIT(15)
2506#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT       0
2507#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK        (0x3FF << \
2508                                        I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2509        __le16  vsi_id;
2510        u8      reserved[6];
2511        __le32  addr_high;
2512        __le32  addr_low;
2513};
2514
2515I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2516
2517struct i40e_aqc_get_set_rss_key_data {
2518        u8 standard_rss_key[0x28];
2519        u8 extended_hash_key[0xc];
2520};
2521
2522I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2523
2524struct  i40e_aqc_get_set_rss_lut {
2525#define I40E_AQC_SET_RSS_LUT_VSI_VALID          BIT(15)
2526#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT       0
2527#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK        (0x3FF << \
2528                                        I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2529        __le16  vsi_id;
2530#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
2531#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
2532                                BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2533
2534#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI     0
2535#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF      1
2536        __le16  flags;
2537        u8      reserved[4];
2538        __le32  addr_high;
2539        __le32  addr_low;
2540};
2541
2542I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2543
2544/* tunnel key structure 0x0B10 */
2545
2546struct i40e_aqc_tunnel_key_structure_A0 {
2547        __le16     key1_off;
2548        __le16     key1_len;
2549        __le16     key2_off;
2550        __le16     key2_len;
2551        __le16     flags;
2552#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2553/* response flags */
2554#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS    0x01
2555#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED   0x02
2556#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2557        u8         resreved[6];
2558};
2559
2560I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2561
2562struct i40e_aqc_tunnel_key_structure {
2563        u8      key1_off;
2564        u8      key2_off;
2565        u8      key1_len;  /* 0 to 15 */
2566        u8      key2_len;  /* 0 to 15 */
2567        u8      flags;
2568#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE     0x01
2569/* response flags */
2570#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS      0x01
2571#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED     0x02
2572#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN   0x03
2573        u8      network_key_index;
2574#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN                0x0
2575#define I40E_AQC_NETWORK_KEY_INDEX_NGE                  0x1
2576#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP      0x2
2577#define I40E_AQC_NETWORK_KEY_INDEX_GRE                  0x3
2578        u8      reserved[10];
2579};
2580
2581I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2582
2583/* OEM mode commands (direct 0xFE0x) */
2584struct i40e_aqc_oem_param_change {
2585        __le32  param_type;
2586#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL   0
2587#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL   1
2588#define I40E_AQ_OEM_PARAM_MAC           2
2589        __le32  param_value1;
2590        __le16  param_value2;
2591        u8      reserved[6];
2592};
2593
2594I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2595
2596struct i40e_aqc_oem_state_change {
2597        __le32  state;
2598#define I40E_AQ_OEM_STATE_LINK_DOWN     0x0
2599#define I40E_AQ_OEM_STATE_LINK_UP       0x1
2600        u8      reserved[12];
2601};
2602
2603I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2604
2605/* Initialize OCSD (0xFE02, direct) */
2606struct i40e_aqc_opc_oem_ocsd_initialize {
2607        u8 type_status;
2608        u8 reserved1[3];
2609        __le32 ocsd_memory_block_addr_high;
2610        __le32 ocsd_memory_block_addr_low;
2611        __le32 requested_update_interval;
2612};
2613
2614I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2615
2616/* Initialize OCBB  (0xFE03, direct) */
2617struct i40e_aqc_opc_oem_ocbb_initialize {
2618        u8 type_status;
2619        u8 reserved1[3];
2620        __le32 ocbb_memory_block_addr_high;
2621        __le32 ocbb_memory_block_addr_low;
2622        u8 reserved2[4];
2623};
2624
2625I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2626
2627/* debug commands */
2628
2629/* get device id (0xFF00) uses the generic structure */
2630
2631/* set test more (0xFF01, internal) */
2632
2633struct i40e_acq_set_test_mode {
2634        u8      mode;
2635#define I40E_AQ_TEST_PARTIAL    0
2636#define I40E_AQ_TEST_FULL       1
2637#define I40E_AQ_TEST_NVM        2
2638        u8      reserved[3];
2639        u8      command;
2640#define I40E_AQ_TEST_OPEN       0
2641#define I40E_AQ_TEST_CLOSE      1
2642#define I40E_AQ_TEST_INC        2
2643        u8      reserved2[3];
2644        __le32  address_high;
2645        __le32  address_low;
2646};
2647
2648I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2649
2650/* Debug Read Register command (0xFF03)
2651 * Debug Write Register command (0xFF04)
2652 */
2653struct i40e_aqc_debug_reg_read_write {
2654        __le32 reserved;
2655        __le32 address;
2656        __le32 value_high;
2657        __le32 value_low;
2658};
2659
2660I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2661
2662/* Scatter/gather Reg Read  (indirect 0xFF05)
2663 * Scatter/gather Reg Write (indirect 0xFF06)
2664 */
2665
2666/* i40e_aq_desc is used for the command */
2667struct i40e_aqc_debug_reg_sg_element_data {
2668        __le32 address;
2669        __le32 value;
2670};
2671
2672/* Debug Modify register (direct 0xFF07) */
2673struct i40e_aqc_debug_modify_reg {
2674        __le32 address;
2675        __le32 value;
2676        __le32 clear_mask;
2677        __le32 set_mask;
2678};
2679
2680I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2681
2682/* dump internal data (0xFF08, indirect) */
2683
2684#define I40E_AQ_CLUSTER_ID_AUX          0
2685#define I40E_AQ_CLUSTER_ID_SWITCH_FLU   1
2686#define I40E_AQ_CLUSTER_ID_TXSCHED      2
2687#define I40E_AQ_CLUSTER_ID_HMC          3
2688#define I40E_AQ_CLUSTER_ID_MAC0         4
2689#define I40E_AQ_CLUSTER_ID_MAC1         5
2690#define I40E_AQ_CLUSTER_ID_MAC2         6
2691#define I40E_AQ_CLUSTER_ID_MAC3         7
2692#define I40E_AQ_CLUSTER_ID_DCB          8
2693#define I40E_AQ_CLUSTER_ID_EMP_MEM      9
2694#define I40E_AQ_CLUSTER_ID_PKT_BUF      10
2695#define I40E_AQ_CLUSTER_ID_ALTRAM       11
2696
2697struct i40e_aqc_debug_dump_internals {
2698        u8      cluster_id;
2699        u8      table_id;
2700        __le16  data_size;
2701        __le32  idx;
2702        __le32  address_high;
2703        __le32  address_low;
2704};
2705
2706I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2707
2708struct i40e_aqc_debug_modify_internals {
2709        u8      cluster_id;
2710        u8      cluster_specific_params[7];
2711        __le32  address_high;
2712        __le32  address_low;
2713};
2714
2715I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2716
2717#endif /* _I40E_ADMINQ_CMD_H_ */
2718