LXR linux/drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.h

   1/*
   2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
   3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
   4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2
   8 * as published by the Free Software Foundation
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#ifndef MT76X0U_H
  17#define MT76X0U_H
  18
  19#include <linux/bitfield.h>
  20#include <linux/kernel.h>
  21#include <linux/device.h>
  22#include <linux/mutex.h>
  23#include <linux/usb.h>
  24#include <linux/completion.h>
  25#include <net/mac80211.h>
  26#include <linux/debugfs.h>
  27
  28#include "../mt76.h"
  29#include "regs.h"
  30
  31#define MT_CALIBRATE_INTERVAL           (4 * HZ)
  32
  33#define MT_FREQ_CAL_INIT_DELAY          (30 * HZ)
  34#define MT_FREQ_CAL_CHECK_INTERVAL      (10 * HZ)
  35#define MT_FREQ_CAL_ADJ_INTERVAL        (HZ / 2)
  36
  37#define MT_BBP_REG_VERSION              0x00
  38
  39#define MT_USB_AGGR_SIZE_LIMIT          21 /* * 1024B */
  40#define MT_USB_AGGR_TIMEOUT             0x80 /* * 33ns */
  41#define MT_RX_ORDER                     3
  42#define MT_RX_URB_SIZE                  (PAGE_SIZE << MT_RX_ORDER)
  43
  44struct mt76x0_dma_buf {
  45        struct urb *urb;
  46        void *buf;
  47        dma_addr_t dma;
  48        size_t len;
  49};
  50
  51struct mt76x0_mcu {
  52        struct mutex mutex;
  53
  54        u8 msg_seq;
  55
  56        struct mt76x0_dma_buf resp;
  57        struct completion resp_cmpl;
  58
  59        struct mt76_reg_pair *reg_pairs;
  60        unsigned int reg_pairs_len;
  61        u32 reg_base;
  62        bool burst_read;
  63};
  64
  65struct mac_stats {
  66        u64 rx_stat[6];
  67        u64 tx_stat[6];
  68        u64 aggr_stat[2];
  69        u64 aggr_n[32];
  70        u64 zero_len_del[2];
  71};
  72
  73#define N_RX_ENTRIES    16
  74struct mt76x0_rx_queue {
  75        struct mt76x0_dev *dev;
  76
  77        struct mt76x0_dma_buf_rx {
  78                struct urb *urb;
  79                struct page *p;
  80        } e[N_RX_ENTRIES];
  81
  82        unsigned int start;
  83        unsigned int end;
  84        unsigned int entries;
  85        unsigned int pending;
  86};
  87
  88#define N_TX_ENTRIES    64
  89
  90struct mt76x0_tx_queue {
  91        struct mt76x0_dev *dev;
  92
  93        struct mt76x0_dma_buf_tx {
  94                struct urb *urb;
  95                struct sk_buff *skb;
  96        } e[N_TX_ENTRIES];
  97
  98        unsigned int start;
  99        unsigned int end;
 100        unsigned int entries;
 101        unsigned int used;
 102        unsigned int fifo_seq;
 103};
 104
 105/* WCID allocation:
 106 *     0: mcast wcid
 107 *     1: bssid wcid
 108 *  1...: STAs
 109 * ...7e: group wcids
 110 *    7f: reserved
 111 */
 112#define N_WCIDS         128
 113#define GROUP_WCID(idx) (254 - idx)
 114
 115struct mt76x0_eeprom_params;
 116
 117#define MT_EE_TEMPERATURE_SLOPE         39
 118#define MT_FREQ_OFFSET_INVALID          -128
 119
 120/* addr req mask */
 121#define MT_VEND_TYPE_EEPROM     BIT(31)
 122#define MT_VEND_TYPE_CFG        BIT(30)
 123#define MT_VEND_TYPE_MASK       (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
 124
 125#define MT_VEND_ADDR(type, n)   (MT_VEND_TYPE_##type | (n))
 126
 127enum mt_bw {
 128        MT_BW_20,
 129        MT_BW_40,
 130};
 131
 132/**
 133 * struct mt76x0_dev - adapter structure
 134 * @lock:               protects @wcid->tx_rate.
 135 * @mac_lock:           locks out mac80211's tx status and rx paths.
 136 * @tx_lock:            protects @tx_q and changes of MT76_STATE_*_STATS
 137 *                      flags in @state.
 138 * @rx_lock:            protects @rx_q.
 139 * @con_mon_lock:       protects @ap_bssid, @bcn_*, @avg_rssi.
 140 * @mutex:              ensures exclusive access from mac80211 callbacks.
 141 * @reg_atomic_mutex:   ensures atomicity of indirect register accesses
 142 *                      (accesses to RF and BBP).
 143 * @hw_atomic_mutex:    ensures exclusive access to HW during critical
 144 *                      operations (power management, channel switch).
 145 */
 146struct mt76x0_dev {
 147        struct mt76_dev mt76; /* must be first */
 148
 149        struct mutex mutex;
 150
 151        struct mutex usb_ctrl_mtx;
 152        u8 data[32];
 153
 154        struct tasklet_struct rx_tasklet;
 155        struct tasklet_struct tx_tasklet;
 156
 157        u8 out_ep[__MT_EP_OUT_MAX];
 158        u16 out_max_packet;
 159        u8 in_ep[__MT_EP_IN_MAX];
 160        u16 in_max_packet;
 161
 162        unsigned long wcid_mask[DIV_ROUND_UP(N_WCIDS, BITS_PER_LONG)];
 163        unsigned long vif_mask;
 164
 165        struct mt76x0_mcu mcu;
 166
 167        struct delayed_work cal_work;
 168        struct delayed_work mac_work;
 169
 170        struct workqueue_struct *stat_wq;
 171        struct delayed_work stat_work;
 172
 173        struct mt76_wcid *mon_wcid;
 174        struct mt76_wcid __rcu *wcid[N_WCIDS];
 175
 176        spinlock_t mac_lock;
 177
 178        const u16 *beacon_offsets;
 179
 180        u8 macaddr[ETH_ALEN];
 181        struct mt76x0_eeprom_params *ee;
 182
 183        struct mutex reg_atomic_mutex;
 184        struct mutex hw_atomic_mutex;
 185
 186        u32 rxfilter;
 187        u32 debugfs_reg;
 188
 189        /* TX */
 190        spinlock_t tx_lock;
 191        struct mt76x0_tx_queue *tx_q;
 192        struct sk_buff_head tx_skb_done;
 193
 194        atomic_t avg_ampdu_len;
 195
 196        /* RX */
 197        spinlock_t rx_lock;
 198        struct mt76x0_rx_queue rx_q;
 199
 200        /* Connection monitoring things */
 201        spinlock_t con_mon_lock;
 202        u8 ap_bssid[ETH_ALEN];
 203
 204        s8 bcn_freq_off;
 205        u8 bcn_phy_mode;
 206
 207        int avg_rssi; /* starts at 0 and converges */
 208
 209        u8 agc_save;
 210        u16 chainmask;
 211
 212        struct mac_stats stats;
 213};
 214
 215struct mt76x0_wcid {
 216        u8 idx;
 217        u8 hw_key_idx;
 218
 219        u16 tx_rate;
 220        bool tx_rate_set;
 221        u8 tx_rate_nss;
 222};
 223
 224struct mt76_vif {
 225        u8 idx;
 226
 227        struct mt76_wcid group_wcid;
 228};
 229
 230struct mt76_tx_status {
 231        u8 valid:1;
 232        u8 success:1;
 233        u8 aggr:1;
 234        u8 ack_req:1;
 235        u8 is_probe:1;
 236        u8 wcid;
 237        u8 pktid;
 238        u8 retry;
 239        u16 rate;
 240} __packed __aligned(2);
 241
 242struct mt76_sta {
 243        struct mt76_wcid wcid;
 244        struct mt76_tx_status status;
 245        int n_frames;
 246        u16 agg_ssn[IEEE80211_NUM_TIDS];
 247};
 248
 249struct mt76_reg_pair {
 250        u32 reg;
 251        u32 value;
 252};
 253
 254struct mt76x0_rxwi;
 255
 256extern const struct ieee80211_ops mt76x0_ops;
 257
 258static inline bool is_mt7610e(struct mt76x0_dev *dev)
 259{
 260        /* TODO */
 261        return false;
 262}
 263
 264void mt76x0_init_debugfs(struct mt76x0_dev *dev);
 265
 266int mt76x0_wait_asic_ready(struct mt76x0_dev *dev);
 267
 268/* Compatibility with mt76 */
 269#define mt76_rmw_field(_dev, _reg, _field, _val)        \
 270        mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
 271
 272int mt76x0_write_reg_pairs(struct mt76x0_dev *dev, u32 base,
 273                            const struct mt76_reg_pair *data, int len);
 274int mt76x0_read_reg_pairs(struct mt76x0_dev *dev, u32 base,
 275                          struct mt76_reg_pair *data, int len);
 276int mt76x0_burst_write_regs(struct mt76x0_dev *dev, u32 offset,
 277                             const u32 *data, int n);
 278void mt76x0_addr_wr(struct mt76x0_dev *dev, const u32 offset, const u8 *addr);
 279
 280/* Init */
 281struct mt76x0_dev *mt76x0_alloc_device(struct device *dev);
 282int mt76x0_init_hardware(struct mt76x0_dev *dev);
 283int mt76x0_register_device(struct mt76x0_dev *dev);
 284void mt76x0_cleanup(struct mt76x0_dev *dev);
 285void mt76x0_chip_onoff(struct mt76x0_dev *dev, bool enable, bool reset);
 286
 287int mt76x0_mac_start(struct mt76x0_dev *dev);
 288void mt76x0_mac_stop(struct mt76x0_dev *dev);
 289
 290/* PHY */
 291void mt76x0_phy_init(struct mt76x0_dev *dev);
 292int mt76x0_wait_bbp_ready(struct mt76x0_dev *dev);
 293void mt76x0_agc_save(struct mt76x0_dev *dev);
 294void mt76x0_agc_restore(struct mt76x0_dev *dev);
 295int mt76x0_phy_set_channel(struct mt76x0_dev *dev,
 296                            struct cfg80211_chan_def *chandef);
 297void mt76x0_phy_recalibrate_after_assoc(struct mt76x0_dev *dev);
 298int mt76x0_phy_get_rssi(struct mt76x0_dev *dev, struct mt76x0_rxwi *rxwi);
 299void mt76x0_phy_con_cal_onoff(struct mt76x0_dev *dev,
 300                               struct ieee80211_bss_conf *info);
 301
 302/* MAC */
 303void mt76x0_mac_work(struct work_struct *work);
 304void mt76x0_mac_set_protection(struct mt76x0_dev *dev, bool legacy_prot,
 305                                int ht_mode);
 306void mt76x0_mac_set_short_preamble(struct mt76x0_dev *dev, bool short_preamb);
 307void mt76x0_mac_config_tsf(struct mt76x0_dev *dev, bool enable, int interval);
 308void
 309mt76x0_mac_wcid_setup(struct mt76x0_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
 310void mt76x0_mac_set_ampdu_factor(struct mt76x0_dev *dev);
 311
 312/* TX */
 313void mt76x0_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
 314                struct sk_buff *skb);
 315int mt76x0_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 316                    u16 queue, const struct ieee80211_tx_queue_params *params);
 317void mt76x0_tx_status(struct mt76x0_dev *dev, struct sk_buff *skb);
 318void mt76x0_tx_stat(struct work_struct *work);
 319
 320/* util */
 321void mt76x0_remove_hdr_pad(struct sk_buff *skb);
 322int mt76x0_insert_hdr_pad(struct sk_buff *skb);
 323
 324int mt76x0_dma_init(struct mt76x0_dev *dev);
 325void mt76x0_dma_cleanup(struct mt76x0_dev *dev);
 326
 327int mt76x0_dma_enqueue_tx(struct mt76x0_dev *dev, struct sk_buff *skb,
 328                           struct mt76_wcid *wcid, int hw_q);
 329
 330#endif
 331