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58#include <linux/clk.h>
59#include <linux/clk-provider.h>
60#include <linux/err.h>
61#include <linux/io.h>
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/of.h>
65#include <linux/of_device.h>
66#include <linux/platform_device.h>
67#include <linux/pwm.h>
68#include <linux/slab.h>
69#include <linux/spinlock.h>
70
71#define REG_PWM_A 0x0
72#define REG_PWM_B 0x4
73#define PWM_HIGH_SHIFT 16
74
75#define REG_MISC_AB 0x8
76#define MISC_B_CLK_EN BIT(23)
77#define MISC_A_CLK_EN BIT(15)
78#define MISC_CLK_DIV_MASK 0x7f
79#define MISC_B_CLK_DIV_SHIFT 16
80#define MISC_A_CLK_DIV_SHIFT 8
81#define MISC_B_CLK_SEL_SHIFT 6
82#define MISC_A_CLK_SEL_SHIFT 4
83#define MISC_CLK_SEL_WIDTH 2
84#define MISC_B_EN BIT(1)
85#define MISC_A_EN BIT(0)
86
87static const unsigned int mux_reg_shifts[] = {
88 MISC_A_CLK_SEL_SHIFT,
89 MISC_B_CLK_SEL_SHIFT
90};
91
92struct meson_pwm_channel {
93 unsigned int hi;
94 unsigned int lo;
95 u8 pre_div;
96
97 struct pwm_state state;
98
99 struct clk *clk_parent;
100 struct clk_mux mux;
101 struct clk *clk;
102};
103
104struct meson_pwm_data {
105 const char * const *parent_names;
106 unsigned int num_parents;
107};
108
109struct meson_pwm {
110 struct pwm_chip chip;
111 const struct meson_pwm_data *data;
112 void __iomem *base;
113 u8 inverter_mask;
114 spinlock_t lock;
115};
116
117static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
118{
119 return container_of(chip, struct meson_pwm, chip);
120}
121
122static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
123{
124 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
125 struct device *dev = chip->dev;
126 int err;
127
128 if (!channel)
129 return -ENODEV;
130
131 if (channel->clk_parent) {
132 err = clk_set_parent(channel->clk, channel->clk_parent);
133 if (err < 0) {
134 dev_err(dev, "failed to set parent %s for %s: %d\n",
135 __clk_get_name(channel->clk_parent),
136 __clk_get_name(channel->clk), err);
137 return err;
138 }
139 }
140
141 err = clk_prepare_enable(channel->clk);
142 if (err < 0) {
143 dev_err(dev, "failed to enable clock %s: %d\n",
144 __clk_get_name(channel->clk), err);
145 return err;
146 }
147
148 chip->ops->get_state(chip, pwm, &channel->state);
149
150 return 0;
151}
152
153static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
154{
155 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
156
157 if (channel)
158 clk_disable_unprepare(channel->clk);
159}
160
161static int meson_pwm_calc(struct meson_pwm *meson,
162 struct meson_pwm_channel *channel, unsigned int id,
163 unsigned int duty, unsigned int period)
164{
165 unsigned int pre_div, cnt, duty_cnt;
166 unsigned long fin_freq = -1;
167 u64 fin_ps;
168
169 if (~(meson->inverter_mask >> id) & 0x1)
170 duty = period - duty;
171
172 if (period == channel->state.period &&
173 duty == channel->state.duty_cycle)
174 return 0;
175
176 fin_freq = clk_get_rate(channel->clk);
177 if (fin_freq == 0) {
178 dev_err(meson->chip.dev, "invalid source clock frequency\n");
179 return -EINVAL;
180 }
181
182 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
183 fin_ps = (u64)NSEC_PER_SEC * 1000;
184 do_div(fin_ps, fin_freq);
185
186
187 for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
188 cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
189 fin_ps * (pre_div + 1));
190 dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
191 fin_ps, pre_div, cnt);
192 if (cnt <= 0xffff)
193 break;
194 }
195
196 if (pre_div == MISC_CLK_DIV_MASK) {
197 dev_err(meson->chip.dev, "unable to get period pre_div\n");
198 return -EINVAL;
199 }
200
201 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
202 pre_div, cnt);
203
204 if (duty == period) {
205 channel->pre_div = pre_div;
206 channel->hi = cnt;
207 channel->lo = 0;
208 } else if (duty == 0) {
209 channel->pre_div = pre_div;
210 channel->hi = 0;
211 channel->lo = cnt;
212 } else {
213
214 duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000,
215 fin_ps * (pre_div + 1));
216 if (duty_cnt > 0xffff) {
217 dev_err(meson->chip.dev, "unable to get duty cycle\n");
218 return -EINVAL;
219 }
220
221 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
222 duty, pre_div, duty_cnt);
223
224 channel->pre_div = pre_div;
225 channel->hi = duty_cnt;
226 channel->lo = cnt - duty_cnt;
227 }
228
229 return 0;
230}
231
232static void meson_pwm_enable(struct meson_pwm *meson,
233 struct meson_pwm_channel *channel,
234 unsigned int id)
235{
236 u32 value, clk_shift, clk_enable, enable;
237 unsigned int offset;
238
239 switch (id) {
240 case 0:
241 clk_shift = MISC_A_CLK_DIV_SHIFT;
242 clk_enable = MISC_A_CLK_EN;
243 enable = MISC_A_EN;
244 offset = REG_PWM_A;
245 break;
246
247 case 1:
248 clk_shift = MISC_B_CLK_DIV_SHIFT;
249 clk_enable = MISC_B_CLK_EN;
250 enable = MISC_B_EN;
251 offset = REG_PWM_B;
252 break;
253
254 default:
255 return;
256 }
257
258 value = readl(meson->base + REG_MISC_AB);
259 value &= ~(MISC_CLK_DIV_MASK << clk_shift);
260 value |= channel->pre_div << clk_shift;
261 value |= clk_enable;
262 writel(value, meson->base + REG_MISC_AB);
263
264 value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo;
265 writel(value, meson->base + offset);
266
267 value = readl(meson->base + REG_MISC_AB);
268 value |= enable;
269 writel(value, meson->base + REG_MISC_AB);
270}
271
272static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
273{
274 u32 value, enable;
275
276 switch (id) {
277 case 0:
278 enable = MISC_A_EN;
279 break;
280
281 case 1:
282 enable = MISC_B_EN;
283 break;
284
285 default:
286 return;
287 }
288
289 value = readl(meson->base + REG_MISC_AB);
290 value &= ~enable;
291 writel(value, meson->base + REG_MISC_AB);
292}
293
294static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
295 struct pwm_state *state)
296{
297 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
298 struct meson_pwm *meson = to_meson_pwm(chip);
299 unsigned long flags;
300 int err = 0;
301
302 if (!state)
303 return -EINVAL;
304
305 spin_lock_irqsave(&meson->lock, flags);
306
307 if (!state->enabled) {
308 meson_pwm_disable(meson, pwm->hwpwm);
309 channel->state.enabled = false;
310
311 goto unlock;
312 }
313
314 if (state->period != channel->state.period ||
315 state->duty_cycle != channel->state.duty_cycle ||
316 state->polarity != channel->state.polarity) {
317 if (channel->state.enabled) {
318 meson_pwm_disable(meson, pwm->hwpwm);
319 channel->state.enabled = false;
320 }
321
322 if (state->polarity != channel->state.polarity) {
323 if (state->polarity == PWM_POLARITY_NORMAL)
324 meson->inverter_mask |= BIT(pwm->hwpwm);
325 else
326 meson->inverter_mask &= ~BIT(pwm->hwpwm);
327 }
328
329 err = meson_pwm_calc(meson, channel, pwm->hwpwm,
330 state->duty_cycle, state->period);
331 if (err < 0)
332 goto unlock;
333
334 channel->state.polarity = state->polarity;
335 channel->state.period = state->period;
336 channel->state.duty_cycle = state->duty_cycle;
337 }
338
339 if (state->enabled && !channel->state.enabled) {
340 meson_pwm_enable(meson, channel, pwm->hwpwm);
341 channel->state.enabled = true;
342 }
343
344unlock:
345 spin_unlock_irqrestore(&meson->lock, flags);
346 return err;
347}
348
349static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
350 struct pwm_state *state)
351{
352 struct meson_pwm *meson = to_meson_pwm(chip);
353 u32 value, mask;
354
355 if (!state)
356 return;
357
358 switch (pwm->hwpwm) {
359 case 0:
360 mask = MISC_A_EN;
361 break;
362
363 case 1:
364 mask = MISC_B_EN;
365 break;
366
367 default:
368 return;
369 }
370
371 value = readl(meson->base + REG_MISC_AB);
372 state->enabled = (value & mask) != 0;
373}
374
375static const struct pwm_ops meson_pwm_ops = {
376 .request = meson_pwm_request,
377 .free = meson_pwm_free,
378 .apply = meson_pwm_apply,
379 .get_state = meson_pwm_get_state,
380 .owner = THIS_MODULE,
381};
382
383static const char * const pwm_meson8b_parent_names[] = {
384 "xtal", "vid_pll", "fclk_div4", "fclk_div3"
385};
386
387static const struct meson_pwm_data pwm_meson8b_data = {
388 .parent_names = pwm_meson8b_parent_names,
389 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
390};
391
392static const char * const pwm_gxbb_parent_names[] = {
393 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
394};
395
396static const struct meson_pwm_data pwm_gxbb_data = {
397 .parent_names = pwm_gxbb_parent_names,
398 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
399};
400
401
402
403
404
405static const char * const pwm_gxbb_ao_parent_names[] = {
406 "xtal", "clk81"
407};
408
409static const struct meson_pwm_data pwm_gxbb_ao_data = {
410 .parent_names = pwm_gxbb_ao_parent_names,
411 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
412};
413
414static const char * const pwm_axg_ee_parent_names[] = {
415 "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
416};
417
418static const struct meson_pwm_data pwm_axg_ee_data = {
419 .parent_names = pwm_axg_ee_parent_names,
420 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
421};
422
423static const char * const pwm_axg_ao_parent_names[] = {
424 "aoclk81", "xtal", "fclk_div4", "fclk_div5"
425};
426
427static const struct meson_pwm_data pwm_axg_ao_data = {
428 .parent_names = pwm_axg_ao_parent_names,
429 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
430};
431
432static const struct of_device_id meson_pwm_matches[] = {
433 {
434 .compatible = "amlogic,meson8b-pwm",
435 .data = &pwm_meson8b_data
436 },
437 {
438 .compatible = "amlogic,meson-gxbb-pwm",
439 .data = &pwm_gxbb_data
440 },
441 {
442 .compatible = "amlogic,meson-gxbb-ao-pwm",
443 .data = &pwm_gxbb_ao_data
444 },
445 {
446 .compatible = "amlogic,meson-axg-ee-pwm",
447 .data = &pwm_axg_ee_data
448 },
449 {
450 .compatible = "amlogic,meson-axg-ao-pwm",
451 .data = &pwm_axg_ao_data
452 },
453 {},
454};
455MODULE_DEVICE_TABLE(of, meson_pwm_matches);
456
457static int meson_pwm_init_channels(struct meson_pwm *meson,
458 struct meson_pwm_channel *channels)
459{
460 struct device *dev = meson->chip.dev;
461 struct clk_init_data init;
462 unsigned int i;
463 char name[255];
464 int err;
465
466 for (i = 0; i < meson->chip.npwm; i++) {
467 struct meson_pwm_channel *channel = &channels[i];
468
469 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
470
471 init.name = name;
472 init.ops = &clk_mux_ops;
473 init.flags = CLK_IS_BASIC;
474 init.parent_names = meson->data->parent_names;
475 init.num_parents = meson->data->num_parents;
476
477 channel->mux.reg = meson->base + REG_MISC_AB;
478 channel->mux.shift = mux_reg_shifts[i];
479 channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
480 channel->mux.flags = 0;
481 channel->mux.lock = &meson->lock;
482 channel->mux.table = NULL;
483 channel->mux.hw.init = &init;
484
485 channel->clk = devm_clk_register(dev, &channel->mux.hw);
486 if (IS_ERR(channel->clk)) {
487 err = PTR_ERR(channel->clk);
488 dev_err(dev, "failed to register %s: %d\n", name, err);
489 return err;
490 }
491
492 snprintf(name, sizeof(name), "clkin%u", i);
493
494 channel->clk_parent = devm_clk_get(dev, name);
495 if (IS_ERR(channel->clk_parent)) {
496 err = PTR_ERR(channel->clk_parent);
497 if (err == -EPROBE_DEFER)
498 return err;
499
500 channel->clk_parent = NULL;
501 }
502 }
503
504 return 0;
505}
506
507static void meson_pwm_add_channels(struct meson_pwm *meson,
508 struct meson_pwm_channel *channels)
509{
510 unsigned int i;
511
512 for (i = 0; i < meson->chip.npwm; i++)
513 pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
514}
515
516static int meson_pwm_probe(struct platform_device *pdev)
517{
518 struct meson_pwm_channel *channels;
519 struct meson_pwm *meson;
520 struct resource *regs;
521 int err;
522
523 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
524 if (!meson)
525 return -ENOMEM;
526
527 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
528 meson->base = devm_ioremap_resource(&pdev->dev, regs);
529 if (IS_ERR(meson->base))
530 return PTR_ERR(meson->base);
531
532 spin_lock_init(&meson->lock);
533 meson->chip.dev = &pdev->dev;
534 meson->chip.ops = &meson_pwm_ops;
535 meson->chip.base = -1;
536 meson->chip.npwm = 2;
537 meson->chip.of_xlate = of_pwm_xlate_with_flags;
538 meson->chip.of_pwm_n_cells = 3;
539
540 meson->data = of_device_get_match_data(&pdev->dev);
541 meson->inverter_mask = BIT(meson->chip.npwm) - 1;
542
543 channels = devm_kcalloc(&pdev->dev, meson->chip.npwm,
544 sizeof(*channels), GFP_KERNEL);
545 if (!channels)
546 return -ENOMEM;
547
548 err = meson_pwm_init_channels(meson, channels);
549 if (err < 0)
550 return err;
551
552 err = pwmchip_add(&meson->chip);
553 if (err < 0) {
554 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
555 return err;
556 }
557
558 meson_pwm_add_channels(meson, channels);
559
560 platform_set_drvdata(pdev, meson);
561
562 return 0;
563}
564
565static int meson_pwm_remove(struct platform_device *pdev)
566{
567 struct meson_pwm *meson = platform_get_drvdata(pdev);
568
569 return pwmchip_remove(&meson->chip);
570}
571
572static struct platform_driver meson_pwm_driver = {
573 .driver = {
574 .name = "meson-pwm",
575 .of_match_table = meson_pwm_matches,
576 },
577 .probe = meson_pwm_probe,
578 .remove = meson_pwm_remove,
579};
580module_platform_driver(meson_pwm_driver);
581
582MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
583MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
584MODULE_LICENSE("Dual BSD/GPL");
585
