LXR linux/drivers/scsi/bfa/bfa_hw

   1/*
   2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
   3 * Copyright (c) 2014- QLogic Corporation.
   4 * All rights reserved
   5 * www.qlogic.com
   6 *
   7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms of the GNU General Public License (GPL) Version 2 as
  11 * published by the Free Software Foundation
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 * General Public License for more details.
  17 */
  18
  19#include "bfad_drv.h"
  20#include "bfa_modules.h"
  21#include "bfi_reg.h"
  22
  23BFA_TRC_FILE(HAL, IOCFC_CT);
  24
  25/*
  26 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
  27 */
  28static void
  29bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
  30{
  31}
  32
  33void
  34bfa_hwct_reginit(struct bfa_s *bfa)
  35{
  36        struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  37        void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
  38        int     fn = bfa_ioc_pcifn(&bfa->ioc);
  39
  40        if (fn == 0) {
  41                bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
  42                bfa_regs->intr_mask   = (kva + HOSTFN0_INT_MSK);
  43        } else {
  44                bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
  45                bfa_regs->intr_mask   = (kva + HOSTFN1_INT_MSK);
  46        }
  47}
  48
  49void
  50bfa_hwct2_reginit(struct bfa_s *bfa)
  51{
  52        struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  53        void __iomem    *kva = bfa_ioc_bar0(&bfa->ioc);
  54
  55        bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
  56        bfa_regs->intr_mask   = (kva + CT2_HOSTFN_INTR_MASK);
  57}
  58
  59void
  60bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
  61{
  62        u32     r32;
  63
  64        r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
  65        writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
  66}
  67
  68/*
  69 * Actions to respond RME Interrupt for Catapult ASIC:
  70 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
  71 * - Acknowledge by writing to RME Queue Control register
  72 * - Update CI
  73 */
  74void
  75bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
  76{
  77        u32     r32;
  78
  79        r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
  80        writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
  81
  82        bfa_rspq_ci(bfa, rspq) = ci;
  83        writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
  84        mmiowb();
  85}
  86
  87/*
  88 * Actions to respond RME Interrupt for Catapult2 ASIC:
  89 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
  90 * - Update CI
  91 */
  92void
  93bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
  94{
  95        bfa_rspq_ci(bfa, rspq) = ci;
  96        writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
  97        mmiowb();
  98}
  99
 100void
 101bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
 102                 u32 *num_vecs, u32 *max_vec_bit)
 103{
 104        *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
 105        *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
 106        *num_vecs = BFI_MSIX_CT_MAX;
 107}
 108
 109/*
 110 * Setup MSI-X vector for catapult
 111 */
 112void
 113bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
 114{
 115        WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
 116        bfa_trc(bfa, nvecs);
 117
 118        bfa->msix.nvecs = nvecs;
 119        bfa_hwct_msix_uninstall(bfa);
 120}
 121
 122void
 123bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
 124{
 125        if (bfa->msix.nvecs == 0)
 126                return;
 127
 128        if (bfa->msix.nvecs == 1)
 129                bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
 130        else
 131                bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
 132}
 133
 134void
 135bfa_hwct_msix_queue_install(struct bfa_s *bfa)
 136{
 137        int i;
 138
 139        if (bfa->msix.nvecs == 0)
 140                return;
 141
 142        if (bfa->msix.nvecs == 1) {
 143                for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
 144                        bfa->msix.handler[i] = bfa_msix_all;
 145                return;
 146        }
 147
 148        for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
 149                bfa->msix.handler[i] = bfa_msix_reqq;
 150
 151        for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
 152                bfa->msix.handler[i] = bfa_msix_rspq;
 153}
 154
 155void
 156bfa_hwct_msix_uninstall(struct bfa_s *bfa)
 157{
 158        int i;
 159
 160        for (i = 0; i < BFI_MSIX_CT_MAX; i++)
 161                bfa->msix.handler[i] = bfa_hwct_msix_dummy;
 162}
 163
 164/*
 165 * Enable MSI-X vectors
 166 */
 167void
 168bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
 169{
 170        bfa_trc(bfa, 0);
 171        bfa_ioc_isr_mode_set(&bfa->ioc, msix);
 172}
 173
 174void
 175bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
 176{
 177        *start = BFI_MSIX_RME_QMIN_CT;
 178        *end = BFI_MSIX_RME_QMAX_CT;
 179}
 180