1
2
3
4
5
6
7
8#include <asm/cacheflush.h>
9#include <linux/io.h>
10#include <linux/slab.h>
11#include <soc/fsl/dpaa2-global.h>
12
13#include "qbman-portal.h"
14
15#define QMAN_REV_4000 0x04000000
16#define QMAN_REV_4100 0x04010000
17#define QMAN_REV_4101 0x04010001
18#define QMAN_REV_MASK 0xffff0000
19
20
21#define QB_VALID_BIT ((u32)0x80)
22
23
24#define QBMAN_MC_ACQUIRE 0x30
25#define QBMAN_WQCHAN_CONFIGURE 0x46
26
27
28#define QBMAN_CINH_SWP_EQAR 0x8c0
29#define QBMAN_CINH_SWP_DQPI 0xa00
30#define QBMAN_CINH_SWP_DCAP 0xac0
31#define QBMAN_CINH_SWP_SDQCR 0xb00
32#define QBMAN_CINH_SWP_RAR 0xcc0
33#define QBMAN_CINH_SWP_ISR 0xe00
34#define QBMAN_CINH_SWP_IER 0xe40
35#define QBMAN_CINH_SWP_ISDR 0xe80
36#define QBMAN_CINH_SWP_IIR 0xec0
37
38
39#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6))
40#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((u32)(n) << 6))
41#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((u32)(n) << 6))
42#define QBMAN_CENA_SWP_CR 0x600
43#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((u32)(vb) >> 1))
44#define QBMAN_CENA_SWP_VDQCR 0x780
45
46
47#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)(p) & 0x1ff) >> 6)
48
49
50#define QMAN_DQ_TOKEN_VALID 1
51
52
53#define QB_SDQCR_FC_SHIFT 29
54#define QB_SDQCR_FC_MASK 0x1
55#define QB_SDQCR_DCT_SHIFT 24
56#define QB_SDQCR_DCT_MASK 0x3
57#define QB_SDQCR_TOK_SHIFT 16
58#define QB_SDQCR_TOK_MASK 0xff
59#define QB_SDQCR_SRC_SHIFT 0
60#define QB_SDQCR_SRC_MASK 0xffff
61
62
63#define QMAN_SDQCR_TOKEN 0xbb
64
65enum qbman_sdqcr_dct {
66 qbman_sdqcr_dct_null = 0,
67 qbman_sdqcr_dct_prio_ics,
68 qbman_sdqcr_dct_active_ics,
69 qbman_sdqcr_dct_active
70};
71
72enum qbman_sdqcr_fc {
73 qbman_sdqcr_fc_one = 0,
74 qbman_sdqcr_fc_up_to_3 = 1
75};
76
77
78
79static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
80{
81 return readl_relaxed(p->addr_cinh + offset);
82}
83
84static inline void qbman_write_register(struct qbman_swp *p, u32 offset,
85 u32 value)
86{
87 writel_relaxed(value, p->addr_cinh + offset);
88}
89
90static inline void *qbman_get_cmd(struct qbman_swp *p, u32 offset)
91{
92 return p->addr_cena + offset;
93}
94
95#define QBMAN_CINH_SWP_CFG 0xd00
96
97#define SWP_CFG_DQRR_MF_SHIFT 20
98#define SWP_CFG_EST_SHIFT 16
99#define SWP_CFG_WN_SHIFT 14
100#define SWP_CFG_RPM_SHIFT 12
101#define SWP_CFG_DCM_SHIFT 10
102#define SWP_CFG_EPM_SHIFT 8
103#define SWP_CFG_SD_SHIFT 5
104#define SWP_CFG_SP_SHIFT 4
105#define SWP_CFG_SE_SHIFT 3
106#define SWP_CFG_DP_SHIFT 2
107#define SWP_CFG_DE_SHIFT 1
108#define SWP_CFG_EP_SHIFT 0
109
110static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn, u8 est, u8 rpm, u8 dcm,
111 u8 epm, int sd, int sp, int se,
112 int dp, int de, int ep)
113{
114 return (max_fill << SWP_CFG_DQRR_MF_SHIFT |
115 est << SWP_CFG_EST_SHIFT |
116 wn << SWP_CFG_WN_SHIFT |
117 rpm << SWP_CFG_RPM_SHIFT |
118 dcm << SWP_CFG_DCM_SHIFT |
119 epm << SWP_CFG_EPM_SHIFT |
120 sd << SWP_CFG_SD_SHIFT |
121 sp << SWP_CFG_SP_SHIFT |
122 se << SWP_CFG_SE_SHIFT |
123 dp << SWP_CFG_DP_SHIFT |
124 de << SWP_CFG_DE_SHIFT |
125 ep << SWP_CFG_EP_SHIFT);
126}
127
128
129
130
131
132
133
134
135
136struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
137{
138 struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
139 u32 reg;
140
141 if (!p)
142 return NULL;
143 p->desc = d;
144 p->mc.valid_bit = QB_VALID_BIT;
145 p->sdq = 0;
146 p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
147 p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
148 p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
149
150 atomic_set(&p->vdq.available, 1);
151 p->vdq.valid_bit = QB_VALID_BIT;
152 p->dqrr.next_idx = 0;
153 p->dqrr.valid_bit = QB_VALID_BIT;
154
155 if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_4100) {
156 p->dqrr.dqrr_size = 4;
157 p->dqrr.reset_bug = 1;
158 } else {
159 p->dqrr.dqrr_size = 8;
160 p->dqrr.reset_bug = 0;
161 }
162
163 p->addr_cena = d->cena_bar;
164 p->addr_cinh = d->cinh_bar;
165
166 reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
167 1,
168 0,
169 3,
170 2,
171 3,
172 0,
173 1,
174 0,
175 1,
176 0,
177 0);
178
179 qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
180 reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
181 if (!reg) {
182 pr_err("qbman: the portal is not enabled!\n");
183 return NULL;
184 }
185
186
187
188
189
190
191
192 qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
193 return p;
194}
195
196
197
198
199
200
201void qbman_swp_finish(struct qbman_swp *p)
202{
203 kfree(p);
204}
205
206
207
208
209
210
211
212u32 qbman_swp_interrupt_read_status(struct qbman_swp *p)
213{
214 return qbman_read_register(p, QBMAN_CINH_SWP_ISR);
215}
216
217
218
219
220
221
222void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask)
223{
224 qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask);
225}
226
227
228
229
230
231
232
233u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
234{
235 return qbman_read_register(p, QBMAN_CINH_SWP_IER);
236}
237
238
239
240
241
242
243void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask)
244{
245 qbman_write_register(p, QBMAN_CINH_SWP_IER, mask);
246}
247
248
249
250
251
252
253
254int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
255{
256 return qbman_read_register(p, QBMAN_CINH_SWP_IIR);
257}
258
259
260
261
262
263
264void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
265{
266 qbman_write_register(p, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
267}
268
269
270
271
272
273
274
275
276
277
278void *qbman_swp_mc_start(struct qbman_swp *p)
279{
280 return qbman_get_cmd(p, QBMAN_CENA_SWP_CR);
281}
282
283
284
285
286
287void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb)
288{
289 u8 *v = cmd;
290
291 dma_wmb();
292 *v = cmd_verb | p->mc.valid_bit;
293}
294
295
296
297
298
299void *qbman_swp_mc_result(struct qbman_swp *p)
300{
301 u32 *ret, verb;
302
303 ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
304
305
306 verb = ret[0] & ~QB_VALID_BIT;
307 if (!verb)
308 return NULL;
309 p->mc.valid_bit ^= QB_VALID_BIT;
310 return ret;
311}
312
313#define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
314enum qb_enqueue_commands {
315 enqueue_empty = 0,
316 enqueue_response_always = 1,
317 enqueue_rejects_to_fq = 2
318};
319
320#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
321#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
322#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
323
324
325
326
327
328void qbman_eq_desc_clear(struct qbman_eq_desc *d)
329{
330 memset(d, 0, sizeof(*d));
331}
332
333
334
335
336
337
338
339void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
340{
341 d->verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
342 if (respond_success)
343 d->verb |= enqueue_response_always;
344 else
345 d->verb |= enqueue_rejects_to_fq;
346}
347
348
349
350
351
352
353
354
355
356
357
358
359
360void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid)
361{
362 d->verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
363 d->tgtid = cpu_to_le32(fqid);
364}
365
366
367
368
369
370
371
372
373void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
374 u32 qd_bin, u32 qd_prio)
375{
376 d->verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
377 d->tgtid = cpu_to_le32(qdid);
378 d->qdbin = cpu_to_le16(qd_bin);
379 d->qpri = qd_prio;
380}
381
382#define EQAR_IDX(eqar) ((eqar) & 0x7)
383#define EQAR_VB(eqar) ((eqar) & 0x80)
384#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
385
386
387
388
389
390
391
392
393
394
395
396
397int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
398 const struct dpaa2_fd *fd)
399{
400 struct qbman_eq_desc *p;
401 u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
402
403 if (!EQAR_SUCCESS(eqar))
404 return -EBUSY;
405
406 p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
407 memcpy(&p->dca, &d->dca, 31);
408 memcpy(&p->fd, fd, sizeof(*fd));
409
410
411 dma_wmb();
412 p->verb = d->verb | EQAR_VB(eqar);
413
414 return 0;
415}
416
417
418
419
420
421
422
423
424
425
426void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled)
427{
428 u16 src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
429
430 WARN_ON(channel_idx > 15);
431 *enabled = src | (1 << channel_idx);
432}
433
434
435
436
437
438
439
440void qbman_swp_push_set(struct qbman_swp *s, u8 channel_idx, int enable)
441{
442 u16 dqsrc;
443
444 WARN_ON(channel_idx > 15);
445 if (enable)
446 s->sdq |= 1 << channel_idx;
447 else
448 s->sdq &= ~(1 << channel_idx);
449
450
451
452
453 dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
454 if (dqsrc != 0)
455 qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, s->sdq);
456 else
457 qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, 0);
458}
459
460#define QB_VDQCR_VERB_DCT_SHIFT 0
461#define QB_VDQCR_VERB_DT_SHIFT 2
462#define QB_VDQCR_VERB_RLS_SHIFT 4
463#define QB_VDQCR_VERB_WAE_SHIFT 5
464
465enum qb_pull_dt_e {
466 qb_pull_dt_channel,
467 qb_pull_dt_workqueue,
468 qb_pull_dt_framequeue
469};
470
471
472
473
474
475
476void qbman_pull_desc_clear(struct qbman_pull_desc *d)
477{
478 memset(d, 0, sizeof(*d));
479}
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
495 struct dpaa2_dq *storage,
496 dma_addr_t storage_phys,
497 int stash)
498{
499
500 d->rsp_addr_virt = (u64)(uintptr_t)storage;
501
502 if (!storage) {
503 d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
504 return;
505 }
506 d->verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
507 if (stash)
508 d->verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
509 else
510 d->verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
511
512 d->rsp_addr = cpu_to_le64(storage_phys);
513}
514
515
516
517
518
519
520void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes)
521{
522 d->numf = numframes - 1;
523}
524
525
526
527
528
529
530
531
532
533
534
535
536
537void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid)
538{
539 d->verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
540 d->verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
541 d->dq_src = cpu_to_le32(fqid);
542}
543
544
545
546
547
548
549void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
550 enum qbman_pull_type_e dct)
551{
552 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
553 d->verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
554 d->dq_src = cpu_to_le32(wqid);
555}
556
557
558
559
560
561
562
563void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
564 enum qbman_pull_type_e dct)
565{
566 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
567 d->verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
568 d->dq_src = cpu_to_le32(chid);
569}
570
571
572
573
574
575
576
577
578
579
580int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
581{
582 struct qbman_pull_desc *p;
583
584 if (!atomic_dec_and_test(&s->vdq.available)) {
585 atomic_inc(&s->vdq.available);
586 return -EBUSY;
587 }
588 s->vdq.storage = (void *)(uintptr_t)d->rsp_addr_virt;
589 p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
590 p->numf = d->numf;
591 p->tok = QMAN_DQ_TOKEN_VALID;
592 p->dq_src = d->dq_src;
593 p->rsp_addr = d->rsp_addr;
594 p->rsp_addr_virt = d->rsp_addr_virt;
595 dma_wmb();
596
597
598 p->verb = d->verb | s->vdq.valid_bit;
599 s->vdq.valid_bit ^= QB_VALID_BIT;
600
601 return 0;
602}
603
604#define QMAN_DQRR_PI_MASK 0xf
605
606
607
608
609
610
611
612
613
614const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
615{
616 u32 verb;
617 u32 response_verb;
618 u32 flags;
619 struct dpaa2_dq *p;
620
621
622
623
624 if (unlikely(s->dqrr.reset_bug)) {
625
626
627
628
629
630
631
632
633 u8 pi = qbman_read_register(s, QBMAN_CINH_SWP_DQPI) &
634 QMAN_DQRR_PI_MASK;
635
636
637 if (pi == s->dqrr.next_idx)
638 return NULL;
639
640
641
642
643
644
645
646
647
648 if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
649 pr_debug("next_idx=%d, pi=%d, clear reset bug\n",
650 s->dqrr.next_idx, pi);
651 s->dqrr.reset_bug = 0;
652 }
653 prefetch(qbman_get_cmd(s,
654 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
655 }
656
657 p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
658 verb = p->dq.verb;
659
660
661
662
663
664
665
666
667
668 if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
669 prefetch(qbman_get_cmd(s,
670 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
671 return NULL;
672 }
673
674
675
676
677 s->dqrr.next_idx++;
678 s->dqrr.next_idx &= s->dqrr.dqrr_size - 1;
679 if (!s->dqrr.next_idx)
680 s->dqrr.valid_bit ^= QB_VALID_BIT;
681
682
683
684
685
686 flags = p->dq.stat;
687 response_verb = verb & QBMAN_RESULT_MASK;
688 if ((response_verb == QBMAN_RESULT_DQ) &&
689 (flags & DPAA2_DQ_STAT_VOLATILE) &&
690 (flags & DPAA2_DQ_STAT_EXPIRED))
691 atomic_inc(&s->vdq.available);
692
693 prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
694
695 return p;
696}
697
698
699
700
701
702
703
704void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq)
705{
706 qbman_write_register(s, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
707}
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq)
727{
728 if (dq->dq.tok != QMAN_DQ_TOKEN_VALID)
729 return 0;
730
731
732
733
734
735
736 ((struct dpaa2_dq *)dq)->dq.tok = 0;
737
738
739
740
741
742
743 if (s->vdq.storage == dq) {
744 s->vdq.storage = NULL;
745 atomic_inc(&s->vdq.available);
746 }
747
748 return 1;
749}
750
751
752
753
754
755void qbman_release_desc_clear(struct qbman_release_desc *d)
756{
757 memset(d, 0, sizeof(*d));
758 d->verb = 1 << 5;
759}
760
761
762
763
764void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid)
765{
766 d->bpid = cpu_to_le16(bpid);
767}
768
769
770
771
772
773void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
774{
775 if (enable)
776 d->verb |= 1 << 6;
777 else
778 d->verb &= ~(1 << 6);
779}
780
781#define RAR_IDX(rar) ((rar) & 0x7)
782#define RAR_VB(rar) ((rar) & 0x80)
783#define RAR_SUCCESS(rar) ((rar) & 0x100)
784
785
786
787
788
789
790
791
792
793
794int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
795 const u64 *buffers, unsigned int num_buffers)
796{
797 int i;
798 struct qbman_release_desc *p;
799 u32 rar;
800
801 if (!num_buffers || (num_buffers > 7))
802 return -EINVAL;
803
804 rar = qbman_read_register(s, QBMAN_CINH_SWP_RAR);
805 if (!RAR_SUCCESS(rar))
806 return -EBUSY;
807
808
809 p = qbman_get_cmd(s, QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
810
811 for (i = 0; i < num_buffers; i++)
812 p->buf[i] = cpu_to_le64(buffers[i]);
813 p->bpid = d->bpid;
814
815
816
817
818
819 dma_wmb();
820 p->verb = d->verb | RAR_VB(rar) | num_buffers;
821
822 return 0;
823}
824
825struct qbman_acquire_desc {
826 u8 verb;
827 u8 reserved;
828 __le16 bpid;
829 u8 num;
830 u8 reserved2[59];
831};
832
833struct qbman_acquire_rslt {
834 u8 verb;
835 u8 rslt;
836 __le16 reserved;
837 u8 num;
838 u8 reserved2[3];
839 __le64 buf[7];
840};
841
842
843
844
845
846
847
848
849
850
851
852int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
853 unsigned int num_buffers)
854{
855 struct qbman_acquire_desc *p;
856 struct qbman_acquire_rslt *r;
857 int i;
858
859 if (!num_buffers || (num_buffers > 7))
860 return -EINVAL;
861
862
863 p = qbman_swp_mc_start(s);
864
865 if (!p)
866 return -EBUSY;
867
868
869 p->bpid = cpu_to_le16(bpid);
870 p->num = num_buffers;
871
872
873 r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
874 if (unlikely(!r)) {
875 pr_err("qbman: acquire from BPID %d failed, no response\n",
876 bpid);
877 return -EIO;
878 }
879
880
881 WARN_ON((r->verb & 0x7f) != QBMAN_MC_ACQUIRE);
882
883
884 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
885 pr_err("qbman: acquire from BPID 0x%x failed, code=0x%02x\n",
886 bpid, r->rslt);
887 return -EIO;
888 }
889
890 WARN_ON(r->num > num_buffers);
891
892
893 for (i = 0; i < r->num; i++)
894 buffers[i] = le64_to_cpu(r->buf[i]);
895
896 return (int)r->num;
897}
898
899struct qbman_alt_fq_state_desc {
900 u8 verb;
901 u8 reserved[3];
902 __le32 fqid;
903 u8 reserved2[56];
904};
905
906struct qbman_alt_fq_state_rslt {
907 u8 verb;
908 u8 rslt;
909 u8 reserved[62];
910};
911
912#define ALT_FQ_FQID_MASK 0x00FFFFFF
913
914int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
915 u8 alt_fq_verb)
916{
917 struct qbman_alt_fq_state_desc *p;
918 struct qbman_alt_fq_state_rslt *r;
919
920
921 p = qbman_swp_mc_start(s);
922 if (!p)
923 return -EBUSY;
924
925 p->fqid = cpu_to_le32(fqid & ALT_FQ_FQID_MASK);
926
927
928 r = qbman_swp_mc_complete(s, p, alt_fq_verb);
929 if (unlikely(!r)) {
930 pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
931 alt_fq_verb);
932 return -EIO;
933 }
934
935
936 WARN_ON((r->verb & QBMAN_RESULT_MASK) != alt_fq_verb);
937
938
939 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
940 pr_err("qbman: ALT FQID %d failed: verb = 0x%08x code = 0x%02x\n",
941 fqid, r->verb, r->rslt);
942 return -EIO;
943 }
944
945 return 0;
946}
947
948struct qbman_cdan_ctrl_desc {
949 u8 verb;
950 u8 reserved;
951 __le16 ch;
952 u8 we;
953 u8 ctrl;
954 __le16 reserved2;
955 __le64 cdan_ctx;
956 u8 reserved3[48];
957
958};
959
960struct qbman_cdan_ctrl_rslt {
961 u8 verb;
962 u8 rslt;
963 __le16 ch;
964 u8 reserved[60];
965};
966
967int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
968 u8 we_mask, u8 cdan_en,
969 u64 ctx)
970{
971 struct qbman_cdan_ctrl_desc *p = NULL;
972 struct qbman_cdan_ctrl_rslt *r = NULL;
973
974
975 p = qbman_swp_mc_start(s);
976 if (!p)
977 return -EBUSY;
978
979
980 p->ch = cpu_to_le16(channelid);
981 p->we = we_mask;
982 if (cdan_en)
983 p->ctrl = 1;
984 else
985 p->ctrl = 0;
986 p->cdan_ctx = cpu_to_le64(ctx);
987
988
989 r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
990 if (unlikely(!r)) {
991 pr_err("qbman: wqchan config failed, no response\n");
992 return -EIO;
993 }
994
995 WARN_ON((r->verb & 0x7f) != QBMAN_WQCHAN_CONFIGURE);
996
997
998 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
999 pr_err("qbman: CDAN cQID %d failed: code = 0x%02x\n",
1000 channelid, r->rslt);
1001 return -EIO;
1002 }
1003
1004 return 0;
1005}
1006