1
2
3
4
5
6
7
8
9
10
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22#include <linux/of_device.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30#include "nau8540.h"
31
32
33#define NAU_FREF_MAX 13500000
34#define NAU_FVCO_MAX 100000000
35#define NAU_FVCO_MIN 90000000
36
37
38#define CLK_ADC_MAX 6144000
39
40
41static const struct nau8540_fll_attr mclk_src_scaling[] = {
42 { 1, 0x0 },
43 { 2, 0x2 },
44 { 4, 0x3 },
45 { 8, 0x4 },
46 { 16, 0x5 },
47 { 32, 0x6 },
48 { 3, 0x7 },
49 { 6, 0xa },
50 { 12, 0xb },
51 { 24, 0xc },
52};
53
54
55static const struct nau8540_fll_attr fll_ratio[] = {
56 { 512000, 0x01 },
57 { 256000, 0x02 },
58 { 128000, 0x04 },
59 { 64000, 0x08 },
60 { 32000, 0x10 },
61 { 8000, 0x20 },
62 { 4000, 0x40 },
63};
64
65static const struct nau8540_fll_attr fll_pre_scalar[] = {
66 { 1, 0x0 },
67 { 2, 0x1 },
68 { 4, 0x2 },
69 { 8, 0x3 },
70};
71
72
73static const struct nau8540_osr_attr osr_adc_sel[] = {
74 { 32, 3 },
75 { 64, 2 },
76 { 128, 1 },
77 { 256, 0 },
78};
79
80static const struct reg_default nau8540_reg_defaults[] = {
81 {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
82 {NAU8540_REG_CLOCK_CTRL, 0x0000},
83 {NAU8540_REG_CLOCK_SRC, 0x0000},
84 {NAU8540_REG_FLL1, 0x0001},
85 {NAU8540_REG_FLL2, 0x3126},
86 {NAU8540_REG_FLL3, 0x0008},
87 {NAU8540_REG_FLL4, 0x0010},
88 {NAU8540_REG_FLL5, 0xC000},
89 {NAU8540_REG_FLL6, 0x6000},
90 {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
91 {NAU8540_REG_PCM_CTRL0, 0x000B},
92 {NAU8540_REG_PCM_CTRL1, 0x3010},
93 {NAU8540_REG_PCM_CTRL2, 0x0800},
94 {NAU8540_REG_PCM_CTRL3, 0x0000},
95 {NAU8540_REG_PCM_CTRL4, 0x000F},
96 {NAU8540_REG_ALC_CONTROL_1, 0x0000},
97 {NAU8540_REG_ALC_CONTROL_2, 0x700B},
98 {NAU8540_REG_ALC_CONTROL_3, 0x0022},
99 {NAU8540_REG_ALC_CONTROL_4, 0x1010},
100 {NAU8540_REG_ALC_CONTROL_5, 0x1010},
101 {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
102 {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
103 {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
104 {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
105 {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
106 {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
107 {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
108 {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
109 {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
110 {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
111 {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
112 {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
113 {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
114 {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
115 {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
116 {NAU8540_REG_DIGITAL_MUX, 0x00E4},
117 {NAU8540_REG_GPIO_CTRL, 0x0000},
118 {NAU8540_REG_MISC_CTRL, 0x0000},
119 {NAU8540_REG_I2C_CTRL, 0xEFFF},
120 {NAU8540_REG_VMID_CTRL, 0x0000},
121 {NAU8540_REG_MUTE, 0x0000},
122 {NAU8540_REG_ANALOG_ADC1, 0x0011},
123 {NAU8540_REG_ANALOG_ADC2, 0x0020},
124 {NAU8540_REG_ANALOG_PWR, 0x0000},
125 {NAU8540_REG_MIC_BIAS, 0x0004},
126 {NAU8540_REG_REFERENCE, 0x0000},
127 {NAU8540_REG_FEPGA1, 0x0000},
128 {NAU8540_REG_FEPGA2, 0x0000},
129 {NAU8540_REG_FEPGA3, 0x0101},
130 {NAU8540_REG_FEPGA4, 0x0101},
131 {NAU8540_REG_PWR, 0x0000},
132};
133
134static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
135{
136 switch (reg) {
137 case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
138 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
139 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
140 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
141 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
142 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
143 case NAU8540_REG_I2C_DEVICE_ID:
144 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
145 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
146 return true;
147 default:
148 return false;
149 }
150
151}
152
153static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
154{
155 switch (reg) {
156 case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
157 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
158 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
159 case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
160 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
161 case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
162 case NAU8540_REG_RST:
163 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
164 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
165 return true;
166 default:
167 return false;
168 }
169}
170
171static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
172{
173 switch (reg) {
174 case NAU8540_REG_SW_RESET:
175 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
176 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
177 case NAU8540_REG_I2C_DEVICE_ID:
178 case NAU8540_REG_RST:
179 return true;
180 default:
181 return false;
182 }
183}
184
185
186static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
187static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
188
189static const struct snd_kcontrol_new nau8540_snd_controls[] = {
190 SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
191 0, 0x520, 0, adc_vol_tlv),
192 SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
193 0, 0x520, 0, adc_vol_tlv),
194 SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
195 0, 0x520, 0, adc_vol_tlv),
196 SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
197 0, 0x520, 0, adc_vol_tlv),
198
199 SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
200 0, 0x25, 0, fepga_gain_tlv),
201 SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
202 8, 0x25, 0, fepga_gain_tlv),
203 SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
204 0, 0x25, 0, fepga_gain_tlv),
205 SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
206 8, 0x25, 0, fepga_gain_tlv),
207};
208
209static const char * const adc_channel[] = {
210 "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
211};
212static SOC_ENUM_SINGLE_DECL(
213 digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
214
215static const struct snd_kcontrol_new digital_ch4_mux =
216 SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
217
218static SOC_ENUM_SINGLE_DECL(
219 digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
220
221static const struct snd_kcontrol_new digital_ch3_mux =
222 SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
223
224static SOC_ENUM_SINGLE_DECL(
225 digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
226
227static const struct snd_kcontrol_new digital_ch2_mux =
228 SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
229
230static SOC_ENUM_SINGLE_DECL(
231 digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
232
233static const struct snd_kcontrol_new digital_ch1_mux =
234 SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
235
236static int adc_power_control(struct snd_soc_dapm_widget *w,
237 struct snd_kcontrol *k, int event)
238{
239 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
240 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
241
242 if (SND_SOC_DAPM_EVENT_ON(event)) {
243 msleep(300);
244
245 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
246 NAU8540_I2S_DO12_TRI, 0);
247 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
248 NAU8540_I2S_DO34_TRI, 0);
249 } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
250 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
251 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
252 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
253 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
254 }
255 return 0;
256}
257
258static int aiftx_power_control(struct snd_soc_dapm_widget *w,
259 struct snd_kcontrol *k, int event)
260{
261 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
262 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
263
264 if (SND_SOC_DAPM_EVENT_OFF(event)) {
265 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
266 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
267 }
268 return 0;
269}
270
271static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
272 SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
273 SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
274
275 SND_SOC_DAPM_INPUT("MIC1"),
276 SND_SOC_DAPM_INPUT("MIC2"),
277 SND_SOC_DAPM_INPUT("MIC3"),
278 SND_SOC_DAPM_INPUT("MIC4"),
279
280 SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
281 SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
282 SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
283 SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
284
285 SND_SOC_DAPM_ADC_E("ADC1", NULL,
286 NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
287 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
288 SND_SOC_DAPM_ADC_E("ADC2", NULL,
289 NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
290 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
291 SND_SOC_DAPM_ADC_E("ADC3", NULL,
292 NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
293 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
294 SND_SOC_DAPM_ADC_E("ADC4", NULL,
295 NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
296 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
297
298 SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
299 SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
300 SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
301 SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
302
303 SND_SOC_DAPM_MUX("Digital CH4 Mux",
304 SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
305 SND_SOC_DAPM_MUX("Digital CH3 Mux",
306 SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
307 SND_SOC_DAPM_MUX("Digital CH2 Mux",
308 SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
309 SND_SOC_DAPM_MUX("Digital CH1 Mux",
310 SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
311
312 SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
313 aiftx_power_control, SND_SOC_DAPM_POST_PMD),
314};
315
316static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
317 {"Frontend PGA1", NULL, "MIC1"},
318 {"Frontend PGA2", NULL, "MIC2"},
319 {"Frontend PGA3", NULL, "MIC3"},
320 {"Frontend PGA4", NULL, "MIC4"},
321
322 {"ADC1", NULL, "Frontend PGA1"},
323 {"ADC2", NULL, "Frontend PGA2"},
324 {"ADC3", NULL, "Frontend PGA3"},
325 {"ADC4", NULL, "Frontend PGA4"},
326
327 {"ADC CH1", NULL, "ADC1"},
328 {"ADC CH2", NULL, "ADC2"},
329 {"ADC CH3", NULL, "ADC3"},
330 {"ADC CH4", NULL, "ADC4"},
331
332 {"ADC1", NULL, "MICBIAS1"},
333 {"ADC2", NULL, "MICBIAS1"},
334 {"ADC3", NULL, "MICBIAS2"},
335 {"ADC4", NULL, "MICBIAS2"},
336
337 {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
338 {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
339 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
340 {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
341
342 {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
343 {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
344 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
345 {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
346
347 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
348 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
349 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
350 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
351
352 {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
353 {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
354 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
355 {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
356
357 {"AIFTX", NULL, "Digital CH1 Mux"},
358 {"AIFTX", NULL, "Digital CH2 Mux"},
359 {"AIFTX", NULL, "Digital CH3 Mux"},
360 {"AIFTX", NULL, "Digital CH4 Mux"},
361};
362
363static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr)
364{
365 if (osr >= ARRAY_SIZE(osr_adc_sel))
366 return -EINVAL;
367
368 if (rate * osr > CLK_ADC_MAX) {
369 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
370 return -EINVAL;
371 }
372
373 return 0;
374}
375
376static int nau8540_hw_params(struct snd_pcm_substream *substream,
377 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
378{
379 struct snd_soc_component *component = dai->component;
380 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
381 unsigned int val_len = 0, osr;
382
383
384
385
386
387
388
389 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
390 osr &= NAU8540_ADC_OSR_MASK;
391 if (nau8540_clock_check(nau8540, params_rate(params), osr))
392 return -EINVAL;
393 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
394 NAU8540_CLK_ADC_SRC_MASK,
395 osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT);
396
397 switch (params_width(params)) {
398 case 16:
399 val_len |= NAU8540_I2S_DL_16;
400 break;
401 case 20:
402 val_len |= NAU8540_I2S_DL_20;
403 break;
404 case 24:
405 val_len |= NAU8540_I2S_DL_24;
406 break;
407 case 32:
408 val_len |= NAU8540_I2S_DL_32;
409 break;
410 default:
411 return -EINVAL;
412 }
413
414 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
415 NAU8540_I2S_DL_MASK, val_len);
416
417 return 0;
418}
419
420static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
421{
422 struct snd_soc_component *component = dai->component;
423 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
424 unsigned int ctrl1_val = 0, ctrl2_val = 0;
425
426 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
427 case SND_SOC_DAIFMT_CBM_CFM:
428 ctrl2_val |= NAU8540_I2S_MS_MASTER;
429 break;
430 case SND_SOC_DAIFMT_CBS_CFS:
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
437 case SND_SOC_DAIFMT_NB_NF:
438 break;
439 case SND_SOC_DAIFMT_IB_NF:
440 ctrl1_val |= NAU8540_I2S_BP_INV;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
447 case SND_SOC_DAIFMT_I2S:
448 ctrl1_val |= NAU8540_I2S_DF_I2S;
449 break;
450 case SND_SOC_DAIFMT_LEFT_J:
451 ctrl1_val |= NAU8540_I2S_DF_LEFT;
452 break;
453 case SND_SOC_DAIFMT_RIGHT_J:
454 ctrl1_val |= NAU8540_I2S_DF_RIGTH;
455 break;
456 case SND_SOC_DAIFMT_DSP_A:
457 ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
458 break;
459 case SND_SOC_DAIFMT_DSP_B:
460 ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
461 ctrl1_val |= NAU8540_I2S_PCMB_EN;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
468 NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
469 NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
470 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
471 NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
472 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
473 NAU8540_I2S_DO34_OE, 0);
474
475 return 0;
476}
477
478
479
480
481
482
483
484
485
486
487
488
489
490static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
491 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
492{
493 struct snd_soc_component *component = dai->component;
494 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
495 unsigned int ctrl2_val = 0, ctrl4_val = 0;
496
497 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
498 return -EINVAL;
499
500 ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
501 if (tx_mask & 0xf0) {
502 ctrl2_val = 4 * slot_width;
503 ctrl4_val |= (tx_mask >> 4);
504 } else {
505 ctrl4_val |= tx_mask;
506 }
507 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
508 NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
509 NAU8540_TDM_TX_MASK, ctrl4_val);
510 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
511 NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
512 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
513 NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
514 NAU8540_I2S_DO34_OE | ctrl2_val);
515
516 return 0;
517}
518
519
520static const struct snd_soc_dai_ops nau8540_dai_ops = {
521 .hw_params = nau8540_hw_params,
522 .set_fmt = nau8540_set_fmt,
523 .set_tdm_slot = nau8540_set_tdm_slot,
524};
525
526#define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
527#define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
528 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
529
530static struct snd_soc_dai_driver nau8540_dai = {
531 .name = "nau8540-hifi",
532 .capture = {
533 .stream_name = "Capture",
534 .channels_min = 1,
535 .channels_max = 4,
536 .rates = NAU8540_RATES,
537 .formats = NAU8540_FORMATS,
538 },
539 .ops = &nau8540_dai_ops,
540};
541
542
543
544
545
546
547
548
549
550
551
552static int nau8540_calc_fll_param(unsigned int fll_in,
553 unsigned int fs, struct nau8540_fll *fll_param)
554{
555 u64 fvco, fvco_max;
556 unsigned int fref, i, fvco_sel;
557
558
559
560
561
562 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
563 fref = fll_in / fll_pre_scalar[i].param;
564 if (fref <= NAU_FREF_MAX)
565 break;
566 }
567 if (i == ARRAY_SIZE(fll_pre_scalar))
568 return -EINVAL;
569 fll_param->clk_ref_div = fll_pre_scalar[i].val;
570
571
572 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
573 if (fref >= fll_ratio[i].param)
574 break;
575 }
576 if (i == ARRAY_SIZE(fll_ratio))
577 return -EINVAL;
578 fll_param->ratio = fll_ratio[i].val;
579
580
581
582
583
584
585 fvco_max = 0;
586 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
587 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
588 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
589 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
590 fvco_max < fvco) {
591 fvco_max = fvco;
592 fvco_sel = i;
593 }
594 }
595 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
596 return -EINVAL;
597 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
598
599
600
601
602 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
603 fll_param->fll_int = (fvco >> 16) & 0x3FF;
604 fll_param->fll_frac = fvco & 0xFFFF;
605 return 0;
606}
607
608static void nau8540_fll_apply(struct regmap *regmap,
609 struct nau8540_fll *fll_param)
610{
611 regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
612 NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
613 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
614 regmap_update_bits(regmap, NAU8540_REG_FLL1,
615 NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK,
616 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
617
618 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
619
620 regmap_update_bits(regmap, NAU8540_REG_FLL3,
621 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
622
623 regmap_update_bits(regmap, NAU8540_REG_FLL4,
624 NAU8540_FLL_REF_DIV_MASK,
625 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
626 regmap_update_bits(regmap, NAU8540_REG_FLL5,
627 NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
628 regmap_update_bits(regmap,
629 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
630 if (fll_param->fll_frac) {
631 regmap_update_bits(regmap, NAU8540_REG_FLL5,
632 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
633 NAU8540_FLL_FTR_SW_MASK,
634 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
635 NAU8540_FLL_FTR_SW_FILTER);
636 regmap_update_bits(regmap, NAU8540_REG_FLL6,
637 NAU8540_SDM_EN | NAU8540_CUTOFF500,
638 NAU8540_SDM_EN | NAU8540_CUTOFF500);
639 } else {
640 regmap_update_bits(regmap, NAU8540_REG_FLL5,
641 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
642 NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
643 regmap_update_bits(regmap, NAU8540_REG_FLL6,
644 NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);
645 }
646}
647
648
649static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source,
650 unsigned int freq_in, unsigned int freq_out)
651{
652 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
653 struct nau8540_fll fll_param;
654 int ret, fs;
655
656 switch (pll_id) {
657 case NAU8540_CLK_FLL_MCLK:
658 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
659 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
660 NAU8540_FLL_CLK_SRC_MCLK | 0);
661 break;
662
663 case NAU8540_CLK_FLL_BLK:
664 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
665 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
666 NAU8540_FLL_CLK_SRC_BLK |
667 (0xf << NAU8540_GAIN_ERR_SFT));
668 break;
669
670 case NAU8540_CLK_FLL_FS:
671 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
672 NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK,
673 NAU8540_FLL_CLK_SRC_FS |
674 (0xf << NAU8540_GAIN_ERR_SFT));
675 break;
676
677 default:
678 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
679 return -EINVAL;
680 }
681 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
682 freq_out, pll_id);
683
684 fs = freq_out / 256;
685 ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
686 if (ret < 0) {
687 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
688 return ret;
689 }
690 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
691 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
692 fll_param.fll_int, fll_param.clk_ref_div);
693
694 nau8540_fll_apply(nau8540->regmap, &fll_param);
695 mdelay(2);
696 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
697 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
698
699 return 0;
700}
701
702static int nau8540_set_sysclk(struct snd_soc_component *component,
703 int clk_id, int source, unsigned int freq, int dir)
704{
705 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
706
707 switch (clk_id) {
708 case NAU8540_CLK_DIS:
709 case NAU8540_CLK_MCLK:
710 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
711 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
712 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
713 NAU8540_DCO_EN, 0);
714 break;
715
716 case NAU8540_CLK_INTERNAL:
717 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
718 NAU8540_DCO_EN, NAU8540_DCO_EN);
719 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
720 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
721 break;
722
723 default:
724 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
725 return -EINVAL;
726 }
727
728 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
729 freq, clk_id);
730
731 return 0;
732}
733
734static void nau8540_reset_chip(struct regmap *regmap)
735{
736 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
737 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
738}
739
740static void nau8540_init_regs(struct nau8540 *nau8540)
741{
742 struct regmap *regmap = nau8540->regmap;
743
744
745 regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
746 NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
747 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
748 regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
749 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
750 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
751 mdelay(2);
752 regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
753 NAU8540_PU_PRE, NAU8540_PU_PRE);
754 regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
755 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
756 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
757
758
759
760 regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
761 NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
762 NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
763
764 regmap_update_bits(regmap, NAU8540_REG_FEPGA1,
765 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT,
766 NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT);
767 regmap_update_bits(regmap, NAU8540_REG_FEPGA2,
768 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT,
769 NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT);
770
771 regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1,
772 NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI);
773 regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2,
774 NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI);
775}
776
777static int __maybe_unused nau8540_suspend(struct snd_soc_component *component)
778{
779 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
780
781 regcache_cache_only(nau8540->regmap, true);
782 regcache_mark_dirty(nau8540->regmap);
783
784 return 0;
785}
786
787static int __maybe_unused nau8540_resume(struct snd_soc_component *component)
788{
789 struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component);
790
791 regcache_cache_only(nau8540->regmap, false);
792 regcache_sync(nau8540->regmap);
793
794 return 0;
795}
796
797static const struct snd_soc_component_driver nau8540_component_driver = {
798 .set_sysclk = nau8540_set_sysclk,
799 .set_pll = nau8540_set_pll,
800 .suspend = nau8540_suspend,
801 .resume = nau8540_resume,
802 .controls = nau8540_snd_controls,
803 .num_controls = ARRAY_SIZE(nau8540_snd_controls),
804 .dapm_widgets = nau8540_dapm_widgets,
805 .num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets),
806 .dapm_routes = nau8540_dapm_routes,
807 .num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes),
808 .suspend_bias_off = 1,
809 .idle_bias_on = 1,
810 .use_pmdown_time = 1,
811 .endianness = 1,
812 .non_legacy_dai_naming = 1,
813};
814
815static const struct regmap_config nau8540_regmap_config = {
816 .val_bits = 16,
817 .reg_bits = 16,
818
819 .max_register = NAU8540_REG_MAX,
820 .readable_reg = nau8540_readable_reg,
821 .writeable_reg = nau8540_writeable_reg,
822 .volatile_reg = nau8540_volatile_reg,
823
824 .cache_type = REGCACHE_RBTREE,
825 .reg_defaults = nau8540_reg_defaults,
826 .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
827};
828
829static int nau8540_i2c_probe(struct i2c_client *i2c,
830 const struct i2c_device_id *id)
831{
832 struct device *dev = &i2c->dev;
833 struct nau8540 *nau8540 = dev_get_platdata(dev);
834 int ret, value;
835
836 if (!nau8540) {
837 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
838 if (!nau8540)
839 return -ENOMEM;
840 }
841 i2c_set_clientdata(i2c, nau8540);
842
843 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
844 if (IS_ERR(nau8540->regmap))
845 return PTR_ERR(nau8540->regmap);
846 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
847 if (ret < 0) {
848 dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
849 ret);
850 return ret;
851 }
852
853 nau8540->dev = dev;
854 nau8540_reset_chip(nau8540->regmap);
855 nau8540_init_regs(nau8540);
856
857 return devm_snd_soc_register_component(dev,
858 &nau8540_component_driver, &nau8540_dai, 1);
859}
860
861static const struct i2c_device_id nau8540_i2c_ids[] = {
862 { "nau8540", 0 },
863 { }
864};
865MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
866
867#ifdef CONFIG_OF
868static const struct of_device_id nau8540_of_ids[] = {
869 { .compatible = "nuvoton,nau8540", },
870 {}
871};
872MODULE_DEVICE_TABLE(of, nau8540_of_ids);
873#endif
874
875static struct i2c_driver nau8540_i2c_driver = {
876 .driver = {
877 .name = "nau8540",
878 .of_match_table = of_match_ptr(nau8540_of_ids),
879 },
880 .probe = nau8540_i2c_probe,
881 .id_table = nau8540_i2c_ids,
882};
883module_i2c_driver(nau8540_i2c_driver);
884
885MODULE_DESCRIPTION("ASoC NAU85L40 driver");
886MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
887MODULE_LICENSE("GPL v2");
888
