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12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/dmi.h>
21#include <linux/acpi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <linux/workqueue.h>
31
32#include "rl6347a.h"
33#include "rt274.h"
34
35#define RT274_VENDOR_ID 0x10ec0274
36
37struct rt274_priv {
38 struct reg_default *index_cache;
39 int index_cache_size;
40 struct regmap *regmap;
41 struct snd_soc_component *component;
42 struct i2c_client *i2c;
43 struct snd_soc_jack *jack;
44 struct delayed_work jack_detect_work;
45 int sys_clk;
46 int clk_id;
47 int fs;
48 bool master;
49};
50
51static const struct reg_default rt274_index_def[] = {
52 { 0x00, 0x1004 },
53 { 0x01, 0xaaaa },
54 { 0x02, 0x88aa },
55 { 0x03, 0x0002 },
56 { 0x04, 0xaa09 },
57 { 0x05, 0x0700 },
58 { 0x06, 0x6110 },
59 { 0x07, 0x0200 },
60 { 0x08, 0xa807 },
61 { 0x09, 0x0021 },
62 { 0x0a, 0x7770 },
63 { 0x0b, 0x7770 },
64 { 0x0c, 0x002b },
65 { 0x0d, 0x2420 },
66 { 0x0e, 0x65c0 },
67 { 0x0f, 0x7770 },
68 { 0x10, 0x0420 },
69 { 0x11, 0x7418 },
70 { 0x12, 0x6bd0 },
71 { 0x13, 0x645f },
72 { 0x14, 0x0400 },
73 { 0x15, 0x8ccc },
74 { 0x16, 0x4c50 },
75 { 0x17, 0xff00 },
76 { 0x18, 0x0003 },
77 { 0x19, 0x2c11 },
78 { 0x1a, 0x830b },
79 { 0x1b, 0x4e4b },
80 { 0x1c, 0x0000 },
81 { 0x1d, 0x0000 },
82 { 0x1e, 0x0000 },
83 { 0x1f, 0x0000 },
84 { 0x20, 0x51ff },
85 { 0x21, 0x8000 },
86 { 0x22, 0x8f00 },
87 { 0x23, 0x88f4 },
88 { 0x24, 0x0000 },
89 { 0x25, 0x0000 },
90 { 0x26, 0x0000 },
91 { 0x27, 0x0000 },
92 { 0x28, 0x0000 },
93 { 0x29, 0x3000 },
94 { 0x2a, 0x0000 },
95 { 0x2b, 0x0000 },
96 { 0x2c, 0x0f00 },
97 { 0x2d, 0x100f },
98 { 0x2e, 0x2902 },
99 { 0x2f, 0xe280 },
100 { 0x30, 0x1000 },
101 { 0x31, 0x8400 },
102 { 0x32, 0x5aaa },
103 { 0x33, 0x8420 },
104 { 0x34, 0xa20c },
105 { 0x35, 0x096a },
106 { 0x36, 0x5757 },
107 { 0x37, 0xfe05 },
108 { 0x38, 0x4901 },
109 { 0x39, 0x110a },
110 { 0x3a, 0x0010 },
111 { 0x3b, 0x60d9 },
112 { 0x3c, 0xf214 },
113 { 0x3d, 0xc2ba },
114 { 0x3e, 0xa928 },
115 { 0x3f, 0x0000 },
116 { 0x40, 0x9800 },
117 { 0x41, 0x0000 },
118 { 0x42, 0x2000 },
119 { 0x43, 0x3d90 },
120 { 0x44, 0x4900 },
121 { 0x45, 0x5289 },
122 { 0x46, 0x0004 },
123 { 0x47, 0xa47a },
124 { 0x48, 0xd049 },
125 { 0x49, 0x0049 },
126 { 0x4a, 0xa83b },
127 { 0x4b, 0x0777 },
128 { 0x4c, 0x065c },
129 { 0x4d, 0x7fff },
130 { 0x4e, 0x7fff },
131 { 0x4f, 0x0000 },
132 { 0x50, 0x0000 },
133 { 0x51, 0x0000 },
134 { 0x52, 0xbf5f },
135 { 0x53, 0x3320 },
136 { 0x54, 0xcc00 },
137 { 0x55, 0x0000 },
138 { 0x56, 0x3f00 },
139 { 0x57, 0x0000 },
140 { 0x58, 0x0000 },
141 { 0x59, 0x0000 },
142 { 0x5a, 0x1300 },
143 { 0x5b, 0x005f },
144 { 0x5c, 0x0000 },
145 { 0x5d, 0x1001 },
146 { 0x5e, 0x1000 },
147 { 0x5f, 0x0000 },
148 { 0x60, 0x5554 },
149 { 0x61, 0xffc0 },
150 { 0x62, 0xa000 },
151 { 0x63, 0xd010 },
152 { 0x64, 0x0000 },
153 { 0x65, 0x3fb1 },
154 { 0x66, 0x1881 },
155 { 0x67, 0xc810 },
156 { 0x68, 0x2000 },
157 { 0x69, 0xfff0 },
158 { 0x6a, 0x0300 },
159 { 0x6b, 0x5060 },
160 { 0x6c, 0x0000 },
161 { 0x6d, 0x0000 },
162 { 0x6e, 0x0c25 },
163 { 0x6f, 0x0c0b },
164 { 0x70, 0x8000 },
165 { 0x71, 0x4008 },
166 { 0x72, 0x0000 },
167 { 0x73, 0x0800 },
168 { 0x74, 0xa28f },
169 { 0x75, 0xa050 },
170 { 0x76, 0x7fe8 },
171 { 0x77, 0xdb8c },
172 { 0x78, 0x0000 },
173 { 0x79, 0x0000 },
174 { 0x7a, 0x2a96 },
175 { 0x7b, 0x800f },
176 { 0x7c, 0x0200 },
177 { 0x7d, 0x1600 },
178 { 0x7e, 0x0000 },
179 { 0x7f, 0x0000 },
180};
181#define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def)
182
183static const struct reg_default rt274_reg[] = {
184 { 0x00170500, 0x00000400 },
185 { 0x00220000, 0x00000031 },
186 { 0x00239000, 0x00000057 },
187 { 0x0023a000, 0x00000057 },
188 { 0x00270500, 0x00000400 },
189 { 0x00370500, 0x00000400 },
190 { 0x00870500, 0x00000400 },
191 { 0x00920000, 0x00000031 },
192 { 0x00935000, 0x00000097 },
193 { 0x00936000, 0x00000097 },
194 { 0x00970500, 0x00000400 },
195 { 0x00b37000, 0x00000400 },
196 { 0x00b37200, 0x00000400 },
197 { 0x00b37300, 0x00000400 },
198 { 0x00c37000, 0x00000400 },
199 { 0x00c37100, 0x00000400 },
200 { 0x01270500, 0x00000400 },
201 { 0x01370500, 0x00000400 },
202 { 0x01371f00, 0x411111f0 },
203 { 0x01937000, 0x00000000 },
204 { 0x01970500, 0x00000400 },
205 { 0x02050000, 0x0000001b },
206 { 0x02139000, 0x00000080 },
207 { 0x0213a000, 0x00000080 },
208 { 0x02170100, 0x00000001 },
209 { 0x02170500, 0x00000400 },
210 { 0x02170700, 0x00000000 },
211 { 0x02270100, 0x00000000 },
212 { 0x02370100, 0x00000000 },
213 { 0x01970700, 0x00000020 },
214 { 0x00830000, 0x00000097 },
215 { 0x00930000, 0x00000097 },
216 { 0x01270700, 0x00000000 },
217};
218
219static bool rt274_volatile_register(struct device *dev, unsigned int reg)
220{
221 switch (reg) {
222 case 0 ... 0xff:
223 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
224 case RT274_GET_HP_SENSE:
225 case RT274_GET_MIC_SENSE:
226 case RT274_PROC_COEF:
227 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
228 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
229 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
230 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
231 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
232 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
233 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
234 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
235 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
236 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
237 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
238 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
239 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
240 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
241 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
242 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
243 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
244 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
245 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
246 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
247 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
248 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
249 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
250 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
251 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
252 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
253 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
254 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
255 return true;
256 default:
257 return false;
258 }
259
260
261}
262
263static bool rt274_readable_register(struct device *dev, unsigned int reg)
264{
265 switch (reg) {
266 case 0 ... 0xff:
267 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
268 case RT274_GET_HP_SENSE:
269 case RT274_GET_MIC_SENSE:
270 case RT274_SET_AUDIO_POWER:
271 case RT274_SET_HPO_POWER:
272 case RT274_SET_DMIC1_POWER:
273 case RT274_LOUT_MUX:
274 case RT274_HPO_MUX:
275 case RT274_ADC0_MUX:
276 case RT274_ADC1_MUX:
277 case RT274_SET_MIC:
278 case RT274_SET_PIN_HPO:
279 case RT274_SET_PIN_LOUT3:
280 case RT274_SET_PIN_DMIC1:
281 case RT274_SET_AMP_GAIN_HPO:
282 case RT274_SET_DMIC2_DEFAULT:
283 case RT274_DAC0L_GAIN:
284 case RT274_DAC0R_GAIN:
285 case RT274_DAC1L_GAIN:
286 case RT274_DAC1R_GAIN:
287 case RT274_ADCL_GAIN:
288 case RT274_ADCR_GAIN:
289 case RT274_MIC_GAIN:
290 case RT274_HPOL_GAIN:
291 case RT274_HPOR_GAIN:
292 case RT274_LOUTL_GAIN:
293 case RT274_LOUTR_GAIN:
294 case RT274_DAC_FORMAT:
295 case RT274_ADC_FORMAT:
296 case RT274_COEF_INDEX:
297 case RT274_PROC_COEF:
298 case RT274_SET_AMP_GAIN_ADC_IN1:
299 case RT274_SET_AMP_GAIN_ADC_IN2:
300 case RT274_SET_POWER(RT274_DAC_OUT0):
301 case RT274_SET_POWER(RT274_DAC_OUT1):
302 case RT274_SET_POWER(RT274_ADC_IN1):
303 case RT274_SET_POWER(RT274_ADC_IN2):
304 case RT274_SET_POWER(RT274_DMIC2):
305 case RT274_SET_POWER(RT274_MIC):
306 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):
307 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):
308 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):
309 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):
310 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):
311 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):
312 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):
313 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):
314 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):
315 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):
316 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):
317 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):
318 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):
319 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):
320 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):
321 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):
322 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):
323 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):
324 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):
325 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):
326 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):
327 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):
328 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):
329 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):
330 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):
331 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):
332 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):
333 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):
334 return true;
335 default:
336 return false;
337 }
338}
339
340#ifdef CONFIG_PM
341static void rt274_index_sync(struct snd_soc_component *component)
342{
343 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
344 int i;
345
346 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
347 snd_soc_component_write(component, rt274->index_cache[i].reg,
348 rt274->index_cache[i].def);
349 }
350}
351#endif
352
353static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic)
354{
355 unsigned int buf;
356
357 *hp = false;
358 *mic = false;
359
360 if (!rt274->component)
361 return -EINVAL;
362
363 regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf);
364 *hp = buf & 0x80000000;
365 regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf);
366 *mic = buf & 0x80000000;
367
368 pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
369
370 return 0;
371}
372
373static void rt274_jack_detect_work(struct work_struct *work)
374{
375 struct rt274_priv *rt274 =
376 container_of(work, struct rt274_priv, jack_detect_work.work);
377 int status = 0;
378 bool hp = false;
379 bool mic = false;
380
381 if (rt274_jack_detect(rt274, &hp, &mic) < 0)
382 return;
383
384 if (hp == true)
385 status |= SND_JACK_HEADPHONE;
386
387 if (mic == true)
388 status |= SND_JACK_MICROPHONE;
389
390 snd_soc_jack_report(rt274->jack, status,
391 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
392}
393
394static irqreturn_t rt274_irq(int irq, void *data);
395
396static int rt274_mic_detect(struct snd_soc_component *component,
397 struct snd_soc_jack *jack, void *data)
398{
399 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
400
401 if (jack == NULL) {
402
403 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
404 RT274_IRQ_EN, RT274_IRQ_DIS);
405
406 return 0;
407 }
408 rt274->jack = jack;
409
410 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
411 RT274_IRQ_EN, RT274_IRQ_EN);
412
413
414 rt274_irq(0, rt274);
415
416 return 0;
417}
418
419static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
420static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
421
422static const struct snd_kcontrol_new rt274_snd_controls[] = {
423 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN,
424 RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv),
425 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN,
426 RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv),
427 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN,
428 RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
429 SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN,
430 RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1),
431 SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN,
432 0, 0x3, 0, mic_vol_tlv),
433};
434
435static const struct snd_kcontrol_new hpol_enable_control =
436 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN,
437 RT274_MUTE_SFT, 1, 1);
438
439static const struct snd_kcontrol_new hpor_enable_control =
440 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN,
441 RT274_MUTE_SFT, 1, 1);
442
443static const struct snd_kcontrol_new loutl_enable_control =
444 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN,
445 RT274_MUTE_SFT, 1, 1);
446
447static const struct snd_kcontrol_new loutr_enable_control =
448 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN,
449 RT274_MUTE_SFT, 1, 1);
450
451
452static const char * const rt274_adc_src[] = {
453 "Mic", "Line1", "Line2", "Dmic"
454};
455
456static SOC_ENUM_SINGLE_DECL(
457 rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT,
458 rt274_adc_src);
459
460static const struct snd_kcontrol_new rt274_adc0_mux =
461 SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum);
462
463static SOC_ENUM_SINGLE_DECL(
464 rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT,
465 rt274_adc_src);
466
467static const struct snd_kcontrol_new rt274_adc1_mux =
468 SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum);
469
470static const char * const rt274_dac_src[] = {
471 "DAC OUT0", "DAC OUT1"
472};
473
474static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX,
475 0, rt274_dac_src);
476
477static const struct snd_kcontrol_new rt274_hpo_mux =
478SOC_DAPM_ENUM("HPO source", rt274_hpo_enum);
479
480
481static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX,
482 0, rt274_dac_src);
483
484static const struct snd_kcontrol_new rt274_lout_mux =
485SOC_DAPM_ENUM("LOUT source", rt274_lout_enum);
486
487static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = {
488
489 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
490 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
491 SND_SOC_DAPM_INPUT("MIC"),
492 SND_SOC_DAPM_INPUT("LINE1"),
493 SND_SOC_DAPM_INPUT("LINE2"),
494
495
496 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
497 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
498
499
500 SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0),
501 SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0),
502
503
504 SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0,
505 &rt274_adc0_mux),
506 SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0,
507 &rt274_adc1_mux),
508
509
510 SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
511 SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0),
512 SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
513 SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0),
514 SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0),
515 SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0),
516 SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0),
517 SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0),
518
519
520
521 SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0),
522 SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0),
523
524
525 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux),
526 SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux),
527
528 SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO,
529 RT274_SET_PIN_SFT, 0, NULL, 0),
530 SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3,
531 RT274_SET_PIN_SFT, 0, NULL, 0),
532
533
534 SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0,
535 NULL, 0),
536 SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0,
537 NULL, 0),
538
539
540 SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0,
541 &loutl_enable_control),
542 SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0,
543 &loutr_enable_control),
544 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
545 &hpol_enable_control),
546 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
547 &hpor_enable_control),
548
549
550 SND_SOC_DAPM_OUTPUT("HPO Pin"),
551 SND_SOC_DAPM_OUTPUT("SPDIF"),
552 SND_SOC_DAPM_OUTPUT("LINE3"),
553};
554
555static const struct snd_soc_dapm_route rt274_dapm_routes[] = {
556 {"DMIC1", NULL, "DMIC1 Pin"},
557 {"DMIC2", NULL, "DMIC2 Pin"},
558
559 {"ADC 0 Mux", "Mic", "MIC"},
560 {"ADC 0 Mux", "Dmic", "DMIC1"},
561 {"ADC 0 Mux", "Line1", "LINE1"},
562 {"ADC 0 Mux", "Line2", "LINE2"},
563 {"ADC 1 Mux", "Mic", "MIC"},
564 {"ADC 1 Mux", "Dmic", "DMIC2"},
565 {"ADC 1 Mux", "Line1", "LINE1"},
566 {"ADC 1 Mux", "Line2", "LINE2"},
567
568 {"ADC 0", NULL, "ADC 0 Mux"},
569 {"ADC 1", NULL, "ADC 1 Mux"},
570
571 {"AIF1TXL", NULL, "ADC 0"},
572 {"AIF1TXR", NULL, "ADC 0"},
573 {"AIF2TXL", NULL, "ADC 1"},
574 {"AIF2TXR", NULL, "ADC 1"},
575
576 {"DAC 0", NULL, "AIF1RXL"},
577 {"DAC 0", NULL, "AIF1RXR"},
578 {"DAC 1", NULL, "AIF2RXL"},
579 {"DAC 1", NULL, "AIF2RXR"},
580
581 {"DAC OUT0", NULL, "DAC 0"},
582
583 {"DAC OUT1", NULL, "DAC 1"},
584
585 {"LOUT Mux", "DAC OUT0", "DAC OUT0"},
586 {"LOUT Mux", "DAC OUT1", "DAC OUT1"},
587
588 {"LOUT L", "Switch", "LOUT Mux"},
589 {"LOUT R", "Switch", "LOUT Mux"},
590 {"LOUT L", NULL, "LOUT Power"},
591 {"LOUT R", NULL, "LOUT Power"},
592
593 {"LINE3", NULL, "LOUT L"},
594 {"LINE3", NULL, "LOUT R"},
595
596 {"HPO Mux", "DAC OUT0", "DAC OUT0"},
597 {"HPO Mux", "DAC OUT1", "DAC OUT1"},
598
599 {"HPO L", "Switch", "HPO Mux"},
600 {"HPO R", "Switch", "HPO Mux"},
601 {"HPO L", NULL, "HP Power"},
602 {"HPO R", NULL, "HP Power"},
603
604 {"HPO Pin", NULL, "HPO L"},
605 {"HPO Pin", NULL, "HPO R"},
606};
607
608static int rt274_hw_params(struct snd_pcm_substream *substream,
609 struct snd_pcm_hw_params *params,
610 struct snd_soc_dai *dai)
611{
612 struct snd_soc_component *component = dai->component;
613 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
614 unsigned int val = 0;
615 int d_len_code = 0, c_len_code = 0;
616
617 switch (params_rate(params)) {
618
619 case 44100:
620 case 48000:
621 break;
622 default:
623 dev_err(component->dev, "Unsupported sample rate %d\n",
624 params_rate(params));
625 return -EINVAL;
626 }
627 switch (rt274->sys_clk) {
628 case 12288000:
629 case 24576000:
630 if (params_rate(params) != 48000) {
631 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
632 params_rate(params), rt274->sys_clk);
633 return -EINVAL;
634 }
635 break;
636 case 11289600:
637 case 22579200:
638 if (params_rate(params) != 44100) {
639 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",
640 params_rate(params), rt274->sys_clk);
641 return -EINVAL;
642 }
643 break;
644 }
645
646 if (params_channels(params) <= 16) {
647
648 val |= (params_channels(params) - 1);
649 } else {
650 dev_err(component->dev, "Unsupported channels %d\n",
651 params_channels(params));
652 return -EINVAL;
653 }
654
655 switch (params_width(params)) {
656
657 case 16:
658 d_len_code = 0;
659 c_len_code = 0;
660 val |= (0x1 << 4);
661 break;
662 case 32:
663 d_len_code = 2;
664 c_len_code = 3;
665 val |= (0x4 << 4);
666 break;
667 case 20:
668 d_len_code = 1;
669 c_len_code = 1;
670 val |= (0x2 << 4);
671 break;
672 case 24:
673 d_len_code = 2;
674 c_len_code = 2;
675 val |= (0x3 << 4);
676 break;
677 case 8:
678 d_len_code = 3;
679 c_len_code = 0;
680 break;
681 default:
682 return -EINVAL;
683 }
684
685 if (rt274->master)
686 c_len_code = 0x3;
687
688 snd_soc_component_update_bits(component,
689 RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14);
690 dev_dbg(component->dev, "format val = 0x%x\n", val);
691
692 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val);
693 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val);
694
695 return 0;
696}
697
698static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
699{
700 struct snd_soc_component *component = dai->component;
701 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
702
703 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
704 case SND_SOC_DAIFMT_CBM_CFM:
705 snd_soc_component_update_bits(component,
706 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M);
707 rt274->master = true;
708 break;
709 case SND_SOC_DAIFMT_CBS_CFS:
710 snd_soc_component_update_bits(component,
711 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S);
712 rt274->master = false;
713 break;
714 default:
715 return -EINVAL;
716 }
717
718 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
719 case SND_SOC_DAIFMT_I2S:
720 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
721 RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S);
722 break;
723 case SND_SOC_DAIFMT_LEFT_J:
724 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
725 RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ);
726 break;
727 case SND_SOC_DAIFMT_DSP_A:
728 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
729 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA);
730 break;
731 case SND_SOC_DAIFMT_DSP_B:
732 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,
733 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB);
734 break;
735 default:
736 return -EINVAL;
737 }
738
739 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0);
740 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0);
741
742 return 0;
743}
744
745static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
746 unsigned int freq_in, unsigned int freq_out)
747{
748 struct snd_soc_component *component = dai->component;
749 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
750
751 switch (source) {
752 case RT274_PLL2_S_MCLK:
753 snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
754 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK);
755 break;
756 default:
757 dev_warn(component->dev, "invalid pll source, use BCLK\n");
758 case RT274_PLL2_S_BCLK:
759 snd_soc_component_update_bits(component, RT274_PLL2_CTRL,
760 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK);
761 break;
762 }
763
764 if (source == RT274_PLL2_S_BCLK) {
765 snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
766 (0x3 << 12), (0x3 << 12));
767 switch (rt274->fs) {
768 case 50:
769 snd_soc_component_write(component, 0x7a, 0xaab6);
770 snd_soc_component_write(component, 0x7b, 0x0301);
771 snd_soc_component_write(component, 0x7c, 0x04fe);
772 break;
773 case 64:
774 snd_soc_component_write(component, 0x7a, 0xaa96);
775 snd_soc_component_write(component, 0x7b, 0x8003);
776 snd_soc_component_write(component, 0x7c, 0x081e);
777 break;
778 case 128:
779 snd_soc_component_write(component, 0x7a, 0xaa96);
780 snd_soc_component_write(component, 0x7b, 0x8003);
781 snd_soc_component_write(component, 0x7c, 0x080e);
782 break;
783 default:
784 dev_warn(component->dev, "invalid freq_in, assume 4.8M\n");
785 case 100:
786 snd_soc_component_write(component, 0x7a, 0xaab6);
787 snd_soc_component_write(component, 0x7b, 0x0301);
788 snd_soc_component_write(component, 0x7c, 0x047e);
789 break;
790 }
791 }
792
793 return 0;
794}
795
796static int rt274_set_dai_sysclk(struct snd_soc_dai *dai,
797 int clk_id, unsigned int freq, int dir)
798{
799 struct snd_soc_component *component = dai->component;
800 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
801 unsigned int clk_src, mclk_en;
802
803 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);
804
805 switch (clk_id) {
806 case RT274_SCLK_S_MCLK:
807 mclk_en = RT274_MCLK_MODE_EN;
808 clk_src = RT274_CLK_SRC_MCLK;
809 break;
810 case RT274_SCLK_S_PLL1:
811 mclk_en = RT274_MCLK_MODE_DIS;
812 clk_src = RT274_CLK_SRC_MCLK;
813 break;
814 case RT274_SCLK_S_PLL2:
815 mclk_en = RT274_MCLK_MODE_EN;
816 clk_src = RT274_CLK_SRC_PLL2;
817 break;
818 default:
819 mclk_en = RT274_MCLK_MODE_DIS;
820 clk_src = RT274_CLK_SRC_MCLK;
821 dev_warn(component->dev, "invalid sysclk source, use PLL1\n");
822 break;
823 }
824 snd_soc_component_update_bits(component, RT274_MCLK_CTRL,
825 RT274_MCLK_MODE_MASK, mclk_en);
826 snd_soc_component_update_bits(component, RT274_CLK_CTRL,
827 RT274_CLK_SRC_MASK, clk_src);
828
829 switch (freq) {
830 case 19200000:
831 if (clk_id == RT274_SCLK_S_MCLK) {
832 dev_err(component->dev, "Should not use MCLK\n");
833 return -EINVAL;
834 }
835 snd_soc_component_update_bits(component,
836 RT274_I2S_CTRL2, 0x40, 0x40);
837 break;
838 case 24000000:
839 if (clk_id == RT274_SCLK_S_MCLK) {
840 dev_err(component->dev, "Should not use MCLK\n");
841 return -EINVAL;
842 }
843 snd_soc_component_update_bits(component,
844 RT274_I2S_CTRL2, 0x40, 0x0);
845 break;
846 case 12288000:
847 case 11289600:
848 snd_soc_component_update_bits(component,
849 RT274_MCLK_CTRL, 0x1fcf, 0x0008);
850 break;
851 case 24576000:
852 case 22579200:
853 snd_soc_component_update_bits(component,
854 RT274_MCLK_CTRL, 0x1fcf, 0x1543);
855 break;
856 default:
857 dev_err(component->dev, "Unsupported system clock\n");
858 return -EINVAL;
859 }
860
861 rt274->sys_clk = freq;
862 rt274->clk_id = clk_id;
863
864 return 0;
865}
866
867static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
868{
869 struct snd_soc_component *component = dai->component;
870 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
871
872 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
873 rt274->fs = ratio;
874 if ((ratio / 50) == 0)
875 snd_soc_component_update_bits(component,
876 RT274_I2S_CTRL1, 0x1000, 0x1000);
877 else
878 snd_soc_component_update_bits(component,
879 RT274_I2S_CTRL1, 0x1000, 0x0);
880
881
882 return 0;
883}
884
885static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
886 unsigned int rx_mask, int slots, int slot_width)
887
888{
889 struct snd_soc_component *component = dai->component;
890
891 if (rx_mask || tx_mask) {
892 snd_soc_component_update_bits(component,
893 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN);
894 } else {
895 snd_soc_component_update_bits(component,
896 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS);
897 return 0;
898 }
899
900 switch (slots) {
901 case 4:
902 snd_soc_component_update_bits(component,
903 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH);
904 break;
905 case 2:
906 snd_soc_component_update_bits(component,
907 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH);
908 break;
909 default:
910 dev_err(component->dev,
911 "Support 2 or 4 slots TDM only\n");
912 return -EINVAL;
913 }
914
915 return 0;
916}
917
918static int rt274_set_bias_level(struct snd_soc_component *component,
919 enum snd_soc_bias_level level)
920{
921 switch (level) {
922 case SND_SOC_BIAS_PREPARE:
923 if (SND_SOC_BIAS_STANDBY ==
924 snd_soc_component_get_bias_level(component)) {
925 snd_soc_component_write(component,
926 RT274_SET_AUDIO_POWER, AC_PWRST_D0);
927 }
928 break;
929
930 case SND_SOC_BIAS_STANDBY:
931 snd_soc_component_write(component,
932 RT274_SET_AUDIO_POWER, AC_PWRST_D3);
933 break;
934
935 default:
936 break;
937 }
938
939 return 0;
940}
941
942static irqreturn_t rt274_irq(int irq, void *data)
943{
944 struct rt274_priv *rt274 = data;
945 bool hp = false;
946 bool mic = false;
947 int ret, status = 0;
948
949
950 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
951 RT274_IRQ_CLR, RT274_IRQ_CLR);
952
953 ret = rt274_jack_detect(rt274, &hp, &mic);
954
955 if (ret == 0) {
956 if (hp == true)
957 status |= SND_JACK_HEADPHONE;
958
959 if (mic == true)
960 status |= SND_JACK_MICROPHONE;
961
962 snd_soc_jack_report(rt274->jack, status,
963 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
964
965 pm_wakeup_event(&rt274->i2c->dev, 300);
966 }
967
968 return IRQ_HANDLED;
969}
970
971static int rt274_probe(struct snd_soc_component *component)
972{
973 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
974
975 rt274->component = component;
976
977 if (rt274->i2c->irq) {
978 INIT_DELAYED_WORK(&rt274->jack_detect_work,
979 rt274_jack_detect_work);
980 schedule_delayed_work(&rt274->jack_detect_work,
981 msecs_to_jiffies(1250));
982 }
983
984 return 0;
985}
986
987static void rt274_remove(struct snd_soc_component *component)
988{
989 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
990
991 cancel_delayed_work_sync(&rt274->jack_detect_work);
992}
993
994#ifdef CONFIG_PM
995static int rt274_suspend(struct snd_soc_component *component)
996{
997 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
998
999 regcache_cache_only(rt274->regmap, true);
1000 regcache_mark_dirty(rt274->regmap);
1001
1002 return 0;
1003}
1004
1005static int rt274_resume(struct snd_soc_component *component)
1006{
1007 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);
1008
1009 regcache_cache_only(rt274->regmap, false);
1010 rt274_index_sync(component);
1011 regcache_sync(rt274->regmap);
1012
1013 return 0;
1014}
1015#else
1016#define rt274_suspend NULL
1017#define rt274_resume NULL
1018#endif
1019
1020#define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1021#define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1022 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1023
1024static const struct snd_soc_dai_ops rt274_aif_dai_ops = {
1025 .hw_params = rt274_hw_params,
1026 .set_fmt = rt274_set_dai_fmt,
1027 .set_sysclk = rt274_set_dai_sysclk,
1028 .set_pll = rt274_set_dai_pll,
1029 .set_bclk_ratio = rt274_set_bclk_ratio,
1030 .set_tdm_slot = rt274_set_tdm_slot,
1031};
1032
1033static struct snd_soc_dai_driver rt274_dai[] = {
1034 {
1035 .name = "rt274-aif1",
1036 .id = RT274_AIF1,
1037 .playback = {
1038 .stream_name = "AIF1 Playback",
1039 .channels_min = 1,
1040 .channels_max = 2,
1041 .rates = RT274_STEREO_RATES,
1042 .formats = RT274_FORMATS,
1043 },
1044 .capture = {
1045 .stream_name = "AIF1 Capture",
1046 .channels_min = 1,
1047 .channels_max = 2,
1048 .rates = RT274_STEREO_RATES,
1049 .formats = RT274_FORMATS,
1050 },
1051 .ops = &rt274_aif_dai_ops,
1052 .symmetric_rates = 1,
1053 },
1054};
1055
1056static const struct snd_soc_component_driver soc_component_dev_rt274 = {
1057 .probe = rt274_probe,
1058 .remove = rt274_remove,
1059 .suspend = rt274_suspend,
1060 .resume = rt274_resume,
1061 .set_bias_level = rt274_set_bias_level,
1062 .set_jack = rt274_mic_detect,
1063 .controls = rt274_snd_controls,
1064 .num_controls = ARRAY_SIZE(rt274_snd_controls),
1065 .dapm_widgets = rt274_dapm_widgets,
1066 .num_dapm_widgets = ARRAY_SIZE(rt274_dapm_widgets),
1067 .dapm_routes = rt274_dapm_routes,
1068 .num_dapm_routes = ARRAY_SIZE(rt274_dapm_routes),
1069 .use_pmdown_time = 1,
1070 .endianness = 1,
1071 .non_legacy_dai_naming = 1,
1072};
1073
1074static const struct regmap_config rt274_regmap = {
1075 .reg_bits = 32,
1076 .val_bits = 32,
1077 .max_register = 0x05bfffff,
1078 .volatile_reg = rt274_volatile_register,
1079 .readable_reg = rt274_readable_register,
1080 .reg_write = rl6347a_hw_write,
1081 .reg_read = rl6347a_hw_read,
1082 .cache_type = REGCACHE_RBTREE,
1083 .reg_defaults = rt274_reg,
1084 .num_reg_defaults = ARRAY_SIZE(rt274_reg),
1085};
1086
1087#ifdef CONFIG_OF
1088static const struct of_device_id rt274_of_match[] = {
1089 {.compatible = "realtek,rt274"},
1090 {},
1091};
1092MODULE_DEVICE_TABLE(of, rt274_of_match);
1093#endif
1094
1095static const struct i2c_device_id rt274_i2c_id[] = {
1096 {"rt274", 0},
1097 {}
1098};
1099MODULE_DEVICE_TABLE(i2c, rt274_i2c_id);
1100
1101static const struct acpi_device_id rt274_acpi_match[] = {
1102 { "10EC0274", 0 },
1103 { "INT34C2", 0 },
1104 {},
1105};
1106MODULE_DEVICE_TABLE(acpi, rt274_acpi_match);
1107
1108static int rt274_i2c_probe(struct i2c_client *i2c,
1109 const struct i2c_device_id *id)
1110{
1111 struct rt274_priv *rt274;
1112
1113 int ret;
1114 unsigned int val;
1115
1116 rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274),
1117 GFP_KERNEL);
1118 if (rt274 == NULL)
1119 return -ENOMEM;
1120
1121 rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap);
1122 if (IS_ERR(rt274->regmap)) {
1123 ret = PTR_ERR(rt274->regmap);
1124 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1125 ret);
1126 return ret;
1127 }
1128
1129 regmap_read(rt274->regmap,
1130 RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
1131 if (val != RT274_VENDOR_ID) {
1132 dev_err(&i2c->dev,
1133 "Device with ID register %#x is not rt274\n", val);
1134 return -ENODEV;
1135 }
1136
1137 rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def,
1138 sizeof(rt274_index_def), GFP_KERNEL);
1139 if (!rt274->index_cache)
1140 return -ENOMEM;
1141
1142 rt274->index_cache_size = INDEX_CACHE_SIZE;
1143 rt274->i2c = i2c;
1144 i2c_set_clientdata(i2c, rt274);
1145
1146
1147 regmap_write(rt274->regmap, RT274_RESET, 0);
1148 regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000);
1149
1150
1151 regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0);
1152 regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01);
1153 regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540);
1154 regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100);
1155
1156 regmap_write(rt274->regmap, 0x4a, 0x201b);
1157
1158 regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000);
1159
1160 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0);
1161
1162 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
1163 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888);
1164 msleep(500);
1165 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb);
1166 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);
1167 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888);
1168
1169 regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40);
1170 regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40);
1171 regmap_write(rt274->regmap, RT274_SET_MIC, 0x20);
1172 regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20);
1173
1174 regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004);
1175 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,
1176 RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK);
1177
1178
1179 regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81);
1180 regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82);
1181
1182 if (rt274->i2c->irq) {
1183 ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq,
1184 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274);
1185 if (ret != 0) {
1186 dev_err(&i2c->dev,
1187 "Failed to reguest IRQ: %d\n", ret);
1188 return ret;
1189 }
1190 }
1191
1192 ret = devm_snd_soc_register_component(&i2c->dev,
1193 &soc_component_dev_rt274,
1194 rt274_dai, ARRAY_SIZE(rt274_dai));
1195
1196 return ret;
1197}
1198
1199static int rt274_i2c_remove(struct i2c_client *i2c)
1200{
1201 struct rt274_priv *rt274 = i2c_get_clientdata(i2c);
1202
1203 if (i2c->irq)
1204 free_irq(i2c->irq, rt274);
1205
1206 return 0;
1207}
1208
1209
1210static struct i2c_driver rt274_i2c_driver = {
1211 .driver = {
1212 .name = "rt274",
1213 .acpi_match_table = ACPI_PTR(rt274_acpi_match),
1214#ifdef CONFIG_OF
1215 .of_match_table = of_match_ptr(rt274_of_match),
1216#endif
1217 },
1218 .probe = rt274_i2c_probe,
1219 .remove = rt274_i2c_remove,
1220 .id_table = rt274_i2c_id,
1221};
1222
1223module_i2c_driver(rt274_i2c_driver);
1224
1225MODULE_DESCRIPTION("ASoC RT274 driver");
1226MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1227MODULE_LICENSE("GPL v2");
1228
