1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Include file for Alchemy Semiconductor's Au1k CPU. 5 * 6 * Copyright 2004 Embedded Edge, LLC 7 * dan@embeddededge.com 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29 30/* Specifics for the Au1xxx Programmable Serial Controllers, first 31 * seen in the AU1550 part. 32 */ 33#ifndef _AU1000_PSC_H_ 34#define _AU1000_PSC_H_ 35 36/* 37 * The PSC select and control registers are common to all protocols. 38 */ 39#define PSC_SEL_OFFSET 0x00000000 40#define PSC_CTRL_OFFSET 0x00000004 41 42#define PSC_SEL_CLK_MASK (3 << 4) 43#define PSC_SEL_CLK_INTCLK (0 << 4) 44#define PSC_SEL_CLK_EXTCLK (1 << 4) 45#define PSC_SEL_CLK_SERCLK (2 << 4) 46 47#define PSC_SEL_PS_MASK 0x00000007 48#define PSC_SEL_PS_DISABLED 0 49#define PSC_SEL_PS_SPIMODE 2 50#define PSC_SEL_PS_I2SMODE 3 51#define PSC_SEL_PS_AC97MODE 4 52#define PSC_SEL_PS_SMBUSMODE 5 53 54#define PSC_CTRL_DISABLE 0 55#define PSC_CTRL_SUSPEND 2 56#define PSC_CTRL_ENABLE 3 57 58/* AC97 Registers. */ 59#define PSC_AC97CFG_OFFSET 0x00000008 60#define PSC_AC97MSK_OFFSET 0x0000000c 61#define PSC_AC97PCR_OFFSET 0x00000010 62#define PSC_AC97STAT_OFFSET 0x00000014 63#define PSC_AC97EVNT_OFFSET 0x00000018 64#define PSC_AC97TXRX_OFFSET 0x0000001c 65#define PSC_AC97CDC_OFFSET 0x00000020 66#define PSC_AC97RST_OFFSET 0x00000024 67#define PSC_AC97GPO_OFFSET 0x00000028 68#define PSC_AC97GPI_OFFSET 0x0000002c 69 70/* AC97 Config Register. */ 71#define PSC_AC97CFG_RT_MASK (3 << 30) 72#define PSC_AC97CFG_RT_FIFO1 (0 << 30) 73#define PSC_AC97CFG_RT_FIFO2 (1 << 30) 74#define PSC_AC97CFG_RT_FIFO4 (2 << 30) 75#define PSC_AC97CFG_RT_FIFO8 (3 << 30) 76 77#define PSC_AC97CFG_TT_MASK (3 << 28) 78#define PSC_AC97CFG_TT_FIFO1 (0 << 28) 79#define PSC_AC97CFG_TT_FIFO2 (1 << 28) 80#define PSC_AC97CFG_TT_FIFO4 (2 << 28) 81#define PSC_AC97CFG_TT_FIFO8 (3 << 28) 82 83#define PSC_AC97CFG_DD_DISABLE (1 << 27) 84#define PSC_AC97CFG_DE_ENABLE (1 << 26) 85#define PSC_AC97CFG_SE_ENABLE (1 << 25) 86 87#define PSC_AC97CFG_LEN_MASK (0xf << 21) 88#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) 89#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) 90#define PSC_AC97CFG_GE_ENABLE (1) 91 92/* Enable slots 3-12. */ 93#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) 94#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) 95 96/* 97 * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. 98 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the 99 * arithmetic in the macro. 100 */ 101#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) 102#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) 103 104/* AC97 Mask Register. */ 105#define PSC_AC97MSK_GR (1 << 25) 106#define PSC_AC97MSK_CD (1 << 24) 107#define PSC_AC97MSK_RR (1 << 13) 108#define PSC_AC97MSK_RO (1 << 12) 109#define PSC_AC97MSK_RU (1 << 11) 110#define PSC_AC97MSK_TR (1 << 10) 111#define PSC_AC97MSK_TO (1 << 9) 112#define PSC_AC97MSK_TU (1 << 8) 113#define PSC_AC97MSK_RD (1 << 5) 114#define PSC_AC97MSK_TD (1 << 4) 115#define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ 116 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ 117 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ 118 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ 119 PSC_AC97MSK_RD | PSC_AC97MSK_TD) 120 121/* AC97 Protocol Control Register. */ 122#define PSC_AC97PCR_RC (1 << 6) 123#define PSC_AC97PCR_RP (1 << 5) 124#define PSC_AC97PCR_RS (1 << 4) 125#define PSC_AC97PCR_TC (1 << 2) 126#define PSC_AC97PCR_TP (1 << 1) 127#define PSC_AC97PCR_TS (1 << 0) 128 129/* AC97 Status register (read only). */ 130#define PSC_AC97STAT_CB (1 << 26) 131#define PSC_AC97STAT_CP (1 << 25) 132#define PSC_AC97STAT_CR (1 << 24) 133#define PSC_AC97STAT_RF (1 << 13) 134#define PSC_AC97STAT_RE (1 << 12) 135#define PSC_AC97STAT_RR (1 << 11) 136#define PSC_AC97STAT_TF (1 << 10) 137#define PSC_AC97STAT_TE (1 << 9) 138#define PSC_AC97STAT_TR (1 << 8) 139#define PSC_AC97STAT_RB (1 << 5) 140#define PSC_AC97STAT_TB (1 << 4) 141#define PSC_AC97STAT_DI (1 << 2) 142#define PSC_AC97STAT_DR (1 << 1) 143#define PSC_AC97STAT_SR (1 << 0) 144 145/* AC97 Event Register. */ 146#define PSC_AC97EVNT_GR (1 << 25) 147#define PSC_AC97EVNT_CD (1 << 24) 148#define PSC_AC97EVNT_RR (1 << 13) 149#define PSC_AC97EVNT_RO (1 << 12) 150#define PSC_AC97EVNT_RU (1 << 11) 151#define PSC_AC97EVNT_TR (1 << 10) 152#define PSC_AC97EVNT_TO (1 << 9) 153#define PSC_AC97EVNT_TU (1 << 8) 154#define PSC_AC97EVNT_RD (1 << 5) 155#define PSC_AC97EVNT_TD (1 << 4) 156 157/* CODEC Command Register. */ 158#define PSC_AC97CDC_RD (1 << 25) 159#define PSC_AC97CDC_ID_MASK (3 << 23) 160#define PSC_AC97CDC_INDX_MASK (0x7f << 16) 161#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) 162#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) 163 164/* AC97 Reset Control Register. */ 165#define PSC_AC97RST_RST (1 << 1) 166#define PSC_AC97RST_SNC (1 << 0) 167 168/* PSC in I2S Mode. */ 169typedef struct psc_i2s { 170 u32 psc_sel; 171 u32 psc_ctrl; 172 u32 psc_i2scfg; 173 u32 psc_i2smsk; 174 u32 psc_i2spcr; 175 u32 psc_i2sstat; 176 u32 psc_i2sevent; 177 u32 psc_i2stxrx; 178 u32 psc_i2sudf; 179} psc_i2s_t; 180 181#define PSC_I2SCFG_OFFSET 0x08 182#define PSC_I2SMASK_OFFSET 0x0C 183#define PSC_I2SPCR_OFFSET 0x10 184#define PSC_I2SSTAT_OFFSET 0x14 185#define PSC_I2SEVENT_OFFSET 0x18 186#define PSC_I2SRXTX_OFFSET 0x1C 187#define PSC_I2SUDF_OFFSET 0x20 188 189/* I2S Config Register. */ 190#define PSC_I2SCFG_RT_MASK (3 << 30) 191#define PSC_I2SCFG_RT_FIFO1 (0 << 30) 192#define PSC_I2SCFG_RT_FIFO2 (1 << 30) 193#define PSC_I2SCFG_RT_FIFO4 (2 << 30) 194#define PSC_I2SCFG_RT_FIFO8 (3 << 30) 195 196#define PSC_I2SCFG_TT_MASK (3 << 28) 197#define PSC_I2SCFG_TT_FIFO1 (0 << 28) 198#define PSC_I2SCFG_TT_FIFO2 (1 << 28) 199#define PSC_I2SCFG_TT_FIFO4 (2 << 28) 200#define PSC_I2SCFG_TT_FIFO8 (3 << 28) 201 202#define PSC_I2SCFG_DD_DISABLE (1 << 27) 203#define PSC_I2SCFG_DE_ENABLE (1 << 26) 204#define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) 205#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) 206#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) 207#define PSC_I2SCFG_WI (1 << 15) 208 209#define PSC_I2SCFG_DIV_MASK (3 << 13) 210#define PSC_I2SCFG_DIV2 (0 << 13) 211#define PSC_I2SCFG_DIV4 (1 << 13) 212#define PSC_I2SCFG_DIV8 (2 << 13) 213#define PSC_I2SCFG_DIV16 (3 << 13) 214 215#define PSC_I2SCFG_BI (1 << 12) 216#define PSC_I2SCFG_BUF (1 << 11) 217#define PSC_I2SCFG_MLJ (1 << 10) 218#define PSC_I2SCFG_XM (1 << 9) 219 220/* The word length equation is simply LEN+1. */ 221#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) 222#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) 223 224#define PSC_I2SCFG_LB (1 << 2) 225#define PSC_I2SCFG_MLF (1 << 1) 226#define PSC_I2SCFG_MS (1 << 0) 227 228/* I2S Mask Register. */ 229#define PSC_I2SMSK_RR (1 << 13) 230#define PSC_I2SMSK_RO (1 << 12) 231#define PSC_I2SMSK_RU (1 << 11) 232#define PSC_I2SMSK_TR (1 << 10) 233#define PSC_I2SMSK_TO (1 << 9) 234#define PSC_I2SMSK_TU (1 << 8) 235#define PSC_I2SMSK_RD (1 << 5) 236#define PSC_I2SMSK_TD (1 << 4) 237#define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \ 238 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ 239 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ 240 PSC_I2SMSK_RD | PSC_I2SMSK_TD) 241 242/* I2S Protocol Control Register. */ 243#define PSC_I2SPCR_RC (1 << 6) 244#define PSC_I2SPCR_RP (1 << 5) 245#define PSC_I2SPCR_RS (1 << 4) 246#define PSC_I2SPCR_TC (1 << 2) 247#define PSC_I2SPCR_TP (1 << 1) 248#define PSC_I2SPCR_TS (1 << 0) 249 250/* I2S Status register (read only). */ 251#define PSC_I2SSTAT_RF (1 << 13) 252#define PSC_I2SSTAT_RE (1 << 12) 253#define PSC_I2SSTAT_RR (1 << 11) 254#define PSC_I2SSTAT_TF (1 << 10) 255#define PSC_I2SSTAT_TE (1 << 9) 256#define PSC_I2SSTAT_TR (1 << 8) 257#define PSC_I2SSTAT_RB (1 << 5) 258#define PSC_I2SSTAT_TB (1 << 4) 259#define PSC_I2SSTAT_DI (1 << 2) 260#define PSC_I2SSTAT_DR (1 << 1) 261#define PSC_I2SSTAT_SR (1 << 0) 262 263/* I2S Event Register. */ 264#define PSC_I2SEVNT_RR (1 << 13) 265#define PSC_I2SEVNT_RO (1 << 12) 266#define PSC_I2SEVNT_RU (1 << 11) 267#define PSC_I2SEVNT_TR (1 << 10) 268#define PSC_I2SEVNT_TO (1 << 9) 269#define PSC_I2SEVNT_TU (1 << 8) 270#define PSC_I2SEVNT_RD (1 << 5) 271#define PSC_I2SEVNT_TD (1 << 4) 272 273/* PSC in SPI Mode. */ 274typedef struct psc_spi { 275 u32 psc_sel; 276 u32 psc_ctrl; 277 u32 psc_spicfg; 278 u32 psc_spimsk; 279 u32 psc_spipcr; 280 u32 psc_spistat; 281 u32 psc_spievent; 282 u32 psc_spitxrx; 283} psc_spi_t; 284 285/* SPI Config Register. */ 286#define PSC_SPICFG_RT_MASK (3 << 30) 287#define PSC_SPICFG_RT_FIFO1 (0 << 30) 288#define PSC_SPICFG_RT_FIFO2 (1 << 30) 289#define PSC_SPICFG_RT_FIFO4 (2 << 30) 290#define PSC_SPICFG_RT_FIFO8 (3 << 30) 291 292#define PSC_SPICFG_TT_MASK (3 << 28) 293#define PSC_SPICFG_TT_FIFO1 (0 << 28) 294#define PSC_SPICFG_TT_FIFO2 (1 << 28) 295#define PSC_SPICFG_TT_FIFO4 (2 << 28) 296#define PSC_SPICFG_TT_FIFO8 (3 << 28) 297 298#define PSC_SPICFG_DD_DISABLE (1 << 27) 299#define PSC_SPICFG_DE_ENABLE (1 << 26) 300#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) 301#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) 302 303#define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) 304#define PSC_SPICFG_DIV2 0 305#define PSC_SPICFG_DIV4 1 306#define PSC_SPICFG_DIV8 2 307#define PSC_SPICFG_DIV16 3 308 309#define PSC_SPICFG_BI (1 << 12) 310#define PSC_SPICFG_PSE (1 << 11) 311#define PSC_SPICFG_CGE (1 << 10) 312#define PSC_SPICFG_CDE (1 << 9) 313 314#define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) 315#define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) 316 317#define PSC_SPICFG_LB (1 << 3) 318#define PSC_SPICFG_MLF (1 << 1) 319#define PSC_SPICFG_MO (1 << 0) 320 321/* SPI Mask Register. */ 322#define PSC_SPIMSK_MM (1 << 16) 323#define PSC_SPIMSK_RR (1 << 13) 324#define PSC_SPIMSK_RO (1 << 12) 325#define PSC_SPIMSK_RU (1 << 11) 326#define PSC_SPIMSK_TR (1 << 10) 327#define PSC_SPIMSK_TO (1 << 9) 328#define PSC_SPIMSK_TU (1 << 8) 329#define PSC_SPIMSK_SD (1 << 5) 330#define PSC_SPIMSK_MD (1 << 4) 331#define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ 332 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ 333 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ 334 PSC_SPIMSK_MD) 335 336/* SPI Protocol Control Register. */ 337#define PSC_SPIPCR_RC (1 << 6) 338#define PSC_SPIPCR_SP (1 << 5) 339#define PSC_SPIPCR_SS (1 << 4) 340#define PSC_SPIPCR_TC (1 << 2) 341#define PSC_SPIPCR_MS (1 << 0) 342 343/* SPI Status register (read only). */ 344#define PSC_SPISTAT_RF (1 << 13) 345#define PSC_SPISTAT_RE (1 << 12) 346#define PSC_SPISTAT_RR (1 << 11) 347#define PSC_SPISTAT_TF (1 << 10) 348#define PSC_SPISTAT_TE (1 << 9) 349#define PSC_SPISTAT_TR (1 << 8) 350#define PSC_SPISTAT_SB (1 << 5) 351#define PSC_SPISTAT_MB (1 << 4) 352#define PSC_SPISTAT_DI (1 << 2) 353#define PSC_SPISTAT_DR (1 << 1) 354#define PSC_SPISTAT_SR (1 << 0) 355 356/* SPI Event Register. */ 357#define PSC_SPIEVNT_MM (1 << 16) 358#define PSC_SPIEVNT_RR (1 << 13) 359#define PSC_SPIEVNT_RO (1 << 12) 360#define PSC_SPIEVNT_RU (1 << 11) 361#define PSC_SPIEVNT_TR (1 << 10) 362#define PSC_SPIEVNT_TO (1 << 9) 363#define PSC_SPIEVNT_TU (1 << 8) 364#define PSC_SPIEVNT_SD (1 << 5) 365#define PSC_SPIEVNT_MD (1 << 4) 366 367/* Transmit register control. */ 368#define PSC_SPITXRX_LC (1 << 29) 369#define PSC_SPITXRX_SR (1 << 28) 370 371/* SMBus Config Register. */ 372#define PSC_SMBCFG_RT_MASK (3 << 30) 373#define PSC_SMBCFG_RT_FIFO1 (0 << 30) 374#define PSC_SMBCFG_RT_FIFO2 (1 << 30) 375#define PSC_SMBCFG_RT_FIFO4 (2 << 30) 376#define PSC_SMBCFG_RT_FIFO8 (3 << 30) 377 378#define PSC_SMBCFG_TT_MASK (3 << 28) 379#define PSC_SMBCFG_TT_FIFO1 (0 << 28) 380#define PSC_SMBCFG_TT_FIFO2 (1 << 28) 381#define PSC_SMBCFG_TT_FIFO4 (2 << 28) 382#define PSC_SMBCFG_TT_FIFO8 (3 << 28) 383 384#define PSC_SMBCFG_DD_DISABLE (1 << 27) 385#define PSC_SMBCFG_DE_ENABLE (1 << 26) 386 387#define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) 388#define PSC_SMBCFG_DIV2 0 389#define PSC_SMBCFG_DIV4 1 390#define PSC_SMBCFG_DIV8 2 391#define PSC_SMBCFG_DIV16 3 392 393#define PSC_SMBCFG_GCE (1 << 9) 394#define PSC_SMBCFG_SFM (1 << 8) 395 396#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) 397 398/* SMBus Mask Register. */ 399#define PSC_SMBMSK_DN (1 << 30) 400#define PSC_SMBMSK_AN (1 << 29) 401#define PSC_SMBMSK_AL (1 << 28) 402#define PSC_SMBMSK_RR (1 << 13) 403#define PSC_SMBMSK_RO (1 << 12) 404#define PSC_SMBMSK_RU (1 << 11) 405#define PSC_SMBMSK_TR (1 << 10) 406#define PSC_SMBMSK_TO (1 << 9) 407#define PSC_SMBMSK_TU (1 << 8) 408#define PSC_SMBMSK_SD (1 << 5) 409#define PSC_SMBMSK_MD (1 << 4) 410#define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ 411 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ 412 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ 413 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ 414 PSC_SMBMSK_MD) 415 416/* SMBus Protocol Control Register. */ 417#define PSC_SMBPCR_DC (1 << 2) 418#define PSC_SMBPCR_MS (1 << 0) 419 420/* SMBus Status register (read only). */ 421#define PSC_SMBSTAT_BB (1 << 28) 422#define PSC_SMBSTAT_RF (1 << 13) 423#define PSC_SMBSTAT_RE (1 << 12) 424#define PSC_SMBSTAT_RR (1 << 11) 425#define PSC_SMBSTAT_TF (1 << 10) 426#define PSC_SMBSTAT_TE (1 << 9) 427#define PSC_SMBSTAT_TR (1 << 8) 428#define PSC_SMBSTAT_SB (1 << 5) 429#define PSC_SMBSTAT_MB (1 << 4) 430#define PSC_SMBSTAT_DI (1 << 2) 431#define PSC_SMBSTAT_DR (1 << 1) 432#define PSC_SMBSTAT_SR (1 << 0) 433 434/* SMBus Event Register. */ 435#define PSC_SMBEVNT_DN (1 << 30) 436#define PSC_SMBEVNT_AN (1 << 29) 437#define PSC_SMBEVNT_AL (1 << 28) 438#define PSC_SMBEVNT_RR (1 << 13) 439#define PSC_SMBEVNT_RO (1 << 12) 440#define PSC_SMBEVNT_RU (1 << 11) 441#define PSC_SMBEVNT_TR (1 << 10) 442#define PSC_SMBEVNT_TO (1 << 9) 443#define PSC_SMBEVNT_TU (1 << 8) 444#define PSC_SMBEVNT_SD (1 << 5) 445#define PSC_SMBEVNT_MD (1 << 4) 446#define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ 447 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ 448 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ 449 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ 450 PSC_SMBEVNT_MD) 451 452/* Transmit register control. */ 453#define PSC_SMBTXRX_RSR (1 << 28) 454#define PSC_SMBTXRX_STP (1 << 29) 455#define PSC_SMBTXRX_DATAMASK 0xff 456 457/* SMBus protocol timers register. */ 458#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) 459#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) 460#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) 461#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) 462#define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) 463#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) 464#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) 465 466#endif /* _AU1000_PSC_H_ */ 467