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12#ifndef _ASM_PCI_BRIDGE_H
13#define _ASM_PCI_BRIDGE_H
14
15#include <linux/types.h>
16#include <linux/pci.h>
17#include <asm/xtalk/xwidget.h>
18#include <asm/sn/types.h>
19
20
21
22#define IOPFNSHIFT 12
23
24#define IOPGSIZE (1 << IOPFNSHIFT)
25#define IOPG(x) ((x) >> IOPFNSHIFT)
26#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
27
28
29
30#define BRIDGE_ATE_RAM_SIZE 0x00000400
31
32#define BRIDGE_CONFIG_BASE 0x20000
33#define BRIDGE_CONFIG1_BASE 0x28000
34#define BRIDGE_CONFIG_END 0x30000
35#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
36
37#define BRIDGE_SSRAM_512K 0x00080000
38#define BRIDGE_SSRAM_128K 0x00020000
39#define BRIDGE_SSRAM_64K 0x00010000
40#define BRIDGE_SSRAM_0K 0x00000000
41
42
43
44
45
46#ifndef __ASSEMBLY__
47
48#define ATE_V 0x01
49#define ATE_CO 0x02
50#define ATE_PREC 0x04
51#define ATE_PREF 0x08
52#define ATE_BAR 0x10
53
54#define ATE_PFNSHIFT 12
55#define ATE_TIDSHIFT 8
56#define ATE_RMFSHIFT 48
57
58#define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
59 ((xid)<<ATE_TIDSHIFT) | \
60 (attr))
61
62#define BRIDGE_INTERNAL_ATES 128
63
64
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66
67
68
69
70
71struct bridge_regs {
72
73
74
75 widget_cfg_t b_widget;
76
77
78
79#define b_wid_id b_widget.w_id
80#define b_wid_stat b_widget.w_status
81#define b_wid_err_upper b_widget.w_err_upper_addr
82#define b_wid_err_lower b_widget.w_err_lower_addr
83#define b_wid_control b_widget.w_control
84#define b_wid_req_timeout b_widget.w_req_timeout
85#define b_wid_int_upper b_widget.w_intdest_upper_addr
86#define b_wid_int_lower b_widget.w_intdest_lower_addr
87#define b_wid_err_cmdword b_widget.w_err_cmd_word
88#define b_wid_llp b_widget.w_llp_cfg
89#define b_wid_tflush b_widget.w_tflush
90
91
92 u32 _pad_000058;
93 u32 b_wid_aux_err;
94 u32 _pad_000060;
95 u32 b_wid_resp_upper;
96 u32 _pad_000068;
97 u32 b_wid_resp_lower;
98 u32 _pad_000070;
99 u32 b_wid_tst_pin_ctrl;
100 u32 _pad_000078[2];
101
102
103 u32 _pad_000080;
104 u32 b_dir_map;
105 u32 _pad_000088[2];
106
107
108 u32 _pad_000090;
109 u32 b_ram_perr;
110 u32 _pad_000098[2];
111
112
113 u32 _pad_0000A0;
114 u32 b_arb;
115 u32 _pad_0000A8[2];
116
117
118 u32 _pad_0000B0;
119 u32 b_nic;
120 u32 _pad_0000B8[2];
121
122
123 u32 _pad_0000C0;
124 u32 b_bus_timeout;
125#define b_pci_bus_timeout b_bus_timeout
126
127 u32 _pad_0000C8;
128 u32 b_pci_cfg;
129 u32 _pad_0000D0;
130 u32 b_pci_err_upper;
131 u32 _pad_0000D8;
132 u32 b_pci_err_lower;
133 u32 _pad_0000E0[8];
134#define b_gio_err_lower b_pci_err_lower
135#define b_gio_err_upper b_pci_err_upper
136
137
138 u32 _pad_000100;
139 u32 b_int_status;
140 u32 _pad_000108;
141 u32 b_int_enable;
142 u32 _pad_000110;
143 u32 b_int_rst_stat;
144 u32 _pad_000118;
145 u32 b_int_mode;
146 u32 _pad_000120;
147 u32 b_int_device;
148 u32 _pad_000128;
149 u32 b_int_host_err;
150
151 struct {
152 u32 __pad;
153 u32 addr;
154 } b_int_addr[8];
155
156 u32 _pad_000170[36];
157
158
159 struct {
160 u32 __pad;
161 u32 reg;
162 } b_device[8];
163
164 struct {
165 u32 __pad;
166 u32 reg;
167 } b_wr_req_buf[8];
168
169 struct {
170 u32 __pad;
171 u32 reg;
172 } b_rrb_map[2];
173#define b_even_resp b_rrb_map[0].reg
174#define b_odd_resp b_rrb_map[1].reg
175
176 u32 _pad_000290;
177 u32 b_resp_status;
178 u32 _pad_000298;
179 u32 b_resp_clear;
180
181 u32 _pad_0002A0[24];
182
183 char _pad_000300[0x10000 - 0x000300];
184
185
186 union {
187 u64 wr;
188 struct {
189 u32 _p_pad;
190 u32 rd;
191 } hi;
192 } b_int_ate_ram[128];
193
194 char _pad_010400[0x11000 - 0x010400];
195
196
197 struct {
198 u32 _p_pad;
199 u32 rd;
200 } b_int_ate_ram_lo[128];
201
202 char _pad_011400[0x20000 - 0x011400];
203
204
205 union {
206 u8 c[0x1000 / 1];
207 u16 s[0x1000 / 2];
208 u32 l[0x1000 / 4];
209 u64 d[0x1000 / 8];
210 union {
211 u8 c[0x100 / 1];
212 u16 s[0x100 / 2];
213 u32 l[0x100 / 4];
214 u64 d[0x100 / 8];
215 } f[8];
216 } b_type0_cfg_dev[8];
217
218
219 union {
220 u8 c[0x1000 / 1];
221 u16 s[0x1000 / 2];
222 u32 l[0x1000 / 4];
223 u64 d[0x1000 / 8];
224 } b_type1_cfg;
225
226 char _pad_029000[0x007000];
227
228
229 union {
230 u8 c[8 / 1];
231 u16 s[8 / 2];
232 u32 l[8 / 4];
233 u64 d[8 / 8];
234 } b_pci_iack;
235
236 u8 _pad_030007[0x04fff8];
237
238
239 u64 b_ext_ate_ram[0x10000];
240
241
242 char _pad_100000[0x200000-0x100000];
243
244
245 union {
246 u8 c[0x100000 / 1];
247 u16 s[0x100000 / 2];
248 u32 l[0x100000 / 4];
249 u64 d[0x100000 / 8];
250 } b_devio_raw[10];
251
252
253
254
255
256#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
257
258
259 union {
260 u8 c[0x400000 / 1];
261 u16 s[0x400000 / 2];
262 u32 l[0x400000 / 4];
263 u64 d[0x400000 / 8];
264 } b_external_flash;
265};
266
267
268
269
270
271struct bridge_err_cmdword {
272 union {
273 u32 cmd_word;
274 struct {
275 u32 didn:4,
276 sidn:4,
277 pactyp:4,
278 tnum:5,
279 coh:1,
280 ds:2,
281 gbr:1,
282 vbpm:1,
283 error:1,
284 barr:1,
285 rsvd:8;
286 } berr_st;
287 } berr_un;
288};
289
290#define berr_field berr_un.berr_st
291#endif
292
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299
300
301#define BRIDGE_WID_ID WIDGET_ID
302#define BRIDGE_WID_STAT WIDGET_STATUS
303#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
304#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
305#define BRIDGE_WID_CONTROL WIDGET_CONTROL
306#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
307#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
308#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
309#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
310#define BRIDGE_WID_LLP WIDGET_LLP_CFG
311#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
312
313#define BRIDGE_WID_AUX_ERR 0x00005C
314#define BRIDGE_WID_RESP_UPPER 0x000064
315#define BRIDGE_WID_RESP_LOWER 0x00006C
316#define BRIDGE_WID_TST_PIN_CTRL 0x000074
317
318#define BRIDGE_DIR_MAP 0x000084
319
320#define BRIDGE_RAM_PERR 0x000094
321
322#define BRIDGE_ARB 0x0000A4
323
324#define BRIDGE_NIC 0x0000B4
325
326#define BRIDGE_BUS_TIMEOUT 0x0000C4
327#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
328#define BRIDGE_PCI_CFG 0x0000CC
329#define BRIDGE_PCI_ERR_UPPER 0x0000D4
330#define BRIDGE_PCI_ERR_LOWER 0x0000DC
331
332#define BRIDGE_INT_STATUS 0x000104
333#define BRIDGE_INT_ENABLE 0x00010C
334#define BRIDGE_INT_RST_STAT 0x000114
335#define BRIDGE_INT_MODE 0x00011C
336#define BRIDGE_INT_DEVICE 0x000124
337#define BRIDGE_INT_HOST_ERR 0x00012C
338
339#define BRIDGE_INT_ADDR0 0x000134
340#define BRIDGE_INT_ADDR_OFF 0x000008
341#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
342
343#define BRIDGE_DEVICE0 0x000204
344#define BRIDGE_DEVICE_OFF 0x000008
345#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
346
347#define BRIDGE_WR_REQ_BUF0 0x000244
348#define BRIDGE_WR_REQ_BUF_OFF 0x000008
349#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
350
351#define BRIDGE_EVEN_RESP 0x000284
352#define BRIDGE_ODD_RESP 0x00028C
353
354#define BRIDGE_RESP_STATUS 0x000294
355#define BRIDGE_RESP_CLEAR 0x00029C
356
357
358
359#define BRIDGE_ATE_RAM 0x00010000
360
361#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
362#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
363#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
364#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\
365 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
366#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\
367 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
368 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
369
370#define BRIDGE_TYPE1_CFG 0x00028000
371
372#define BRIDGE_PCI_IACK 0x00030000
373#define BRIDGE_EXT_SSRAM 0x00080000
374
375
376
377#define BRIDGE_DEV_CNT 8
378#define BRIDGE_DEVIO0 0x00200000
379#define BRIDGE_DEVIO1 0x00400000
380#define BRIDGE_DEVIO2 0x00600000
381#define BRIDGE_DEVIO_OFF 0x00100000
382
383#define BRIDGE_DEVIO_2MB 0x00200000
384#define BRIDGE_DEVIO_1MB 0x00100000
385
386#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
387
388#define BRIDGE_EXTERNAL_FLASH 0x00C00000
389
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393
394
395#define BRIDGE_WIDGET_PART_NUM 0xc002
396#define XBRIDGE_WIDGET_PART_NUM 0xd002
397
398
399#define BRIDGE_WIDGET_MFGR_NUM 0x036
400#define XBRIDGE_WIDGET_MFGR_NUM 0x024
401
402
403#define BRIDGE_REV_A 0x1
404#define BRIDGE_REV_B 0x2
405#define BRIDGE_REV_C 0x3
406#define BRIDGE_REV_D 0x4
407
408
409
410#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
411#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
412#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
413#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
414#define BRIDGE_STAT_PENDING (0x1F << 0)
415
416
417#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
418#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
419#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
420#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
421#define BRIDGE_CTRL_RST(n) ((n) << 24)
422#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
423#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
424#define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
425#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
426#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
427#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
428#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
429#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
430#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
431#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
432#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
433#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
434#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
435#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
436#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
437#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
438#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
439#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
440#define BRIDGE_CTRL_SYS_END (0x1 << 9)
441#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
442#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
443#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
444#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
445
446
447#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
448#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
449#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
450#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
451#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
452
453#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \
454 (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
455 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
456
457#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \
458 (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
459 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
460
461
462#define BRIDGE_DIRMAP_W_ID_SHFT 20
463#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
464#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
465#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
466#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
467#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
468
469
470#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
471#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
472#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
473#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
474#define BRIDGE_ARB_FREEZE_GNT (1 << 6)
475#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
476#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
477#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
478#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
479#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
480#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
481
482
483#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
484#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
485#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
486#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
487#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
488
489
490#define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
491#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
492#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
493#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
494#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
495#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
496#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
497#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
498#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
499#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
500#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
501#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
502#define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
503#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
504#define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
505#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
506#define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
507#define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
508#define BRIDGE_ISR_PCI_SERR (0x1 << 13)
509#define BRIDGE_ISR_PCI_PERR (0x1 << 12)
510#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
511#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
512#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
513#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
514#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
515#define BRIDGE_ISR_INT_MSK (0xff << 0)
516#define BRIDGE_ISR_INT(x) (0x1 << (x))
517
518#define BRIDGE_ISR_LINK_ERROR \
519 (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \
520 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \
521 BRIDGE_ISR_LLP_TCTY)
522
523#define BRIDGE_ISR_PCIBUS_PIOERR \
524 (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
525
526#define BRIDGE_ISR_PCIBUS_ERROR \
527 (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \
528 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \
529 BRIDGE_ISR_PCI_PARITY)
530
531#define BRIDGE_ISR_XTALK_ERROR \
532 (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
533 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \
534 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \
535 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \
536 BRIDGE_ISR_UNEXP_RESP)
537
538#define BRIDGE_ISR_ERRORS \
539 (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \
540 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
541 BRIDGE_ISR_PMU_ESIZE_FAULT)
542
543
544
545
546#define BRIDGE_ISR_ERROR_FATAL \
547 ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
548 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
549
550#define BRIDGE_ISR_ERROR_DUMP \
551 (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \
552 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
553
554
555#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
556#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
557#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
558#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
559#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
560#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
561#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
562#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
563#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
564#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
565#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
566#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
567#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
568#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
569#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
570#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
571#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
572#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
573#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
574#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
575#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
576#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
577#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
578#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
579#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
580#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
581
582
583#define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
584#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
585#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
586#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
587#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
588#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
589#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
590#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
591#define BRIDGE_IRR_ALL_CLR 0x7f
592
593#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \
594 BRIDGE_ISR_XREQ_FIFO_OFLOW)
595#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \
596 BRIDGE_ISR_RESP_XTLK_ERR | \
597 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
598#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \
599 BRIDGE_ISR_BAD_XREQ_PKT | \
600 BRIDGE_ISR_REQ_XTLK_ERR | \
601 BRIDGE_ISR_INVLD_ADDR)
602#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \
603 BRIDGE_ISR_LLP_REC_CBERR | \
604 BRIDGE_ISR_LLP_RCTY | \
605 BRIDGE_ISR_LLP_TX_RETRY | \
606 BRIDGE_ISR_LLP_TCTY)
607#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \
608 BRIDGE_ISR_PMU_ESIZE_FAULT)
609#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \
610 BRIDGE_ISR_PCI_PARITY | \
611 BRIDGE_ISR_PCI_SERR | \
612 BRIDGE_ISR_PCI_PERR | \
613 BRIDGE_ISR_PCI_MST_TIMEOUT | \
614 BRIDGE_ISR_PCI_RETRY_CNT)
615
616#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \
617 BRIDGE_ISR_GIO_MST_TIMEOUT)
618
619
620#define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
621#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
622#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
623
624
625#define BRIDGE_INT_ADDR_HOST 0x0003FF00
626#define BRIDGE_INT_ADDR_FLD 0x000000FF
627
628#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
629#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
630#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
631
632#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
633
634
635
636
637
638#define BRIDGE_INT_ADDR_NASID_SHFT 8
639
640
641
642
643
644#define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
645#define BRIDGE_INT_ADDR_DEST_MEM 0
646#define BRIDGE_INT_ADDR_MASK (1 << 17)
647
648
649#define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
650#define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
651#define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
652#define BRIDGE_DEV_VIRTUAL_EN 0x02000000
653#define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
654#define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
655#define BRIDGE_DEV_DEV_SIZE 0x00400000
656#define BRIDGE_DEV_RT 0x00200000
657#define BRIDGE_DEV_SWAP_PMU 0x00100000
658#define BRIDGE_DEV_SWAP_DIR 0x00080000
659#define BRIDGE_DEV_PREF 0x00040000
660#define BRIDGE_DEV_PRECISE 0x00020000
661#define BRIDGE_DEV_COH 0x00010000
662#define BRIDGE_DEV_BARRIER 0x00008000
663#define BRIDGE_DEV_GBR 0x00004000
664#define BRIDGE_DEV_DEV_SWAP 0x00002000
665#define BRIDGE_DEV_DEV_IO_MEM 0x00001000
666#define BRIDGE_DEV_OFF_MASK 0x00000fff
667#define BRIDGE_DEV_OFF_ADDR_SHFT 20
668
669#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \
670 BRIDGE_DEV_SWAP_PMU)
671#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
672 BRIDGE_DEV_SWAP_DIR | \
673 BRIDGE_DEV_PREF | \
674 BRIDGE_DEV_PRECISE | \
675 BRIDGE_DEV_COH | \
676 BRIDGE_DEV_BARRIER)
677#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
678 BRIDGE_DEV_SWAP_DIR | \
679 BRIDGE_DEV_COH | \
680 BRIDGE_DEV_BARRIER)
681
682
683#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
684#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
685#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
686#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
687#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
688#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
689
690
691#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
692
693
694#define BRIDGE_CREDIT 3
695
696
697#define BRIDGE_RRB_EN 0x8
698#define BRIDGE_RRB_DEV 0x7
699#define BRIDGE_RRB_VDEV 0x4
700#define BRIDGE_RRB_PDEV 0x3
701
702
703#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
704#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
705
706
707#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
708
709
710#define XBOX_BRIDGE_WID 8
711#define FLASH_PROM1_BASE 0xE00000
712#define XBOX_RPS_EXISTS 1 << 6
713#define XBOX_RPS_FAIL 1 << 4
714
715
716
717
718
719
720
721
722#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
723#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
724#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
725#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
726#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
727#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
728
729
730#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
731#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
732#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
733#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
734
735
736#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
737#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
738#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
739#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
740#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
741#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
742
743
744
745
746
747#define BRIDGE_LOCAL_BASE 0
748#define BRIDGE_DMA_MAPPED_BASE 0x40000000
749#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
750#define BRIDGE_DMA_DIRECT_BASE 0x80000000
751#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
752
753#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
754
755
756#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
757#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
758
759#define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
760#define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && \
761 (ulong_t)(x) >= PCI32_MAPPED_BASE)
762#define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
763#define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
764
765
766
767
768
769#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
770#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
771
772#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
773
774
775#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
776#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
777
778#define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
779#define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && \
780 (ulong_t)(x) >= GIO_MAPPED_BASE)
781#define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
782
783
784
785
786
787
788#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
789#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \
790 ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
791 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
792
793
794#define PCI64_ATTR_TARG_MASK 0xf000000000000000
795#define PCI64_ATTR_TARG_SHFT 60
796#define PCI64_ATTR_PREF 0x0800000000000000
797#define PCI64_ATTR_PREC 0x0400000000000000
798#define PCI64_ATTR_VIRTUAL 0x0200000000000000
799#define PCI64_ATTR_BAR 0x0100000000000000
800#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
801#define PCI64_ATTR_RMF_SHFT 48
802
803struct bridge_controller {
804 struct resource busn;
805 struct bridge_regs *base;
806 unsigned long baddr;
807 unsigned long intr_addr;
808 struct irq_domain *domain;
809 unsigned int pci_int[8];
810 nasid_t nasid;
811};
812
813#define BRIDGE_CONTROLLER(bus) \
814 ((struct bridge_controller *)((bus)->sysdata))
815
816#define bridge_read(bc, reg) __raw_readl(&bc->base->reg)
817#define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg)
818#define bridge_set(bc, reg, val) \
819 __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
820#define bridge_clr(bc, reg, val) \
821 __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
822
823#endif
824