linux/drivers/ata/sata_mv.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * sata_mv.c - Marvell SATA support
   4 *
   5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
   6 * Copyright 2005: EMC Corporation, all rights reserved.
   7 * Copyright 2005 Red Hat, Inc.  All rights reserved.
   8 *
   9 * Originally written by Brett Russ.
  10 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
  11 *
  12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  13 */
  14
  15/*
  16 * sata_mv TODO list:
  17 *
  18 * --> Develop a low-power-consumption strategy, and implement it.
  19 *
  20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
  21 *
  22 * --> [Experiment, Marvell value added] Is it possible to use target
  23 *       mode to cross-connect two Linux boxes with Marvell cards?  If so,
  24 *       creating LibATA target mode support would be very interesting.
  25 *
  26 *       Target mode, for those without docs, is the ability to directly
  27 *       connect two SATA ports.
  28 */
  29
  30/*
  31 * 80x1-B2 errata PCI#11:
  32 *
  33 * Users of the 6041/6081 Rev.B2 chips (current is C0)
  34 * should be careful to insert those cards only onto PCI-X bus #0,
  35 * and only in device slots 0..7, not higher.  The chips may not
  36 * work correctly otherwise  (note: this is a pretty rare condition).
  37 */
  38
  39#include <linux/kernel.h>
  40#include <linux/module.h>
  41#include <linux/pci.h>
  42#include <linux/init.h>
  43#include <linux/blkdev.h>
  44#include <linux/delay.h>
  45#include <linux/interrupt.h>
  46#include <linux/dmapool.h>
  47#include <linux/dma-mapping.h>
  48#include <linux/device.h>
  49#include <linux/clk.h>
  50#include <linux/phy/phy.h>
  51#include <linux/platform_device.h>
  52#include <linux/ata_platform.h>
  53#include <linux/mbus.h>
  54#include <linux/bitops.h>
  55#include <linux/gfp.h>
  56#include <linux/of.h>
  57#include <linux/of_irq.h>
  58#include <scsi/scsi_host.h>
  59#include <scsi/scsi_cmnd.h>
  60#include <scsi/scsi_device.h>
  61#include <linux/libata.h>
  62
  63#define DRV_NAME        "sata_mv"
  64#define DRV_VERSION     "1.28"
  65
  66/*
  67 * module options
  68 */
  69
  70#ifdef CONFIG_PCI
  71static int msi;
  72module_param(msi, int, S_IRUGO);
  73MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  74#endif
  75
  76static int irq_coalescing_io_count;
  77module_param(irq_coalescing_io_count, int, S_IRUGO);
  78MODULE_PARM_DESC(irq_coalescing_io_count,
  79                 "IRQ coalescing I/O count threshold (0..255)");
  80
  81static int irq_coalescing_usecs;
  82module_param(irq_coalescing_usecs, int, S_IRUGO);
  83MODULE_PARM_DESC(irq_coalescing_usecs,
  84                 "IRQ coalescing time threshold in usecs");
  85
  86enum {
  87        /* BAR's are enumerated in terms of pci_resource_start() terms */
  88        MV_PRIMARY_BAR          = 0,    /* offset 0x10: memory space */
  89        MV_IO_BAR               = 2,    /* offset 0x18: IO space */
  90        MV_MISC_BAR             = 3,    /* offset 0x1c: FLASH, NVRAM, SRAM */
  91
  92        MV_MAJOR_REG_AREA_SZ    = 0x10000,      /* 64KB */
  93        MV_MINOR_REG_AREA_SZ    = 0x2000,       /* 8KB */
  94
  95        /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
  96        COAL_CLOCKS_PER_USEC    = 150,          /* for calculating COAL_TIMEs */
  97        MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
  98        MAX_COAL_IO_COUNT       = 255,          /* completed I/O count */
  99
 100        MV_PCI_REG_BASE         = 0,
 101
 102        /*
 103         * Per-chip ("all ports") interrupt coalescing feature.
 104         * This is only for GEN_II / GEN_IIE hardware.
 105         *
 106         * Coalescing defers the interrupt until either the IO_THRESHOLD
 107         * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
 108         */
 109        COAL_REG_BASE           = 0x18000,
 110        IRQ_COAL_CAUSE          = (COAL_REG_BASE + 0x08),
 111        ALL_PORTS_COAL_IRQ      = (1 << 4),     /* all ports irq event */
 112
 113        IRQ_COAL_IO_THRESHOLD   = (COAL_REG_BASE + 0xcc),
 114        IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
 115
 116        /*
 117         * Registers for the (unused here) transaction coalescing feature:
 118         */
 119        TRAN_COAL_CAUSE_LO      = (COAL_REG_BASE + 0x88),
 120        TRAN_COAL_CAUSE_HI      = (COAL_REG_BASE + 0x8c),
 121
 122        SATAHC0_REG_BASE        = 0x20000,
 123        FLASH_CTL               = 0x1046c,
 124        GPIO_PORT_CTL           = 0x104f0,
 125        RESET_CFG               = 0x180d8,
 126
 127        MV_PCI_REG_SZ           = MV_MAJOR_REG_AREA_SZ,
 128        MV_SATAHC_REG_SZ        = MV_MAJOR_REG_AREA_SZ,
 129        MV_SATAHC_ARBTR_REG_SZ  = MV_MINOR_REG_AREA_SZ,         /* arbiter */
 130        MV_PORT_REG_SZ          = MV_MINOR_REG_AREA_SZ,
 131
 132        MV_MAX_Q_DEPTH          = 32,
 133        MV_MAX_Q_DEPTH_MASK     = MV_MAX_Q_DEPTH - 1,
 134
 135        /* CRQB needs alignment on a 1KB boundary. Size == 1KB
 136         * CRPB needs alignment on a 256B boundary. Size == 256B
 137         * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
 138         */
 139        MV_CRQB_Q_SZ            = (32 * MV_MAX_Q_DEPTH),
 140        MV_CRPB_Q_SZ            = (8 * MV_MAX_Q_DEPTH),
 141        MV_MAX_SG_CT            = 256,
 142        MV_SG_TBL_SZ            = (16 * MV_MAX_SG_CT),
 143
 144        /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
 145        MV_PORT_HC_SHIFT        = 2,
 146        MV_PORTS_PER_HC         = (1 << MV_PORT_HC_SHIFT), /* 4 */
 147        /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
 148        MV_PORT_MASK            = (MV_PORTS_PER_HC - 1),   /* 3 */
 149
 150        /* Host Flags */
 151        MV_FLAG_DUAL_HC         = (1 << 30),  /* two SATA Host Controllers */
 152
 153        MV_COMMON_FLAGS         = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
 154
 155        MV_GEN_I_FLAGS          = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
 156
 157        MV_GEN_II_FLAGS         = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
 158                                  ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
 159
 160        MV_GEN_IIE_FLAGS        = MV_GEN_II_FLAGS | ATA_FLAG_AN,
 161
 162        CRQB_FLAG_READ          = (1 << 0),
 163        CRQB_TAG_SHIFT          = 1,
 164        CRQB_IOID_SHIFT         = 6,    /* CRQB Gen-II/IIE IO Id shift */
 165        CRQB_PMP_SHIFT          = 12,   /* CRQB Gen-II/IIE PMP shift */
 166        CRQB_HOSTQ_SHIFT        = 17,   /* CRQB Gen-II/IIE HostQueTag shift */
 167        CRQB_CMD_ADDR_SHIFT     = 8,
 168        CRQB_CMD_CS             = (0x2 << 11),
 169        CRQB_CMD_LAST           = (1 << 15),
 170
 171        CRPB_FLAG_STATUS_SHIFT  = 8,
 172        CRPB_IOID_SHIFT_6       = 5,    /* CRPB Gen-II IO Id shift */
 173        CRPB_IOID_SHIFT_7       = 7,    /* CRPB Gen-IIE IO Id shift */
 174
 175        EPRD_FLAG_END_OF_TBL    = (1 << 31),
 176
 177        /* PCI interface registers */
 178
 179        MV_PCI_COMMAND          = 0xc00,
 180        MV_PCI_COMMAND_MWRCOM   = (1 << 4),     /* PCI Master Write Combining */
 181        MV_PCI_COMMAND_MRDTRIG  = (1 << 7),     /* PCI Master Read Trigger */
 182
 183        PCI_MAIN_CMD_STS        = 0xd30,
 184        STOP_PCI_MASTER         = (1 << 2),
 185        PCI_MASTER_EMPTY        = (1 << 3),
 186        GLOB_SFT_RST            = (1 << 4),
 187
 188        MV_PCI_MODE             = 0xd00,
 189        MV_PCI_MODE_MASK        = 0x30,
 190
 191        MV_PCI_EXP_ROM_BAR_CTL  = 0xd2c,
 192        MV_PCI_DISC_TIMER       = 0xd04,
 193        MV_PCI_MSI_TRIGGER      = 0xc38,
 194        MV_PCI_SERR_MASK        = 0xc28,
 195        MV_PCI_XBAR_TMOUT       = 0x1d04,
 196        MV_PCI_ERR_LOW_ADDRESS  = 0x1d40,
 197        MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
 198        MV_PCI_ERR_ATTRIBUTE    = 0x1d48,
 199        MV_PCI_ERR_COMMAND      = 0x1d50,
 200
 201        PCI_IRQ_CAUSE           = 0x1d58,
 202        PCI_IRQ_MASK            = 0x1d5c,
 203        PCI_UNMASK_ALL_IRQS     = 0x7fffff,     /* bits 22-0 */
 204
 205        PCIE_IRQ_CAUSE          = 0x1900,
 206        PCIE_IRQ_MASK           = 0x1910,
 207        PCIE_UNMASK_ALL_IRQS    = 0x40a,        /* assorted bits */
 208
 209        /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
 210        PCI_HC_MAIN_IRQ_CAUSE   = 0x1d60,
 211        PCI_HC_MAIN_IRQ_MASK    = 0x1d64,
 212        SOC_HC_MAIN_IRQ_CAUSE   = 0x20020,
 213        SOC_HC_MAIN_IRQ_MASK    = 0x20024,
 214        ERR_IRQ                 = (1 << 0),     /* shift by (2 * port #) */
 215        DONE_IRQ                = (1 << 1),     /* shift by (2 * port #) */
 216        HC0_IRQ_PEND            = 0x1ff,        /* bits 0-8 = HC0's ports */
 217        HC_SHIFT                = 9,            /* bits 9-17 = HC1's ports */
 218        DONE_IRQ_0_3            = 0x000000aa,   /* DONE_IRQ ports 0,1,2,3 */
 219        DONE_IRQ_4_7            = (DONE_IRQ_0_3 << HC_SHIFT),  /* 4,5,6,7 */
 220        PCI_ERR                 = (1 << 18),
 221        TRAN_COAL_LO_DONE       = (1 << 19),    /* transaction coalescing */
 222        TRAN_COAL_HI_DONE       = (1 << 20),    /* transaction coalescing */
 223        PORTS_0_3_COAL_DONE     = (1 << 8),     /* HC0 IRQ coalescing */
 224        PORTS_4_7_COAL_DONE     = (1 << 17),    /* HC1 IRQ coalescing */
 225        ALL_PORTS_COAL_DONE     = (1 << 21),    /* GEN_II(E) IRQ coalescing */
 226        GPIO_INT                = (1 << 22),
 227        SELF_INT                = (1 << 23),
 228        TWSI_INT                = (1 << 24),
 229        HC_MAIN_RSVD            = (0x7f << 25), /* bits 31-25 */
 230        HC_MAIN_RSVD_5          = (0x1fff << 19), /* bits 31-19 */
 231        HC_MAIN_RSVD_SOC        = (0x3fffffb << 6),     /* bits 31-9, 7-6 */
 232
 233        /* SATAHC registers */
 234        HC_CFG                  = 0x00,
 235
 236        HC_IRQ_CAUSE            = 0x14,
 237        DMA_IRQ                 = (1 << 0),     /* shift by port # */
 238        HC_COAL_IRQ             = (1 << 4),     /* IRQ coalescing */
 239        DEV_IRQ                 = (1 << 8),     /* shift by port # */
 240
 241        /*
 242         * Per-HC (Host-Controller) interrupt coalescing feature.
 243         * This is present on all chip generations.
 244         *
 245         * Coalescing defers the interrupt until either the IO_THRESHOLD
 246         * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
 247         */
 248        HC_IRQ_COAL_IO_THRESHOLD        = 0x000c,
 249        HC_IRQ_COAL_TIME_THRESHOLD      = 0x0010,
 250
 251        SOC_LED_CTRL            = 0x2c,
 252        SOC_LED_CTRL_BLINK      = (1 << 0),     /* Active LED blink */
 253        SOC_LED_CTRL_ACT_PRESENCE = (1 << 2),   /* Multiplex dev presence */
 254                                                /*  with dev activity LED */
 255
 256        /* Shadow block registers */
 257        SHD_BLK                 = 0x100,
 258        SHD_CTL_AST             = 0x20,         /* ofs from SHD_BLK */
 259
 260        /* SATA registers */
 261        SATA_STATUS             = 0x300,  /* ctrl, err regs follow status */
 262        SATA_ACTIVE             = 0x350,
 263        FIS_IRQ_CAUSE           = 0x364,
 264        FIS_IRQ_CAUSE_AN        = (1 << 9),     /* async notification */
 265
 266        LTMODE                  = 0x30c,        /* requires read-after-write */
 267        LTMODE_BIT8             = (1 << 8),     /* unknown, but necessary */
 268
 269        PHY_MODE2               = 0x330,
 270        PHY_MODE3               = 0x310,
 271
 272        PHY_MODE4               = 0x314,        /* requires read-after-write */
 273        PHY_MODE4_CFG_MASK      = 0x00000003,   /* phy internal config field */
 274        PHY_MODE4_CFG_VALUE     = 0x00000001,   /* phy internal config field */
 275        PHY_MODE4_RSVD_ZEROS    = 0x5de3fffa,   /* Gen2e always write zeros */
 276        PHY_MODE4_RSVD_ONES     = 0x00000005,   /* Gen2e always write ones */
 277
 278        SATA_IFCTL              = 0x344,
 279        SATA_TESTCTL            = 0x348,
 280        SATA_IFSTAT             = 0x34c,
 281        VENDOR_UNIQUE_FIS       = 0x35c,
 282
 283        FISCFG                  = 0x360,
 284        FISCFG_WAIT_DEV_ERR     = (1 << 8),     /* wait for host on DevErr */
 285        FISCFG_SINGLE_SYNC      = (1 << 16),    /* SYNC on DMA activation */
 286
 287        PHY_MODE9_GEN2          = 0x398,
 288        PHY_MODE9_GEN1          = 0x39c,
 289        PHYCFG_OFS              = 0x3a0,        /* only in 65n devices */
 290
 291        MV5_PHY_MODE            = 0x74,
 292        MV5_LTMODE              = 0x30,
 293        MV5_PHY_CTL             = 0x0C,
 294        SATA_IFCFG              = 0x050,
 295        LP_PHY_CTL              = 0x058,
 296        LP_PHY_CTL_PIN_PU_PLL   = (1 << 0),
 297        LP_PHY_CTL_PIN_PU_RX    = (1 << 1),
 298        LP_PHY_CTL_PIN_PU_TX    = (1 << 2),
 299        LP_PHY_CTL_GEN_TX_3G    = (1 << 5),
 300        LP_PHY_CTL_GEN_RX_3G    = (1 << 9),
 301
 302        MV_M2_PREAMP_MASK       = 0x7e0,
 303
 304        /* Port registers */
 305        EDMA_CFG                = 0,
 306        EDMA_CFG_Q_DEPTH        = 0x1f,         /* max device queue depth */
 307        EDMA_CFG_NCQ            = (1 << 5),     /* for R/W FPDMA queued */
 308        EDMA_CFG_NCQ_GO_ON_ERR  = (1 << 14),    /* continue on error */
 309        EDMA_CFG_RD_BRST_EXT    = (1 << 11),    /* read burst 512B */
 310        EDMA_CFG_WR_BUFF_LEN    = (1 << 13),    /* write buffer 512B */
 311        EDMA_CFG_EDMA_FBS       = (1 << 16),    /* EDMA FIS-Based Switching */
 312        EDMA_CFG_FBS            = (1 << 26),    /* FIS-Based Switching */
 313
 314        EDMA_ERR_IRQ_CAUSE      = 0x8,
 315        EDMA_ERR_IRQ_MASK       = 0xc,
 316        EDMA_ERR_D_PAR          = (1 << 0),     /* UDMA data parity err */
 317        EDMA_ERR_PRD_PAR        = (1 << 1),     /* UDMA PRD parity err */
 318        EDMA_ERR_DEV            = (1 << 2),     /* device error */
 319        EDMA_ERR_DEV_DCON       = (1 << 3),     /* device disconnect */
 320        EDMA_ERR_DEV_CON        = (1 << 4),     /* device connected */
 321        EDMA_ERR_SERR           = (1 << 5),     /* SError bits [WBDST] raised */
 322        EDMA_ERR_SELF_DIS       = (1 << 7),     /* Gen II/IIE self-disable */
 323        EDMA_ERR_SELF_DIS_5     = (1 << 8),     /* Gen I self-disable */
 324        EDMA_ERR_BIST_ASYNC     = (1 << 8),     /* BIST FIS or Async Notify */
 325        EDMA_ERR_TRANS_IRQ_7    = (1 << 8),     /* Gen IIE transprt layer irq */
 326        EDMA_ERR_CRQB_PAR       = (1 << 9),     /* CRQB parity error */
 327        EDMA_ERR_CRPB_PAR       = (1 << 10),    /* CRPB parity error */
 328        EDMA_ERR_INTRL_PAR      = (1 << 11),    /* internal parity error */
 329        EDMA_ERR_IORDY          = (1 << 12),    /* IORdy timeout */
 330
 331        EDMA_ERR_LNK_CTRL_RX    = (0xf << 13),  /* link ctrl rx error */
 332        EDMA_ERR_LNK_CTRL_RX_0  = (1 << 13),    /* transient: CRC err */
 333        EDMA_ERR_LNK_CTRL_RX_1  = (1 << 14),    /* transient: FIFO err */
 334        EDMA_ERR_LNK_CTRL_RX_2  = (1 << 15),    /* fatal: caught SYNC */
 335        EDMA_ERR_LNK_CTRL_RX_3  = (1 << 16),    /* transient: FIS rx err */
 336
 337        EDMA_ERR_LNK_DATA_RX    = (0xf << 17),  /* link data rx error */
 338
 339        EDMA_ERR_LNK_CTRL_TX    = (0x1f << 21), /* link ctrl tx error */
 340        EDMA_ERR_LNK_CTRL_TX_0  = (1 << 21),    /* transient: CRC err */
 341        EDMA_ERR_LNK_CTRL_TX_1  = (1 << 22),    /* transient: FIFO err */
 342        EDMA_ERR_LNK_CTRL_TX_2  = (1 << 23),    /* transient: caught SYNC */
 343        EDMA_ERR_LNK_CTRL_TX_3  = (1 << 24),    /* transient: caught DMAT */
 344        EDMA_ERR_LNK_CTRL_TX_4  = (1 << 25),    /* transient: FIS collision */
 345
 346        EDMA_ERR_LNK_DATA_TX    = (0x1f << 26), /* link data tx error */
 347
 348        EDMA_ERR_TRANS_PROTO    = (1 << 31),    /* transport protocol error */
 349        EDMA_ERR_OVERRUN_5      = (1 << 5),
 350        EDMA_ERR_UNDERRUN_5     = (1 << 6),
 351
 352        EDMA_ERR_IRQ_TRANSIENT  = EDMA_ERR_LNK_CTRL_RX_0 |
 353                                  EDMA_ERR_LNK_CTRL_RX_1 |
 354                                  EDMA_ERR_LNK_CTRL_RX_3 |
 355                                  EDMA_ERR_LNK_CTRL_TX,
 356
 357        EDMA_EH_FREEZE          = EDMA_ERR_D_PAR |
 358                                  EDMA_ERR_PRD_PAR |
 359                                  EDMA_ERR_DEV_DCON |
 360                                  EDMA_ERR_DEV_CON |
 361                                  EDMA_ERR_SERR |
 362                                  EDMA_ERR_SELF_DIS |
 363                                  EDMA_ERR_CRQB_PAR |
 364                                  EDMA_ERR_CRPB_PAR |
 365                                  EDMA_ERR_INTRL_PAR |
 366                                  EDMA_ERR_IORDY |
 367                                  EDMA_ERR_LNK_CTRL_RX_2 |
 368                                  EDMA_ERR_LNK_DATA_RX |
 369                                  EDMA_ERR_LNK_DATA_TX |
 370                                  EDMA_ERR_TRANS_PROTO,
 371
 372        EDMA_EH_FREEZE_5        = EDMA_ERR_D_PAR |
 373                                  EDMA_ERR_PRD_PAR |
 374                                  EDMA_ERR_DEV_DCON |
 375                                  EDMA_ERR_DEV_CON |
 376                                  EDMA_ERR_OVERRUN_5 |
 377                                  EDMA_ERR_UNDERRUN_5 |
 378                                  EDMA_ERR_SELF_DIS_5 |
 379                                  EDMA_ERR_CRQB_PAR |
 380                                  EDMA_ERR_CRPB_PAR |
 381                                  EDMA_ERR_INTRL_PAR |
 382                                  EDMA_ERR_IORDY,
 383
 384        EDMA_REQ_Q_BASE_HI      = 0x10,
 385        EDMA_REQ_Q_IN_PTR       = 0x14,         /* also contains BASE_LO */
 386
 387        EDMA_REQ_Q_OUT_PTR      = 0x18,
 388        EDMA_REQ_Q_PTR_SHIFT    = 5,
 389
 390        EDMA_RSP_Q_BASE_HI      = 0x1c,
 391        EDMA_RSP_Q_IN_PTR       = 0x20,
 392        EDMA_RSP_Q_OUT_PTR      = 0x24,         /* also contains BASE_LO */
 393        EDMA_RSP_Q_PTR_SHIFT    = 3,
 394
 395        EDMA_CMD                = 0x28,         /* EDMA command register */
 396        EDMA_EN                 = (1 << 0),     /* enable EDMA */
 397        EDMA_DS                 = (1 << 1),     /* disable EDMA; self-negated */
 398        EDMA_RESET              = (1 << 2),     /* reset eng/trans/link/phy */
 399
 400        EDMA_STATUS             = 0x30,         /* EDMA engine status */
 401        EDMA_STATUS_CACHE_EMPTY = (1 << 6),     /* GenIIe command cache empty */
 402        EDMA_STATUS_IDLE        = (1 << 7),     /* GenIIe EDMA enabled/idle */
 403
 404        EDMA_IORDY_TMOUT        = 0x34,
 405        EDMA_ARB_CFG            = 0x38,
 406
 407        EDMA_HALTCOND           = 0x60,         /* GenIIe halt conditions */
 408        EDMA_UNKNOWN_RSVD       = 0x6C,         /* GenIIe unknown/reserved */
 409
 410        BMDMA_CMD               = 0x224,        /* bmdma command register */
 411        BMDMA_STATUS            = 0x228,        /* bmdma status register */
 412        BMDMA_PRD_LOW           = 0x22c,        /* bmdma PRD addr 31:0 */
 413        BMDMA_PRD_HIGH          = 0x230,        /* bmdma PRD addr 63:32 */
 414
 415        /* Host private flags (hp_flags) */
 416        MV_HP_FLAG_MSI          = (1 << 0),
 417        MV_HP_ERRATA_50XXB0     = (1 << 1),
 418        MV_HP_ERRATA_50XXB2     = (1 << 2),
 419        MV_HP_ERRATA_60X1B2     = (1 << 3),
 420        MV_HP_ERRATA_60X1C0     = (1 << 4),
 421        MV_HP_GEN_I             = (1 << 6),     /* Generation I: 50xx */
 422        MV_HP_GEN_II            = (1 << 7),     /* Generation II: 60xx */
 423        MV_HP_GEN_IIE           = (1 << 8),     /* Generation IIE: 6042/7042 */
 424        MV_HP_PCIE              = (1 << 9),     /* PCIe bus/regs: 7042 */
 425        MV_HP_CUT_THROUGH       = (1 << 10),    /* can use EDMA cut-through */
 426        MV_HP_FLAG_SOC          = (1 << 11),    /* SystemOnChip, no PCI */
 427        MV_HP_QUIRK_LED_BLINK_EN = (1 << 12),   /* is led blinking enabled? */
 428        MV_HP_FIX_LP_PHY_CTL    = (1 << 13),    /* fix speed in LP_PHY_CTL ? */
 429
 430        /* Port private flags (pp_flags) */
 431        MV_PP_FLAG_EDMA_EN      = (1 << 0),     /* is EDMA engine enabled? */
 432        MV_PP_FLAG_NCQ_EN       = (1 << 1),     /* is EDMA set up for NCQ? */
 433        MV_PP_FLAG_FBS_EN       = (1 << 2),     /* is EDMA set up for FBS? */
 434        MV_PP_FLAG_DELAYED_EH   = (1 << 3),     /* delayed dev err handling */
 435        MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4),    /* ignore initial ATA_DRDY */
 436};
 437
 438#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
 439#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
 440#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
 441#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
 442#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
 443
 444#define WINDOW_CTRL(i)          (0x20030 + ((i) << 4))
 445#define WINDOW_BASE(i)          (0x20034 + ((i) << 4))
 446
 447enum {
 448        /* DMA boundary 0xffff is required by the s/g splitting
 449         * we need on /length/ in mv_fill-sg().
 450         */
 451        MV_DMA_BOUNDARY         = 0xffffU,
 452
 453        /* mask of register bits containing lower 32 bits
 454         * of EDMA request queue DMA address
 455         */
 456        EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
 457
 458        /* ditto, for response queue */
 459        EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
 460};
 461
 462enum chip_type {
 463        chip_504x,
 464        chip_508x,
 465        chip_5080,
 466        chip_604x,
 467        chip_608x,
 468        chip_6042,
 469        chip_7042,
 470        chip_soc,
 471};
 472
 473/* Command ReQuest Block: 32B */
 474struct mv_crqb {
 475        __le32                  sg_addr;
 476        __le32                  sg_addr_hi;
 477        __le16                  ctrl_flags;
 478        __le16                  ata_cmd[11];
 479};
 480
 481struct mv_crqb_iie {
 482        __le32                  addr;
 483        __le32                  addr_hi;
 484        __le32                  flags;
 485        __le32                  len;
 486        __le32                  ata_cmd[4];
 487};
 488
 489/* Command ResPonse Block: 8B */
 490struct mv_crpb {
 491        __le16                  id;
 492        __le16                  flags;
 493        __le32                  tmstmp;
 494};
 495
 496/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
 497struct mv_sg {
 498        __le32                  addr;
 499        __le32                  flags_size;
 500        __le32                  addr_hi;
 501        __le32                  reserved;
 502};
 503
 504/*
 505 * We keep a local cache of a few frequently accessed port
 506 * registers here, to avoid having to read them (very slow)
 507 * when switching between EDMA and non-EDMA modes.
 508 */
 509struct mv_cached_regs {
 510        u32                     fiscfg;
 511        u32                     ltmode;
 512        u32                     haltcond;
 513        u32                     unknown_rsvd;
 514};
 515
 516struct mv_port_priv {
 517        struct mv_crqb          *crqb;
 518        dma_addr_t              crqb_dma;
 519        struct mv_crpb          *crpb;
 520        dma_addr_t              crpb_dma;
 521        struct mv_sg            *sg_tbl[MV_MAX_Q_DEPTH];
 522        dma_addr_t              sg_tbl_dma[MV_MAX_Q_DEPTH];
 523
 524        unsigned int            req_idx;
 525        unsigned int            resp_idx;
 526
 527        u32                     pp_flags;
 528        struct mv_cached_regs   cached;
 529        unsigned int            delayed_eh_pmp_map;
 530};
 531
 532struct mv_port_signal {
 533        u32                     amps;
 534        u32                     pre;
 535};
 536
 537struct mv_host_priv {
 538        u32                     hp_flags;
 539        unsigned int            board_idx;
 540        u32                     main_irq_mask;
 541        struct mv_port_signal   signal[8];
 542        const struct mv_hw_ops  *ops;
 543        int                     n_ports;
 544        void __iomem            *base;
 545        void __iomem            *main_irq_cause_addr;
 546        void __iomem            *main_irq_mask_addr;
 547        u32                     irq_cause_offset;
 548        u32                     irq_mask_offset;
 549        u32                     unmask_all_irqs;
 550
 551        /*
 552         * Needed on some devices that require their clocks to be enabled.
 553         * These are optional: if the platform device does not have any
 554         * clocks, they won't be used.  Also, if the underlying hardware
 555         * does not support the common clock framework (CONFIG_HAVE_CLK=n),
 556         * all the clock operations become no-ops (see clk.h).
 557         */
 558        struct clk              *clk;
 559        struct clk              **port_clks;
 560        /*
 561         * Some devices have a SATA PHY which can be enabled/disabled
 562         * in order to save power. These are optional: if the platform
 563         * devices does not have any phy, they won't be used.
 564         */
 565        struct phy              **port_phys;
 566        /*
 567         * These consistent DMA memory pools give us guaranteed
 568         * alignment for hardware-accessed data structures,
 569         * and less memory waste in accomplishing the alignment.
 570         */
 571        struct dma_pool         *crqb_pool;
 572        struct dma_pool         *crpb_pool;
 573        struct dma_pool         *sg_tbl_pool;
 574};
 575
 576struct mv_hw_ops {
 577        void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
 578                           unsigned int port);
 579        void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
 580        void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
 581                           void __iomem *mmio);
 582        int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
 583                        unsigned int n_hc);
 584        void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
 585        void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
 586};
 587
 588static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
 589static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
 590static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
 591static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
 592static int mv_port_start(struct ata_port *ap);
 593static void mv_port_stop(struct ata_port *ap);
 594static int mv_qc_defer(struct ata_queued_cmd *qc);
 595static void mv_qc_prep(struct ata_queued_cmd *qc);
 596static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
 597static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
 598static int mv_hardreset(struct ata_link *link, unsigned int *class,
 599                        unsigned long deadline);
 600static void mv_eh_freeze(struct ata_port *ap);
 601static void mv_eh_thaw(struct ata_port *ap);
 602static void mv6_dev_config(struct ata_device *dev);
 603
 604static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
 605                           unsigned int port);
 606static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
 607static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
 608                           void __iomem *mmio);
 609static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
 610                        unsigned int n_hc);
 611static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
 612static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
 613
 614static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
 615                           unsigned int port);
 616static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
 617static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
 618                           void __iomem *mmio);
 619static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
 620                        unsigned int n_hc);
 621static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
 622static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
 623                                      void __iomem *mmio);
 624static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
 625                                      void __iomem *mmio);
 626static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
 627                                  void __iomem *mmio, unsigned int n_hc);
 628static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
 629                                      void __iomem *mmio);
 630static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
 631static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
 632                                  void __iomem *mmio, unsigned int port);
 633static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
 634static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
 635                             unsigned int port_no);
 636static int mv_stop_edma(struct ata_port *ap);
 637static int mv_stop_edma_engine(void __iomem *port_mmio);
 638static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
 639
 640static void mv_pmp_select(struct ata_port *ap, int pmp);
 641static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
 642                                unsigned long deadline);
 643static int  mv_softreset(struct ata_link *link, unsigned int *class,
 644                                unsigned long deadline);
 645static void mv_pmp_error_handler(struct ata_port *ap);
 646static void mv_process_crpb_entries(struct ata_port *ap,
 647                                        struct mv_port_priv *pp);
 648
 649static void mv_sff_irq_clear(struct ata_port *ap);
 650static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
 651static void mv_bmdma_setup(struct ata_queued_cmd *qc);
 652static void mv_bmdma_start(struct ata_queued_cmd *qc);
 653static void mv_bmdma_stop(struct ata_queued_cmd *qc);
 654static u8   mv_bmdma_status(struct ata_port *ap);
 655static u8 mv_sff_check_status(struct ata_port *ap);
 656
 657/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
 658 * because we have to allow room for worst case splitting of
 659 * PRDs for 64K boundaries in mv_fill_sg().
 660 */
 661#ifdef CONFIG_PCI
 662static struct scsi_host_template mv5_sht = {
 663        ATA_BASE_SHT(DRV_NAME),
 664        .sg_tablesize           = MV_MAX_SG_CT / 2,
 665        .dma_boundary           = MV_DMA_BOUNDARY,
 666};
 667#endif
 668static struct scsi_host_template mv6_sht = {
 669        ATA_NCQ_SHT(DRV_NAME),
 670        .can_queue              = MV_MAX_Q_DEPTH - 1,
 671        .sg_tablesize           = MV_MAX_SG_CT / 2,
 672        .dma_boundary           = MV_DMA_BOUNDARY,
 673};
 674
 675static struct ata_port_operations mv5_ops = {
 676        .inherits               = &ata_sff_port_ops,
 677
 678        .lost_interrupt         = ATA_OP_NULL,
 679
 680        .qc_defer               = mv_qc_defer,
 681        .qc_prep                = mv_qc_prep,
 682        .qc_issue               = mv_qc_issue,
 683
 684        .freeze                 = mv_eh_freeze,
 685        .thaw                   = mv_eh_thaw,
 686        .hardreset              = mv_hardreset,
 687
 688        .scr_read               = mv5_scr_read,
 689        .scr_write              = mv5_scr_write,
 690
 691        .port_start             = mv_port_start,
 692        .port_stop              = mv_port_stop,
 693};
 694
 695static struct ata_port_operations mv6_ops = {
 696        .inherits               = &ata_bmdma_port_ops,
 697
 698        .lost_interrupt         = ATA_OP_NULL,
 699
 700        .qc_defer               = mv_qc_defer,
 701        .qc_prep                = mv_qc_prep,
 702        .qc_issue               = mv_qc_issue,
 703
 704        .dev_config             = mv6_dev_config,
 705
 706        .freeze                 = mv_eh_freeze,
 707        .thaw                   = mv_eh_thaw,
 708        .hardreset              = mv_hardreset,
 709        .softreset              = mv_softreset,
 710        .pmp_hardreset          = mv_pmp_hardreset,
 711        .pmp_softreset          = mv_softreset,
 712        .error_handler          = mv_pmp_error_handler,
 713
 714        .scr_read               = mv_scr_read,
 715        .scr_write              = mv_scr_write,
 716
 717        .sff_check_status       = mv_sff_check_status,
 718        .sff_irq_clear          = mv_sff_irq_clear,
 719        .check_atapi_dma        = mv_check_atapi_dma,
 720        .bmdma_setup            = mv_bmdma_setup,
 721        .bmdma_start            = mv_bmdma_start,
 722        .bmdma_stop             = mv_bmdma_stop,
 723        .bmdma_status           = mv_bmdma_status,
 724
 725        .port_start             = mv_port_start,
 726        .port_stop              = mv_port_stop,
 727};
 728
 729static struct ata_port_operations mv_iie_ops = {
 730        .inherits               = &mv6_ops,
 731        .dev_config             = ATA_OP_NULL,
 732        .qc_prep                = mv_qc_prep_iie,
 733};
 734
 735static const struct ata_port_info mv_port_info[] = {
 736        {  /* chip_504x */
 737                .flags          = MV_GEN_I_FLAGS,
 738                .pio_mask       = ATA_PIO4,
 739                .udma_mask      = ATA_UDMA6,
 740                .port_ops       = &mv5_ops,
 741        },
 742        {  /* chip_508x */
 743                .flags          = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
 744                .pio_mask       = ATA_PIO4,
 745                .udma_mask      = ATA_UDMA6,
 746                .port_ops       = &mv5_ops,
 747        },
 748        {  /* chip_5080 */
 749                .flags          = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
 750                .pio_mask       = ATA_PIO4,
 751                .udma_mask      = ATA_UDMA6,
 752                .port_ops       = &mv5_ops,
 753        },
 754        {  /* chip_604x */
 755                .flags          = MV_GEN_II_FLAGS,
 756                .pio_mask       = ATA_PIO4,
 757                .udma_mask      = ATA_UDMA6,
 758                .port_ops       = &mv6_ops,
 759        },
 760        {  /* chip_608x */
 761                .flags          = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
 762                .pio_mask       = ATA_PIO4,
 763                .udma_mask      = ATA_UDMA6,
 764                .port_ops       = &mv6_ops,
 765        },
 766        {  /* chip_6042 */
 767                .flags          = MV_GEN_IIE_FLAGS,
 768                .pio_mask       = ATA_PIO4,
 769                .udma_mask      = ATA_UDMA6,
 770                .port_ops       = &mv_iie_ops,
 771        },
 772        {  /* chip_7042 */
 773                .flags          = MV_GEN_IIE_FLAGS,
 774                .pio_mask       = ATA_PIO4,
 775                .udma_mask      = ATA_UDMA6,
 776                .port_ops       = &mv_iie_ops,
 777        },
 778        {  /* chip_soc */
 779                .flags          = MV_GEN_IIE_FLAGS,
 780                .pio_mask       = ATA_PIO4,
 781                .udma_mask      = ATA_UDMA6,
 782                .port_ops       = &mv_iie_ops,
 783        },
 784};
 785
 786static const struct pci_device_id mv_pci_tbl[] = {
 787        { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
 788        { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
 789        { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
 790        { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
 791        /* RocketRAID 1720/174x have different identifiers */
 792        { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
 793        { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
 794        { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
 795
 796        { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
 797        { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
 798        { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
 799        { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
 800        { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
 801
 802        { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
 803
 804        /* Adaptec 1430SA */
 805        { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
 806
 807        /* Marvell 7042 support */
 808        { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
 809
 810        /* Highpoint RocketRAID PCIe series */
 811        { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
 812        { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
 813
 814        { }                     /* terminate list */
 815};
 816
 817static const struct mv_hw_ops mv5xxx_ops = {
 818        .phy_errata             = mv5_phy_errata,
 819        .enable_leds            = mv5_enable_leds,
 820        .read_preamp            = mv5_read_preamp,
 821        .reset_hc               = mv5_reset_hc,
 822        .reset_flash            = mv5_reset_flash,
 823        .reset_bus              = mv5_reset_bus,
 824};
 825
 826static const struct mv_hw_ops mv6xxx_ops = {
 827        .phy_errata             = mv6_phy_errata,
 828        .enable_leds            = mv6_enable_leds,
 829        .read_preamp            = mv6_read_preamp,
 830        .reset_hc               = mv6_reset_hc,
 831        .reset_flash            = mv6_reset_flash,
 832        .reset_bus              = mv_reset_pci_bus,
 833};
 834
 835static const struct mv_hw_ops mv_soc_ops = {
 836        .phy_errata             = mv6_phy_errata,
 837        .enable_leds            = mv_soc_enable_leds,
 838        .read_preamp            = mv_soc_read_preamp,
 839        .reset_hc               = mv_soc_reset_hc,
 840        .reset_flash            = mv_soc_reset_flash,
 841        .reset_bus              = mv_soc_reset_bus,
 842};
 843
 844static const struct mv_hw_ops mv_soc_65n_ops = {
 845        .phy_errata             = mv_soc_65n_phy_errata,
 846        .enable_leds            = mv_soc_enable_leds,
 847        .reset_hc               = mv_soc_reset_hc,
 848        .reset_flash            = mv_soc_reset_flash,
 849        .reset_bus              = mv_soc_reset_bus,
 850};
 851
 852/*
 853 * Functions
 854 */
 855
 856static inline void writelfl(unsigned long data, void __iomem *addr)
 857{
 858        writel(data, addr);
 859        (void) readl(addr);     /* flush to avoid PCI posted write */
 860}
 861
 862static inline unsigned int mv_hc_from_port(unsigned int port)
 863{
 864        return port >> MV_PORT_HC_SHIFT;
 865}
 866
 867static inline unsigned int mv_hardport_from_port(unsigned int port)
 868{
 869        return port & MV_PORT_MASK;
 870}
 871
 872/*
 873 * Consolidate some rather tricky bit shift calculations.
 874 * This is hot-path stuff, so not a function.
 875 * Simple code, with two return values, so macro rather than inline.
 876 *
 877 * port is the sole input, in range 0..7.
 878 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
 879 * hardport is the other output, in range 0..3.
 880 *
 881 * Note that port and hardport may be the same variable in some cases.
 882 */
 883#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport)    \
 884{                                                               \
 885        shift    = mv_hc_from_port(port) * HC_SHIFT;            \
 886        hardport = mv_hardport_from_port(port);                 \
 887        shift   += hardport * 2;                                \
 888}
 889
 890static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
 891{
 892        return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
 893}
 894
 895static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
 896                                                 unsigned int port)
 897{
 898        return mv_hc_base(base, mv_hc_from_port(port));
 899}
 900
 901static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
 902{
 903        return  mv_hc_base_from_port(base, port) +
 904                MV_SATAHC_ARBTR_REG_SZ +
 905                (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
 906}
 907
 908static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
 909{
 910        void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
 911        unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
 912
 913        return hc_mmio + ofs;
 914}
 915
 916static inline void __iomem *mv_host_base(struct ata_host *host)
 917{
 918        struct mv_host_priv *hpriv = host->private_data;
 919        return hpriv->base;
 920}
 921
 922static inline void __iomem *mv_ap_base(struct ata_port *ap)
 923{
 924        return mv_port_base(mv_host_base(ap->host), ap->port_no);
 925}
 926
 927static inline int mv_get_hc_count(unsigned long port_flags)
 928{
 929        return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
 930}
 931
 932/**
 933 *      mv_save_cached_regs - (re-)initialize cached port registers
 934 *      @ap: the port whose registers we are caching
 935 *
 936 *      Initialize the local cache of port registers,
 937 *      so that reading them over and over again can
 938 *      be avoided on the hotter paths of this driver.
 939 *      This saves a few microseconds each time we switch
 940 *      to/from EDMA mode to perform (eg.) a drive cache flush.
 941 */
 942static void mv_save_cached_regs(struct ata_port *ap)
 943{
 944        void __iomem *port_mmio = mv_ap_base(ap);
 945        struct mv_port_priv *pp = ap->private_data;
 946
 947        pp->cached.fiscfg = readl(port_mmio + FISCFG);
 948        pp->cached.ltmode = readl(port_mmio + LTMODE);
 949        pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
 950        pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
 951}
 952
 953/**
 954 *      mv_write_cached_reg - write to a cached port register
 955 *      @addr: hardware address of the register
 956 *      @old: pointer to cached value of the register
 957 *      @new: new value for the register
 958 *
 959 *      Write a new value to a cached register,
 960 *      but only if the value is different from before.
 961 */
 962static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
 963{
 964        if (new != *old) {
 965                unsigned long laddr;
 966                *old = new;
 967                /*
 968                 * Workaround for 88SX60x1-B2 FEr SATA#13:
 969                 * Read-after-write is needed to prevent generating 64-bit
 970                 * write cycles on the PCI bus for SATA interface registers
 971                 * at offsets ending in 0x4 or 0xc.
 972                 *
 973                 * Looks like a lot of fuss, but it avoids an unnecessary
 974                 * +1 usec read-after-write delay for unaffected registers.
 975                 */
 976                laddr = (unsigned long)addr & 0xffff;
 977                if (laddr >= 0x300 && laddr <= 0x33c) {
 978                        laddr &= 0x000f;
 979                        if (laddr == 0x4 || laddr == 0xc) {
 980                                writelfl(new, addr); /* read after write */
 981                                return;
 982                        }
 983                }
 984                writel(new, addr); /* unaffected by the errata */
 985        }
 986}
 987
 988static void mv_set_edma_ptrs(void __iomem *port_mmio,
 989                             struct mv_host_priv *hpriv,
 990                             struct mv_port_priv *pp)
 991{
 992        u32 index;
 993
 994        /*
 995         * initialize request queue
 996         */
 997        pp->req_idx &= MV_MAX_Q_DEPTH_MASK;     /* paranoia */
 998        index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
 999
1000        WARN_ON(pp->crqb_dma & 0x3ff);
1001        writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
1002        writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
1003                 port_mmio + EDMA_REQ_Q_IN_PTR);
1004        writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
1005
1006        /*
1007         * initialize response queue
1008         */
1009        pp->resp_idx &= MV_MAX_Q_DEPTH_MASK;    /* paranoia */
1010        index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
1011
1012        WARN_ON(pp->crpb_dma & 0xff);
1013        writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1014        writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
1015        writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
1016                 port_mmio + EDMA_RSP_Q_OUT_PTR);
1017}
1018
1019static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1020{
1021        /*
1022         * When writing to the main_irq_mask in hardware,
1023         * we must ensure exclusivity between the interrupt coalescing bits
1024         * and the corresponding individual port DONE_IRQ bits.
1025         *
1026         * Note that this register is really an "IRQ enable" register,
1027         * not an "IRQ mask" register as Marvell's naming might suggest.
1028         */
1029        if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1030                mask &= ~DONE_IRQ_0_3;
1031        if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1032                mask &= ~DONE_IRQ_4_7;
1033        writelfl(mask, hpriv->main_irq_mask_addr);
1034}
1035
1036static void mv_set_main_irq_mask(struct ata_host *host,
1037                                 u32 disable_bits, u32 enable_bits)
1038{
1039        struct mv_host_priv *hpriv = host->private_data;
1040        u32 old_mask, new_mask;
1041
1042        old_mask = hpriv->main_irq_mask;
1043        new_mask = (old_mask & ~disable_bits) | enable_bits;
1044        if (new_mask != old_mask) {
1045                hpriv->main_irq_mask = new_mask;
1046                mv_write_main_irq_mask(new_mask, hpriv);
1047        }
1048}
1049
1050static void mv_enable_port_irqs(struct ata_port *ap,
1051                                     unsigned int port_bits)
1052{
1053        unsigned int shift, hardport, port = ap->port_no;
1054        u32 disable_bits, enable_bits;
1055
1056        MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1057
1058        disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1059        enable_bits  = port_bits << shift;
1060        mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1061}
1062
1063static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1064                                          void __iomem *port_mmio,
1065                                          unsigned int port_irqs)
1066{
1067        struct mv_host_priv *hpriv = ap->host->private_data;
1068        int hardport = mv_hardport_from_port(ap->port_no);
1069        void __iomem *hc_mmio = mv_hc_base_from_port(
1070                                mv_host_base(ap->host), ap->port_no);
1071        u32 hc_irq_cause;
1072
1073        /* clear EDMA event indicators, if any */
1074        writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1075
1076        /* clear pending irq events */
1077        hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1078        writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1079
1080        /* clear FIS IRQ Cause */
1081        if (IS_GEN_IIE(hpriv))
1082                writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1083
1084        mv_enable_port_irqs(ap, port_irqs);
1085}
1086
1087static void mv_set_irq_coalescing(struct ata_host *host,
1088                                  unsigned int count, unsigned int usecs)
1089{
1090        struct mv_host_priv *hpriv = host->private_data;
1091        void __iomem *mmio = hpriv->base, *hc_mmio;
1092        u32 coal_enable = 0;
1093        unsigned long flags;
1094        unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1095        const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1096                                                        ALL_PORTS_COAL_DONE;
1097
1098        /* Disable IRQ coalescing if either threshold is zero */
1099        if (!usecs || !count) {
1100                clks = count = 0;
1101        } else {
1102                /* Respect maximum limits of the hardware */
1103                clks = usecs * COAL_CLOCKS_PER_USEC;
1104                if (clks > MAX_COAL_TIME_THRESHOLD)
1105                        clks = MAX_COAL_TIME_THRESHOLD;
1106                if (count > MAX_COAL_IO_COUNT)
1107                        count = MAX_COAL_IO_COUNT;
1108        }
1109
1110        spin_lock_irqsave(&host->lock, flags);
1111        mv_set_main_irq_mask(host, coal_disable, 0);
1112
1113        if (is_dual_hc && !IS_GEN_I(hpriv)) {
1114                /*
1115                 * GEN_II/GEN_IIE with dual host controllers:
1116                 * one set of global thresholds for the entire chip.
1117                 */
1118                writel(clks,  mmio + IRQ_COAL_TIME_THRESHOLD);
1119                writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1120                /* clear leftover coal IRQ bit */
1121                writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1122                if (count)
1123                        coal_enable = ALL_PORTS_COAL_DONE;
1124                clks = count = 0; /* force clearing of regular regs below */
1125        }
1126
1127        /*
1128         * All chips: independent thresholds for each HC on the chip.
1129         */
1130        hc_mmio = mv_hc_base_from_port(mmio, 0);
1131        writel(clks,  hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1132        writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1133        writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1134        if (count)
1135                coal_enable |= PORTS_0_3_COAL_DONE;
1136        if (is_dual_hc) {
1137                hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1138                writel(clks,  hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1139                writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1140                writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1141                if (count)
1142                        coal_enable |= PORTS_4_7_COAL_DONE;
1143        }
1144
1145        mv_set_main_irq_mask(host, 0, coal_enable);
1146        spin_unlock_irqrestore(&host->lock, flags);
1147}
1148
1149/**
1150 *      mv_start_edma - Enable eDMA engine
1151 *      @base: port base address
1152 *      @pp: port private data
1153 *
1154 *      Verify the local cache of the eDMA state is accurate with a
1155 *      WARN_ON.
1156 *
1157 *      LOCKING:
1158 *      Inherited from caller.
1159 */
1160static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1161                         struct mv_port_priv *pp, u8 protocol)
1162{
1163        int want_ncq = (protocol == ATA_PROT_NCQ);
1164
1165        if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1166                int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1167                if (want_ncq != using_ncq)
1168                        mv_stop_edma(ap);
1169        }
1170        if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1171                struct mv_host_priv *hpriv = ap->host->private_data;
1172
1173                mv_edma_cfg(ap, want_ncq, 1);
1174
1175                mv_set_edma_ptrs(port_mmio, hpriv, pp);
1176                mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1177
1178                writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1179                pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1180        }
1181}
1182
1183static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1184{
1185        void __iomem *port_mmio = mv_ap_base(ap);
1186        const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1187        const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1188        int i;
1189
1190        /*
1191         * Wait for the EDMA engine to finish transactions in progress.
1192         * No idea what a good "timeout" value might be, but measurements
1193         * indicate that it often requires hundreds of microseconds
1194         * with two drives in-use.  So we use the 15msec value above
1195         * as a rough guess at what even more drives might require.
1196         */
1197        for (i = 0; i < timeout; ++i) {
1198                u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1199                if ((edma_stat & empty_idle) == empty_idle)
1200                        break;
1201                udelay(per_loop);
1202        }
1203        /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
1204}
1205
1206/**
1207 *      mv_stop_edma_engine - Disable eDMA engine
1208 *      @port_mmio: io base address
1209 *
1210 *      LOCKING:
1211 *      Inherited from caller.
1212 */
1213static int mv_stop_edma_engine(void __iomem *port_mmio)
1214{
1215        int i;
1216
1217        /* Disable eDMA.  The disable bit auto clears. */
1218        writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1219
1220        /* Wait for the chip to confirm eDMA is off. */
1221        for (i = 10000; i > 0; i--) {
1222                u32 reg = readl(port_mmio + EDMA_CMD);
1223                if (!(reg & EDMA_EN))
1224                        return 0;
1225                udelay(10);
1226        }
1227        return -EIO;
1228}
1229
1230static int mv_stop_edma(struct ata_port *ap)
1231{
1232        void __iomem *port_mmio = mv_ap_base(ap);
1233        struct mv_port_priv *pp = ap->private_data;
1234        int err = 0;
1235
1236        if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1237                return 0;
1238        pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1239        mv_wait_for_edma_empty_idle(ap);
1240        if (mv_stop_edma_engine(port_mmio)) {
1241                ata_port_err(ap, "Unable to stop eDMA\n");
1242                err = -EIO;
1243        }
1244        mv_edma_cfg(ap, 0, 0);
1245        return err;
1246}
1247
1248#ifdef ATA_DEBUG
1249static void mv_dump_mem(void __iomem *start, unsigned bytes)
1250{
1251        int b, w;
1252        for (b = 0; b < bytes; ) {
1253                DPRINTK("%p: ", start + b);
1254                for (w = 0; b < bytes && w < 4; w++) {
1255                        printk("%08x ", readl(start + b));
1256                        b += sizeof(u32);
1257                }
1258                printk("\n");
1259        }
1260}
1261#endif
1262#if defined(ATA_DEBUG) || defined(CONFIG_PCI)
1263static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1264{
1265#ifdef ATA_DEBUG
1266        int b, w;
1267        u32 dw;
1268        for (b = 0; b < bytes; ) {
1269                DPRINTK("%02x: ", b);
1270                for (w = 0; b < bytes && w < 4; w++) {
1271                        (void) pci_read_config_dword(pdev, b, &dw);
1272                        printk("%08x ", dw);
1273                        b += sizeof(u32);
1274                }
1275                printk("\n");
1276        }
1277#endif
1278}
1279#endif
1280static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1281                             struct pci_dev *pdev)
1282{
1283#ifdef ATA_DEBUG
1284        void __iomem *hc_base = mv_hc_base(mmio_base,
1285                                           port >> MV_PORT_HC_SHIFT);
1286        void __iomem *port_base;
1287        int start_port, num_ports, p, start_hc, num_hcs, hc;
1288
1289        if (0 > port) {
1290                start_hc = start_port = 0;
1291                num_ports = 8;          /* shld be benign for 4 port devs */
1292                num_hcs = 2;
1293        } else {
1294                start_hc = port >> MV_PORT_HC_SHIFT;
1295                start_port = port;
1296                num_ports = num_hcs = 1;
1297        }
1298        DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1299                num_ports > 1 ? num_ports - 1 : start_port);
1300
1301        if (NULL != pdev) {
1302                DPRINTK("PCI config space regs:\n");
1303                mv_dump_pci_cfg(pdev, 0x68);
1304        }
1305        DPRINTK("PCI regs:\n");
1306        mv_dump_mem(mmio_base+0xc00, 0x3c);
1307        mv_dump_mem(mmio_base+0xd00, 0x34);
1308        mv_dump_mem(mmio_base+0xf00, 0x4);
1309        mv_dump_mem(mmio_base+0x1d00, 0x6c);
1310        for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1311                hc_base = mv_hc_base(mmio_base, hc);
1312                DPRINTK("HC regs (HC %i):\n", hc);
1313                mv_dump_mem(hc_base, 0x1c);
1314        }
1315        for (p = start_port; p < start_port + num_ports; p++) {
1316                port_base = mv_port_base(mmio_base, p);
1317                DPRINTK("EDMA regs (port %i):\n", p);
1318                mv_dump_mem(port_base, 0x54);
1319                DPRINTK("SATA regs (port %i):\n", p);
1320                mv_dump_mem(port_base+0x300, 0x60);
1321        }
1322#endif
1323}
1324
1325static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1326{
1327        unsigned int ofs;
1328
1329        switch (sc_reg_in) {
1330        case SCR_STATUS:
1331        case SCR_CONTROL:
1332        case SCR_ERROR:
1333                ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1334                break;
1335        case SCR_ACTIVE:
1336                ofs = SATA_ACTIVE;   /* active is not with the others */
1337                break;
1338        default:
1339                ofs = 0xffffffffU;
1340                break;
1341        }
1342        return ofs;
1343}
1344
1345static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1346{
1347        unsigned int ofs = mv_scr_offset(sc_reg_in);
1348
1349        if (ofs != 0xffffffffU) {
1350                *val = readl(mv_ap_base(link->ap) + ofs);
1351                return 0;
1352        } else
1353                return -EINVAL;
1354}
1355
1356static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1357{
1358        unsigned int ofs = mv_scr_offset(sc_reg_in);
1359
1360        if (ofs != 0xffffffffU) {
1361                void __iomem *addr = mv_ap_base(link->ap) + ofs;
1362                struct mv_host_priv *hpriv = link->ap->host->private_data;
1363                if (sc_reg_in == SCR_CONTROL) {
1364                        /*
1365                         * Workaround for 88SX60x1 FEr SATA#26:
1366                         *
1367                         * COMRESETs have to take care not to accidentally
1368                         * put the drive to sleep when writing SCR_CONTROL.
1369                         * Setting bits 12..15 prevents this problem.
1370                         *
1371                         * So if we see an outbound COMMRESET, set those bits.
1372                         * Ditto for the followup write that clears the reset.
1373                         *
1374                         * The proprietary driver does this for
1375                         * all chip versions, and so do we.
1376                         */
1377                        if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1378                                val |= 0xf000;
1379
1380                        if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
1381                                void __iomem *lp_phy_addr =
1382                                        mv_ap_base(link->ap) + LP_PHY_CTL;
1383                                /*
1384                                 * Set PHY speed according to SControl speed.
1385                                 */
1386                                u32 lp_phy_val =
1387                                        LP_PHY_CTL_PIN_PU_PLL |
1388                                        LP_PHY_CTL_PIN_PU_RX  |
1389                                        LP_PHY_CTL_PIN_PU_TX;
1390
1391                                if ((val & 0xf0) != 0x10)
1392                                        lp_phy_val |=
1393                                                LP_PHY_CTL_GEN_TX_3G |
1394                                                LP_PHY_CTL_GEN_RX_3G;
1395
1396                                writelfl(lp_phy_val, lp_phy_addr);
1397                        }
1398                }
1399                writelfl(val, addr);
1400                return 0;
1401        } else
1402                return -EINVAL;
1403}
1404
1405static void mv6_dev_config(struct ata_device *adev)
1406{
1407        /*
1408         * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1409         *
1410         * Gen-II does not support NCQ over a port multiplier
1411         *  (no FIS-based switching).
1412         */
1413        if (adev->flags & ATA_DFLAG_NCQ) {
1414                if (sata_pmp_attached(adev->link->ap)) {
1415                        adev->flags &= ~ATA_DFLAG_NCQ;
1416                        ata_dev_info(adev,
1417                                "NCQ disabled for command-based switching\n");
1418                }
1419        }
1420}
1421
1422static int mv_qc_defer(struct ata_queued_cmd *qc)
1423{
1424        struct ata_link *link = qc->dev->link;
1425        struct ata_port *ap = link->ap;
1426        struct mv_port_priv *pp = ap->private_data;
1427
1428        /*
1429         * Don't allow new commands if we're in a delayed EH state
1430         * for NCQ and/or FIS-based switching.
1431         */
1432        if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1433                return ATA_DEFER_PORT;
1434
1435        /* PIO commands need exclusive link: no other commands [DMA or PIO]
1436         * can run concurrently.
1437         * set excl_link when we want to send a PIO command in DMA mode
1438         * or a non-NCQ command in NCQ mode.
1439         * When we receive a command from that link, and there are no
1440         * outstanding commands, mark a flag to clear excl_link and let
1441         * the command go through.
1442         */
1443        if (unlikely(ap->excl_link)) {
1444                if (link == ap->excl_link) {
1445                        if (ap->nr_active_links)
1446                                return ATA_DEFER_PORT;
1447                        qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1448                        return 0;
1449                } else
1450                        return ATA_DEFER_PORT;
1451        }
1452
1453        /*
1454         * If the port is completely idle, then allow the new qc.
1455         */
1456        if (ap->nr_active_links == 0)
1457                return 0;
1458
1459        /*
1460         * The port is operating in host queuing mode (EDMA) with NCQ
1461         * enabled, allow multiple NCQ commands.  EDMA also allows
1462         * queueing multiple DMA commands but libata core currently
1463         * doesn't allow it.
1464         */
1465        if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1466            (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1467                if (ata_is_ncq(qc->tf.protocol))
1468                        return 0;
1469                else {
1470                        ap->excl_link = link;
1471                        return ATA_DEFER_PORT;
1472                }
1473        }
1474
1475        return ATA_DEFER_PORT;
1476}
1477
1478static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1479{
1480        struct mv_port_priv *pp = ap->private_data;
1481        void __iomem *port_mmio;
1482
1483        u32 fiscfg,   *old_fiscfg   = &pp->cached.fiscfg;
1484        u32 ltmode,   *old_ltmode   = &pp->cached.ltmode;
1485        u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1486
1487        ltmode   = *old_ltmode & ~LTMODE_BIT8;
1488        haltcond = *old_haltcond | EDMA_ERR_DEV;
1489
1490        if (want_fbs) {
1491                fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1492                ltmode = *old_ltmode | LTMODE_BIT8;
1493                if (want_ncq)
1494                        haltcond &= ~EDMA_ERR_DEV;
1495                else
1496                        fiscfg |=  FISCFG_WAIT_DEV_ERR;
1497        } else {
1498                fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1499        }
1500
1501        port_mmio = mv_ap_base(ap);
1502        mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1503        mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1504        mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1505}
1506
1507static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1508{
1509        struct mv_host_priv *hpriv = ap->host->private_data;
1510        u32 old, new;
1511
1512        /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1513        old = readl(hpriv->base + GPIO_PORT_CTL);
1514        if (want_ncq)
1515                new = old | (1 << 22);
1516        else
1517                new = old & ~(1 << 22);
1518        if (new != old)
1519                writel(new, hpriv->base + GPIO_PORT_CTL);
1520}
1521
1522/**
1523 *      mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1524 *      @ap: Port being initialized
1525 *
1526 *      There are two DMA modes on these chips:  basic DMA, and EDMA.
1527 *
1528 *      Bit-0 of the "EDMA RESERVED" register enables/disables use
1529 *      of basic DMA on the GEN_IIE versions of the chips.
1530 *
1531 *      This bit survives EDMA resets, and must be set for basic DMA
1532 *      to function, and should be cleared when EDMA is active.
1533 */
1534static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1535{
1536        struct mv_port_priv *pp = ap->private_data;
1537        u32 new, *old = &pp->cached.unknown_rsvd;
1538
1539        if (enable_bmdma)
1540                new = *old | 1;
1541        else
1542                new = *old & ~1;
1543        mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1544}
1545
1546/*
1547 * SOC chips have an issue whereby the HDD LEDs don't always blink
1548 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1549 * of the SOC takes care of it, generating a steady blink rate when
1550 * any drive on the chip is active.
1551 *
1552 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1553 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1554 *
1555 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1556 * LED operation works then, and provides better (more accurate) feedback.
1557 *
1558 * Note that this code assumes that an SOC never has more than one HC onboard.
1559 */
1560static void mv_soc_led_blink_enable(struct ata_port *ap)
1561{
1562        struct ata_host *host = ap->host;
1563        struct mv_host_priv *hpriv = host->private_data;
1564        void __iomem *hc_mmio;
1565        u32 led_ctrl;
1566
1567        if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1568                return;
1569        hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1570        hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1571        led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1572        writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1573}
1574
1575static void mv_soc_led_blink_disable(struct ata_port *ap)
1576{
1577        struct ata_host *host = ap->host;
1578        struct mv_host_priv *hpriv = host->private_data;
1579        void __iomem *hc_mmio;
1580        u32 led_ctrl;
1581        unsigned int port;
1582
1583        if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1584                return;
1585
1586        /* disable led-blink only if no ports are using NCQ */
1587        for (port = 0; port < hpriv->n_ports; port++) {
1588                struct ata_port *this_ap = host->ports[port];
1589                struct mv_port_priv *pp = this_ap->private_data;
1590
1591                if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1592                        return;
1593        }
1594
1595        hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1596        hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1597        led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1598        writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1599}
1600
1601static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1602{
1603        u32 cfg;
1604        struct mv_port_priv *pp    = ap->private_data;
1605        struct mv_host_priv *hpriv = ap->host->private_data;
1606        void __iomem *port_mmio    = mv_ap_base(ap);
1607
1608        /* set up non-NCQ EDMA configuration */
1609        cfg = EDMA_CFG_Q_DEPTH;         /* always 0x1f for *all* chips */
1610        pp->pp_flags &=
1611          ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1612
1613        if (IS_GEN_I(hpriv))
1614                cfg |= (1 << 8);        /* enab config burst size mask */
1615
1616        else if (IS_GEN_II(hpriv)) {
1617                cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1618                mv_60x1_errata_sata25(ap, want_ncq);
1619
1620        } else if (IS_GEN_IIE(hpriv)) {
1621                int want_fbs = sata_pmp_attached(ap);
1622                /*
1623                 * Possible future enhancement:
1624                 *
1625                 * The chip can use FBS with non-NCQ, if we allow it,
1626                 * But first we need to have the error handling in place
1627                 * for this mode (datasheet section 7.3.15.4.2.3).
1628                 * So disallow non-NCQ FBS for now.
1629                 */
1630                want_fbs &= want_ncq;
1631
1632                mv_config_fbs(ap, want_ncq, want_fbs);
1633
1634                if (want_fbs) {
1635                        pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1636                        cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1637                }
1638
1639                cfg |= (1 << 23);       /* do not mask PM field in rx'd FIS */
1640                if (want_edma) {
1641                        cfg |= (1 << 22); /* enab 4-entry host queue cache */
1642                        if (!IS_SOC(hpriv))
1643                                cfg |= (1 << 18); /* enab early completion */
1644                }
1645                if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1646                        cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1647                mv_bmdma_enable_iie(ap, !want_edma);
1648
1649                if (IS_SOC(hpriv)) {
1650                        if (want_ncq)
1651                                mv_soc_led_blink_enable(ap);
1652                        else
1653                                mv_soc_led_blink_disable(ap);
1654                }
1655        }
1656
1657        if (want_ncq) {
1658                cfg |= EDMA_CFG_NCQ;
1659                pp->pp_flags |=  MV_PP_FLAG_NCQ_EN;
1660        }
1661
1662        writelfl(cfg, port_mmio + EDMA_CFG);
1663}
1664
1665static void mv_port_free_dma_mem(struct ata_port *ap)
1666{
1667        struct mv_host_priv *hpriv = ap->host->private_data;
1668        struct mv_port_priv *pp = ap->private_data;
1669        int tag;
1670
1671        if (pp->crqb) {
1672                dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1673                pp->crqb = NULL;
1674        }
1675        if (pp->crpb) {
1676                dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1677                pp->crpb = NULL;
1678        }
1679        /*
1680         * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1681         * For later hardware, we have one unique sg_tbl per NCQ tag.
1682         */
1683        for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1684                if (pp->sg_tbl[tag]) {
1685                        if (tag == 0 || !IS_GEN_I(hpriv))
1686                                dma_pool_free(hpriv->sg_tbl_pool,
1687                                              pp->sg_tbl[tag],
1688                                              pp->sg_tbl_dma[tag]);
1689                        pp->sg_tbl[tag] = NULL;
1690                }
1691        }
1692}
1693
1694/**
1695 *      mv_port_start - Port specific init/start routine.
1696 *      @ap: ATA channel to manipulate
1697 *
1698 *      Allocate and point to DMA memory, init port private memory,
1699 *      zero indices.
1700 *
1701 *      LOCKING:
1702 *      Inherited from caller.
1703 */
1704static int mv_port_start(struct ata_port *ap)
1705{
1706        struct device *dev = ap->host->dev;
1707        struct mv_host_priv *hpriv = ap->host->private_data;
1708        struct mv_port_priv *pp;
1709        unsigned long flags;
1710        int tag;
1711
1712        pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1713        if (!pp)
1714                return -ENOMEM;
1715        ap->private_data = pp;
1716
1717        pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1718        if (!pp->crqb)
1719                return -ENOMEM;
1720
1721        pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1722        if (!pp->crpb)
1723                goto out_port_free_dma_mem;
1724
1725        /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1726        if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1727                ap->flags |= ATA_FLAG_AN;
1728        /*
1729         * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1730         * For later hardware, we need one unique sg_tbl per NCQ tag.
1731         */
1732        for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1733                if (tag == 0 || !IS_GEN_I(hpriv)) {
1734                        pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1735                                              GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1736                        if (!pp->sg_tbl[tag])
1737                                goto out_port_free_dma_mem;
1738                } else {
1739                        pp->sg_tbl[tag]     = pp->sg_tbl[0];
1740                        pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1741                }
1742        }
1743
1744        spin_lock_irqsave(ap->lock, flags);
1745        mv_save_cached_regs(ap);
1746        mv_edma_cfg(ap, 0, 0);
1747        spin_unlock_irqrestore(ap->lock, flags);
1748
1749        return 0;
1750
1751out_port_free_dma_mem:
1752        mv_port_free_dma_mem(ap);
1753        return -ENOMEM;
1754}
1755
1756/**
1757 *      mv_port_stop - Port specific cleanup/stop routine.
1758 *      @ap: ATA channel to manipulate
1759 *
1760 *      Stop DMA, cleanup port memory.
1761 *
1762 *      LOCKING:
1763 *      This routine uses the host lock to protect the DMA stop.
1764 */
1765static void mv_port_stop(struct ata_port *ap)
1766{
1767        unsigned long flags;
1768
1769        spin_lock_irqsave(ap->lock, flags);
1770        mv_stop_edma(ap);
1771        mv_enable_port_irqs(ap, 0);
1772        spin_unlock_irqrestore(ap->lock, flags);
1773        mv_port_free_dma_mem(ap);
1774}
1775
1776/**
1777 *      mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1778 *      @qc: queued command whose SG list to source from
1779 *
1780 *      Populate the SG list and mark the last entry.
1781 *
1782 *      LOCKING:
1783 *      Inherited from caller.
1784 */
1785static void mv_fill_sg(struct ata_queued_cmd *qc)
1786{
1787        struct mv_port_priv *pp = qc->ap->private_data;
1788        struct scatterlist *sg;
1789        struct mv_sg *mv_sg, *last_sg = NULL;
1790        unsigned int si;
1791
1792        mv_sg = pp->sg_tbl[qc->hw_tag];
1793        for_each_sg(qc->sg, sg, qc->n_elem, si) {
1794                dma_addr_t addr = sg_dma_address(sg);
1795                u32 sg_len = sg_dma_len(sg);
1796
1797                while (sg_len) {
1798                        u32 offset = addr & 0xffff;
1799                        u32 len = sg_len;
1800
1801                        if (offset + len > 0x10000)
1802                                len = 0x10000 - offset;
1803
1804                        mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1805                        mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1806                        mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1807                        mv_sg->reserved = 0;
1808
1809                        sg_len -= len;
1810                        addr += len;
1811
1812                        last_sg = mv_sg;
1813                        mv_sg++;
1814                }
1815        }
1816
1817        if (likely(last_sg))
1818                last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1819        mb(); /* ensure data structure is visible to the chipset */
1820}
1821
1822static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1823{
1824        u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1825                (last ? CRQB_CMD_LAST : 0);
1826        *cmdw = cpu_to_le16(tmp);
1827}
1828
1829/**
1830 *      mv_sff_irq_clear - Clear hardware interrupt after DMA.
1831 *      @ap: Port associated with this ATA transaction.
1832 *
1833 *      We need this only for ATAPI bmdma transactions,
1834 *      as otherwise we experience spurious interrupts
1835 *      after libata-sff handles the bmdma interrupts.
1836 */
1837static void mv_sff_irq_clear(struct ata_port *ap)
1838{
1839        mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1840}
1841
1842/**
1843 *      mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1844 *      @qc: queued command to check for chipset/DMA compatibility.
1845 *
1846 *      The bmdma engines cannot handle speculative data sizes
1847 *      (bytecount under/over flow).  So only allow DMA for
1848 *      data transfer commands with known data sizes.
1849 *
1850 *      LOCKING:
1851 *      Inherited from caller.
1852 */
1853static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1854{
1855        struct scsi_cmnd *scmd = qc->scsicmd;
1856
1857        if (scmd) {
1858                switch (scmd->cmnd[0]) {
1859                case READ_6:
1860                case READ_10:
1861                case READ_12:
1862                case WRITE_6:
1863                case WRITE_10:
1864                case WRITE_12:
1865                case GPCMD_READ_CD:
1866                case GPCMD_SEND_DVD_STRUCTURE:
1867                case GPCMD_SEND_CUE_SHEET:
1868                        return 0; /* DMA is safe */
1869                }
1870        }
1871        return -EOPNOTSUPP; /* use PIO instead */
1872}
1873
1874/**
1875 *      mv_bmdma_setup - Set up BMDMA transaction
1876 *      @qc: queued command to prepare DMA for.
1877 *
1878 *      LOCKING:
1879 *      Inherited from caller.
1880 */
1881static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1882{
1883        struct ata_port *ap = qc->ap;
1884        void __iomem *port_mmio = mv_ap_base(ap);
1885        struct mv_port_priv *pp = ap->private_data;
1886
1887        mv_fill_sg(qc);
1888
1889        /* clear all DMA cmd bits */
1890        writel(0, port_mmio + BMDMA_CMD);
1891
1892        /* load PRD table addr. */
1893        writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16,
1894                port_mmio + BMDMA_PRD_HIGH);
1895        writelfl(pp->sg_tbl_dma[qc->hw_tag],
1896                port_mmio + BMDMA_PRD_LOW);
1897
1898        /* issue r/w command */
1899        ap->ops->sff_exec_command(ap, &qc->tf);
1900}
1901
1902/**
1903 *      mv_bmdma_start - Start a BMDMA transaction
1904 *      @qc: queued command to start DMA on.
1905 *
1906 *      LOCKING:
1907 *      Inherited from caller.
1908 */
1909static void mv_bmdma_start(struct ata_queued_cmd *qc)
1910{
1911        struct ata_port *ap = qc->ap;
1912        void __iomem *port_mmio = mv_ap_base(ap);
1913        unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1914        u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1915
1916        /* start host DMA transaction */
1917        writelfl(cmd, port_mmio + BMDMA_CMD);
1918}
1919
1920/**
1921 *      mv_bmdma_stop - Stop BMDMA transfer
1922 *      @qc: queued command to stop DMA on.
1923 *
1924 *      Clears the ATA_DMA_START flag in the bmdma control register
1925 *
1926 *      LOCKING:
1927 *      Inherited from caller.
1928 */
1929static void mv_bmdma_stop_ap(struct ata_port *ap)
1930{
1931        void __iomem *port_mmio = mv_ap_base(ap);
1932        u32 cmd;
1933
1934        /* clear start/stop bit */
1935        cmd = readl(port_mmio + BMDMA_CMD);
1936        if (cmd & ATA_DMA_START) {
1937                cmd &= ~ATA_DMA_START;
1938                writelfl(cmd, port_mmio + BMDMA_CMD);
1939
1940                /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1941                ata_sff_dma_pause(ap);
1942        }
1943}
1944
1945static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1946{
1947        mv_bmdma_stop_ap(qc->ap);
1948}
1949
1950/**
1951 *      mv_bmdma_status - Read BMDMA status
1952 *      @ap: port for which to retrieve DMA status.
1953 *
1954 *      Read and return equivalent of the sff BMDMA status register.
1955 *
1956 *      LOCKING:
1957 *      Inherited from caller.
1958 */
1959static u8 mv_bmdma_status(struct ata_port *ap)
1960{
1961        void __iomem *port_mmio = mv_ap_base(ap);
1962        u32 reg, status;
1963
1964        /*
1965         * Other bits are valid only if ATA_DMA_ACTIVE==0,
1966         * and the ATA_DMA_INTR bit doesn't exist.
1967         */
1968        reg = readl(port_mmio + BMDMA_STATUS);
1969        if (reg & ATA_DMA_ACTIVE)
1970                status = ATA_DMA_ACTIVE;
1971        else if (reg & ATA_DMA_ERR)
1972                status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1973        else {
1974                /*
1975                 * Just because DMA_ACTIVE is 0 (DMA completed),
1976                 * this does _not_ mean the device is "done".
1977                 * So we should not yet be signalling ATA_DMA_INTR
1978                 * in some cases.  Eg. DSM/TRIM, and perhaps others.
1979                 */
1980                mv_bmdma_stop_ap(ap);
1981                if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1982                        status = 0;
1983                else
1984                        status = ATA_DMA_INTR;
1985        }
1986        return status;
1987}
1988
1989static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1990{
1991        struct ata_taskfile *tf = &qc->tf;
1992        /*
1993         * Workaround for 88SX60x1 FEr SATA#24.
1994         *
1995         * Chip may corrupt WRITEs if multi_count >= 4kB.
1996         * Note that READs are unaffected.
1997         *
1998         * It's not clear if this errata really means "4K bytes",
1999         * or if it always happens for multi_count > 7
2000         * regardless of device sector_size.
2001         *
2002         * So, for safety, any write with multi_count > 7
2003         * gets converted here into a regular PIO write instead:
2004         */
2005        if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
2006                if (qc->dev->multi_count > 7) {
2007                        switch (tf->command) {
2008                        case ATA_CMD_WRITE_MULTI:
2009                                tf->command = ATA_CMD_PIO_WRITE;
2010                                break;
2011                        case ATA_CMD_WRITE_MULTI_FUA_EXT:
2012                                tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
2013                                /* fall through */
2014                        case ATA_CMD_WRITE_MULTI_EXT:
2015                                tf->command = ATA_CMD_PIO_WRITE_EXT;
2016                                break;
2017                        }
2018                }
2019        }
2020}
2021
2022/**
2023 *      mv_qc_prep - Host specific command preparation.
2024 *      @qc: queued command to prepare
2025 *
2026 *      This routine simply redirects to the general purpose routine
2027 *      if command is not DMA.  Else, it handles prep of the CRQB
2028 *      (command request block), does some sanity checking, and calls
2029 *      the SG load routine.
2030 *
2031 *      LOCKING:
2032 *      Inherited from caller.
2033 */
2034static void mv_qc_prep(struct ata_queued_cmd *qc)
2035{
2036        struct ata_port *ap = qc->ap;
2037        struct mv_port_priv *pp = ap->private_data;
2038        __le16 *cw;
2039        struct ata_taskfile *tf = &qc->tf;
2040        u16 flags = 0;
2041        unsigned in_index;
2042
2043        switch (tf->protocol) {
2044        case ATA_PROT_DMA:
2045                if (tf->command == ATA_CMD_DSM)
2046                        return;
2047                /* fall-thru */
2048        case ATA_PROT_NCQ:
2049                break;  /* continue below */
2050        case ATA_PROT_PIO:
2051                mv_rw_multi_errata_sata24(qc);
2052                return;
2053        default:
2054                return;
2055        }
2056
2057        /* Fill in command request block
2058         */
2059        if (!(tf->flags & ATA_TFLAG_WRITE))
2060                flags |= CRQB_FLAG_READ;
2061        WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
2062        flags |= qc->hw_tag << CRQB_TAG_SHIFT;
2063        flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2064
2065        /* get current queue index from software */
2066        in_index = pp->req_idx;
2067
2068        pp->crqb[in_index].sg_addr =
2069                cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
2070        pp->crqb[in_index].sg_addr_hi =
2071                cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
2072        pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2073
2074        cw = &pp->crqb[in_index].ata_cmd[0];
2075
2076        /* Sadly, the CRQB cannot accommodate all registers--there are
2077         * only 11 bytes...so we must pick and choose required
2078         * registers based on the command.  So, we drop feature and
2079         * hob_feature for [RW] DMA commands, but they are needed for
2080         * NCQ.  NCQ will drop hob_nsect, which is not needed there
2081         * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2082         */
2083        switch (tf->command) {
2084        case ATA_CMD_READ:
2085        case ATA_CMD_READ_EXT:
2086        case ATA_CMD_WRITE:
2087        case ATA_CMD_WRITE_EXT:
2088        case ATA_CMD_WRITE_FUA_EXT:
2089                mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2090                break;
2091        case ATA_CMD_FPDMA_READ:
2092        case ATA_CMD_FPDMA_WRITE:
2093                mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2094                mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2095                break;
2096        default:
2097                /* The only other commands EDMA supports in non-queued and
2098                 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2099                 * of which are defined/used by Linux.  If we get here, this
2100                 * driver needs work.
2101                 *
2102                 * FIXME: modify libata to give qc_prep a return value and
2103                 * return error here.
2104                 */
2105                BUG_ON(tf->command);
2106                break;
2107        }
2108        mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2109        mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2110        mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2111        mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2112        mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2113        mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2114        mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2115        mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2116        mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1);    /* last */
2117
2118        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2119                return;
2120        mv_fill_sg(qc);
2121}
2122
2123/**
2124 *      mv_qc_prep_iie - Host specific command preparation.
2125 *      @qc: queued command to prepare
2126 *
2127 *      This routine simply redirects to the general purpose routine
2128 *      if command is not DMA.  Else, it handles prep of the CRQB
2129 *      (command request block), does some sanity checking, and calls
2130 *      the SG load routine.
2131 *
2132 *      LOCKING:
2133 *      Inherited from caller.
2134 */
2135static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2136{
2137        struct ata_port *ap = qc->ap;
2138        struct mv_port_priv *pp = ap->private_data;
2139        struct mv_crqb_iie *crqb;
2140        struct ata_taskfile *tf = &qc->tf;
2141        unsigned in_index;
2142        u32 flags = 0;
2143
2144        if ((tf->protocol != ATA_PROT_DMA) &&
2145            (tf->protocol != ATA_PROT_NCQ))
2146                return;
2147        if (tf->command == ATA_CMD_DSM)
2148                return;  /* use bmdma for this */
2149
2150        /* Fill in Gen IIE command request block */
2151        if (!(tf->flags & ATA_TFLAG_WRITE))
2152                flags |= CRQB_FLAG_READ;
2153
2154        WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
2155        flags |= qc->hw_tag << CRQB_TAG_SHIFT;
2156        flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT;
2157        flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2158
2159        /* get current queue index from software */
2160        in_index = pp->req_idx;
2161
2162        crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2163        crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
2164        crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
2165        crqb->flags = cpu_to_le32(flags);
2166
2167        crqb->ata_cmd[0] = cpu_to_le32(
2168                        (tf->command << 16) |
2169                        (tf->feature << 24)
2170                );
2171        crqb->ata_cmd[1] = cpu_to_le32(
2172                        (tf->lbal << 0) |
2173                        (tf->lbam << 8) |
2174                        (tf->lbah << 16) |
2175                        (tf->device << 24)
2176                );
2177        crqb->ata_cmd[2] = cpu_to_le32(
2178                        (tf->hob_lbal << 0) |
2179                        (tf->hob_lbam << 8) |
2180                        (tf->hob_lbah << 16) |
2181                        (tf->hob_feature << 24)
2182                );
2183        crqb->ata_cmd[3] = cpu_to_le32(
2184                        (tf->nsect << 0) |
2185                        (tf->hob_nsect << 8)
2186                );
2187
2188        if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2189                return;
2190        mv_fill_sg(qc);
2191}
2192
2193/**
2194 *      mv_sff_check_status - fetch device status, if valid
2195 *      @ap: ATA port to fetch status from
2196 *
2197 *      When using command issue via mv_qc_issue_fis(),
2198 *      the initial ATA_BUSY state does not show up in the
2199 *      ATA status (shadow) register.  This can confuse libata!
2200 *
2201 *      So we have a hook here to fake ATA_BUSY for that situation,
2202 *      until the first time a BUSY, DRQ, or ERR bit is seen.
2203 *
2204 *      The rest of the time, it simply returns the ATA status register.
2205 */
2206static u8 mv_sff_check_status(struct ata_port *ap)
2207{
2208        u8 stat = ioread8(ap->ioaddr.status_addr);
2209        struct mv_port_priv *pp = ap->private_data;
2210
2211        if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2212                if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2213                        pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2214                else
2215                        stat = ATA_BUSY;
2216        }
2217        return stat;
2218}
2219
2220/**
2221 *      mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2222 *      @fis: fis to be sent
2223 *      @nwords: number of 32-bit words in the fis
2224 */
2225static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2226{
2227        void __iomem *port_mmio = mv_ap_base(ap);
2228        u32 ifctl, old_ifctl, ifstat;
2229        int i, timeout = 200, final_word = nwords - 1;
2230
2231        /* Initiate FIS transmission mode */
2232        old_ifctl = readl(port_mmio + SATA_IFCTL);
2233        ifctl = 0x100 | (old_ifctl & 0xf);
2234        writelfl(ifctl, port_mmio + SATA_IFCTL);
2235
2236        /* Send all words of the FIS except for the final word */
2237        for (i = 0; i < final_word; ++i)
2238                writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2239
2240        /* Flag end-of-transmission, and then send the final word */
2241        writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2242        writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2243
2244        /*
2245         * Wait for FIS transmission to complete.
2246         * This typically takes just a single iteration.
2247         */
2248        do {
2249                ifstat = readl(port_mmio + SATA_IFSTAT);
2250        } while (!(ifstat & 0x1000) && --timeout);
2251
2252        /* Restore original port configuration */
2253        writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2254
2255        /* See if it worked */
2256        if ((ifstat & 0x3000) != 0x1000) {
2257                ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2258                              __func__, ifstat);
2259                return AC_ERR_OTHER;
2260        }
2261        return 0;
2262}
2263
2264/**
2265 *      mv_qc_issue_fis - Issue a command directly as a FIS
2266 *      @qc: queued command to start
2267 *
2268 *      Note that the ATA shadow registers are not updated
2269 *      after command issue, so the device will appear "READY"
2270 *      if polled, even while it is BUSY processing the command.
2271 *
2272 *      So we use a status hook to fake ATA_BUSY until the drive changes state.
2273 *
2274 *      Note: we don't get updated shadow regs on *completion*
2275 *      of non-data commands. So avoid sending them via this function,
2276 *      as they will appear to have completed immediately.
2277 *
2278 *      GEN_IIE has special registers that we could get the result tf from,
2279 *      but earlier chipsets do not.  For now, we ignore those registers.
2280 */
2281static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2282{
2283        struct ata_port *ap = qc->ap;
2284        struct mv_port_priv *pp = ap->private_data;
2285        struct ata_link *link = qc->dev->link;
2286        u32 fis[5];
2287        int err = 0;
2288
2289        ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2290        err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2291        if (err)
2292                return err;
2293
2294        switch (qc->tf.protocol) {
2295        case ATAPI_PROT_PIO:
2296                pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2297                /* fall through */
2298        case ATAPI_PROT_NODATA:
2299                ap->hsm_task_state = HSM_ST_FIRST;
2300                break;
2301        case ATA_PROT_PIO:
2302                pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2303                if (qc->tf.flags & ATA_TFLAG_WRITE)
2304                        ap->hsm_task_state = HSM_ST_FIRST;
2305                else
2306                        ap->hsm_task_state = HSM_ST;
2307                break;
2308        default:
2309                ap->hsm_task_state = HSM_ST_LAST;
2310                break;
2311        }
2312
2313        if (qc->tf.flags & ATA_TFLAG_POLLING)
2314                ata_sff_queue_pio_task(link, 0);
2315        return 0;
2316}
2317
2318/**
2319 *      mv_qc_issue - Initiate a command to the host
2320 *      @qc: queued command to start
2321 *
2322 *      This routine simply redirects to the general purpose routine
2323 *      if command is not DMA.  Else, it sanity checks our local
2324 *      caches of the request producer/consumer indices then enables
2325 *      DMA and bumps the request producer index.
2326 *
2327 *      LOCKING:
2328 *      Inherited from caller.
2329 */
2330static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2331{
2332        static int limit_warnings = 10;
2333        struct ata_port *ap = qc->ap;
2334        void __iomem *port_mmio = mv_ap_base(ap);
2335        struct mv_port_priv *pp = ap->private_data;
2336        u32 in_index;
2337        unsigned int port_irqs;
2338
2339        pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2340
2341        switch (qc->tf.protocol) {
2342        case ATA_PROT_DMA:
2343                if (qc->tf.command == ATA_CMD_DSM) {
2344                        if (!ap->ops->bmdma_setup)  /* no bmdma on GEN_I */
2345                                return AC_ERR_OTHER;
2346                        break;  /* use bmdma for this */
2347                }
2348                /* fall thru */
2349        case ATA_PROT_NCQ:
2350                mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2351                pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2352                in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2353
2354                /* Write the request in pointer to kick the EDMA to life */
2355                writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2356                                        port_mmio + EDMA_REQ_Q_IN_PTR);
2357                return 0;
2358
2359        case ATA_PROT_PIO:
2360                /*
2361                 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2362                 *
2363                 * Someday, we might implement special polling workarounds
2364                 * for these, but it all seems rather unnecessary since we
2365                 * normally use only DMA for commands which transfer more
2366                 * than a single block of data.
2367                 *
2368                 * Much of the time, this could just work regardless.
2369                 * So for now, just log the incident, and allow the attempt.
2370                 */
2371                if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2372                        --limit_warnings;
2373                        ata_link_warn(qc->dev->link, DRV_NAME
2374                                      ": attempting PIO w/multiple DRQ: "
2375                                      "this may fail due to h/w errata\n");
2376                }
2377                /* fall through */
2378        case ATA_PROT_NODATA:
2379        case ATAPI_PROT_PIO:
2380        case ATAPI_PROT_NODATA:
2381                if (ap->flags & ATA_FLAG_PIO_POLLING)
2382                        qc->tf.flags |= ATA_TFLAG_POLLING;
2383                break;
2384        }
2385
2386        if (qc->tf.flags & ATA_TFLAG_POLLING)
2387                port_irqs = ERR_IRQ;    /* mask device interrupt when polling */
2388        else
2389                port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2390
2391        /*
2392         * We're about to send a non-EDMA capable command to the
2393         * port.  Turn off EDMA so there won't be problems accessing
2394         * shadow block, etc registers.
2395         */
2396        mv_stop_edma(ap);
2397        mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2398        mv_pmp_select(ap, qc->dev->link->pmp);
2399
2400        if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2401                struct mv_host_priv *hpriv = ap->host->private_data;
2402                /*
2403                 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2404                 *
2405                 * After any NCQ error, the READ_LOG_EXT command
2406                 * from libata-eh *must* use mv_qc_issue_fis().
2407                 * Otherwise it might fail, due to chip errata.
2408                 *
2409                 * Rather than special-case it, we'll just *always*
2410                 * use this method here for READ_LOG_EXT, making for
2411                 * easier testing.
2412                 */
2413                if (IS_GEN_II(hpriv))
2414                        return mv_qc_issue_fis(qc);
2415        }
2416        return ata_bmdma_qc_issue(qc);
2417}
2418
2419static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2420{
2421        struct mv_port_priv *pp = ap->private_data;
2422        struct ata_queued_cmd *qc;
2423
2424        if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2425                return NULL;
2426        qc = ata_qc_from_tag(ap, ap->link.active_tag);
2427        if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2428                return qc;
2429        return NULL;
2430}
2431
2432static void mv_pmp_error_handler(struct ata_port *ap)
2433{
2434        unsigned int pmp, pmp_map;
2435        struct mv_port_priv *pp = ap->private_data;
2436
2437        if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2438                /*
2439                 * Perform NCQ error analysis on failed PMPs
2440                 * before we freeze the port entirely.
2441                 *
2442                 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2443                 */
2444                pmp_map = pp->delayed_eh_pmp_map;
2445                pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2446                for (pmp = 0; pmp_map != 0; pmp++) {
2447                        unsigned int this_pmp = (1 << pmp);
2448                        if (pmp_map & this_pmp) {
2449                                struct ata_link *link = &ap->pmp_link[pmp];
2450                                pmp_map &= ~this_pmp;
2451                                ata_eh_analyze_ncq_error(link);
2452                        }
2453                }
2454                ata_port_freeze(ap);
2455        }
2456        sata_pmp_error_handler(ap);
2457}
2458
2459static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2460{
2461        void __iomem *port_mmio = mv_ap_base(ap);
2462
2463        return readl(port_mmio + SATA_TESTCTL) >> 16;
2464}
2465
2466static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2467{
2468        unsigned int pmp;
2469
2470        /*
2471         * Initialize EH info for PMPs which saw device errors
2472         */
2473        for (pmp = 0; pmp_map != 0; pmp++) {
2474                unsigned int this_pmp = (1 << pmp);
2475                if (pmp_map & this_pmp) {
2476                        struct ata_link *link = &ap->pmp_link[pmp];
2477                        struct ata_eh_info *ehi = &link->eh_info;
2478
2479                        pmp_map &= ~this_pmp;
2480                        ata_ehi_clear_desc(ehi);
2481                        ata_ehi_push_desc(ehi, "dev err");
2482                        ehi->err_mask |= AC_ERR_DEV;
2483                        ehi->action |= ATA_EH_RESET;
2484                        ata_link_abort(link);
2485                }
2486        }
2487}
2488
2489static int mv_req_q_empty(struct ata_port *ap)
2490{
2491        void __iomem *port_mmio = mv_ap_base(ap);
2492        u32 in_ptr, out_ptr;
2493
2494        in_ptr  = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2495                        >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2496        out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2497                        >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2498        return (in_ptr == out_ptr);     /* 1 == queue_is_empty */
2499}
2500
2501static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2502{
2503        struct mv_port_priv *pp = ap->private_data;
2504        int failed_links;
2505        unsigned int old_map, new_map;
2506
2507        /*
2508         * Device error during FBS+NCQ operation:
2509         *
2510         * Set a port flag to prevent further I/O being enqueued.
2511         * Leave the EDMA running to drain outstanding commands from this port.
2512         * Perform the post-mortem/EH only when all responses are complete.
2513         * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2514         */
2515        if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2516                pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2517                pp->delayed_eh_pmp_map = 0;
2518        }
2519        old_map = pp->delayed_eh_pmp_map;
2520        new_map = old_map | mv_get_err_pmp_map(ap);
2521
2522        if (old_map != new_map) {
2523                pp->delayed_eh_pmp_map = new_map;
2524                mv_pmp_eh_prep(ap, new_map & ~old_map);
2525        }
2526        failed_links = hweight16(new_map);
2527
2528        ata_port_info(ap,
2529                      "%s: pmp_map=%04x qc_map=%04llx failed_links=%d nr_active_links=%d\n",
2530                      __func__, pp->delayed_eh_pmp_map,
2531                      ap->qc_active, failed_links,
2532                      ap->nr_active_links);
2533
2534        if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2535                mv_process_crpb_entries(ap, pp);
2536                mv_stop_edma(ap);
2537                mv_eh_freeze(ap);
2538                ata_port_info(ap, "%s: done\n", __func__);
2539                return 1;       /* handled */
2540        }
2541        ata_port_info(ap, "%s: waiting\n", __func__);
2542        return 1;       /* handled */
2543}
2544
2545static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2546{
2547        /*
2548         * Possible future enhancement:
2549         *
2550         * FBS+non-NCQ operation is not yet implemented.
2551         * See related notes in mv_edma_cfg().
2552         *
2553         * Device error during FBS+non-NCQ operation:
2554         *
2555         * We need to snapshot the shadow registers for each failed command.
2556         * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2557         */
2558        return 0;       /* not handled */
2559}
2560
2561static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2562{
2563        struct mv_port_priv *pp = ap->private_data;
2564
2565        if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2566                return 0;       /* EDMA was not active: not handled */
2567        if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2568                return 0;       /* FBS was not active: not handled */
2569
2570        if (!(edma_err_cause & EDMA_ERR_DEV))
2571                return 0;       /* non DEV error: not handled */
2572        edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2573        if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2574                return 0;       /* other problems: not handled */
2575
2576        if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2577                /*
2578                 * EDMA should NOT have self-disabled for this case.
2579                 * If it did, then something is wrong elsewhere,
2580                 * and we cannot handle it here.
2581                 */
2582                if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2583                        ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2584                                      __func__, edma_err_cause, pp->pp_flags);
2585                        return 0; /* not handled */
2586                }
2587                return mv_handle_fbs_ncq_dev_err(ap);
2588        } else {
2589                /*
2590                 * EDMA should have self-disabled for this case.
2591                 * If it did not, then something is wrong elsewhere,
2592                 * and we cannot handle it here.
2593                 */
2594                if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2595                        ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2596                                      __func__, edma_err_cause, pp->pp_flags);
2597                        return 0; /* not handled */
2598                }
2599                return mv_handle_fbs_non_ncq_dev_err(ap);
2600        }
2601        return 0;       /* not handled */
2602}
2603
2604static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2605{
2606        struct ata_eh_info *ehi = &ap->link.eh_info;
2607        char *when = "idle";
2608
2609        ata_ehi_clear_desc(ehi);
2610        if (edma_was_enabled) {
2611                when = "EDMA enabled";
2612        } else {
2613                struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2614                if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2615                        when = "polling";
2616        }
2617        ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2618        ehi->err_mask |= AC_ERR_OTHER;
2619        ehi->action   |= ATA_EH_RESET;
2620        ata_port_freeze(ap);
2621}
2622
2623/**
2624 *      mv_err_intr - Handle error interrupts on the port
2625 *      @ap: ATA channel to manipulate
2626 *
2627 *      Most cases require a full reset of the chip's state machine,
2628 *      which also performs a COMRESET.
2629 *      Also, if the port disabled DMA, update our cached copy to match.
2630 *
2631 *      LOCKING:
2632 *      Inherited from caller.
2633 */
2634static void mv_err_intr(struct ata_port *ap)
2635{
2636        void __iomem *port_mmio = mv_ap_base(ap);
2637        u32 edma_err_cause, eh_freeze_mask, serr = 0;
2638        u32 fis_cause = 0;
2639        struct mv_port_priv *pp = ap->private_data;
2640        struct mv_host_priv *hpriv = ap->host->private_data;
2641        unsigned int action = 0, err_mask = 0;
2642        struct ata_eh_info *ehi = &ap->link.eh_info;
2643        struct ata_queued_cmd *qc;
2644        int abort = 0;
2645
2646        /*
2647         * Read and clear the SError and err_cause bits.
2648         * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2649         * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2650         */
2651        sata_scr_read(&ap->link, SCR_ERROR, &serr);
2652        sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2653
2654        edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2655        if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2656                fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2657                writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2658        }
2659        writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2660
2661        if (edma_err_cause & EDMA_ERR_DEV) {
2662                /*
2663                 * Device errors during FIS-based switching operation
2664                 * require special handling.
2665                 */
2666                if (mv_handle_dev_err(ap, edma_err_cause))
2667                        return;
2668        }
2669
2670        qc = mv_get_active_qc(ap);
2671        ata_ehi_clear_desc(ehi);
2672        ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2673                          edma_err_cause, pp->pp_flags);
2674
2675        if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2676                ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2677                if (fis_cause & FIS_IRQ_CAUSE_AN) {
2678                        u32 ec = edma_err_cause &
2679                               ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2680                        sata_async_notification(ap);
2681                        if (!ec)
2682                                return; /* Just an AN; no need for the nukes */
2683                        ata_ehi_push_desc(ehi, "SDB notify");
2684                }
2685        }
2686        /*
2687         * All generations share these EDMA error cause bits:
2688         */
2689        if (edma_err_cause & EDMA_ERR_DEV) {
2690                err_mask |= AC_ERR_DEV;
2691                action |= ATA_EH_RESET;
2692                ata_ehi_push_desc(ehi, "dev error");
2693        }
2694        if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2695                        EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2696                        EDMA_ERR_INTRL_PAR)) {
2697                err_mask |= AC_ERR_ATA_BUS;
2698                action |= ATA_EH_RESET;
2699                ata_ehi_push_desc(ehi, "parity error");
2700        }
2701        if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2702                ata_ehi_hotplugged(ehi);
2703                ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2704                        "dev disconnect" : "dev connect");
2705                action |= ATA_EH_RESET;
2706        }
2707
2708        /*
2709         * Gen-I has a different SELF_DIS bit,
2710         * different FREEZE bits, and no SERR bit:
2711         */
2712        if (IS_GEN_I(hpriv)) {
2713                eh_freeze_mask = EDMA_EH_FREEZE_5;
2714                if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2715                        pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2716                        ata_ehi_push_desc(ehi, "EDMA self-disable");
2717                }
2718        } else {
2719                eh_freeze_mask = EDMA_EH_FREEZE;
2720                if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2721                        pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2722                        ata_ehi_push_desc(ehi, "EDMA self-disable");
2723                }
2724                if (edma_err_cause & EDMA_ERR_SERR) {
2725                        ata_ehi_push_desc(ehi, "SError=%08x", serr);
2726                        err_mask |= AC_ERR_ATA_BUS;
2727                        action |= ATA_EH_RESET;
2728                }
2729        }
2730
2731        if (!err_mask) {
2732                err_mask = AC_ERR_OTHER;
2733                action |= ATA_EH_RESET;
2734        }
2735
2736        ehi->serror |= serr;
2737        ehi->action |= action;
2738
2739        if (qc)
2740                qc->err_mask |= err_mask;
2741        else
2742                ehi->err_mask |= err_mask;
2743
2744        if (err_mask == AC_ERR_DEV) {
2745                /*
2746                 * Cannot do ata_port_freeze() here,
2747                 * because it would kill PIO access,
2748                 * which is needed for further diagnosis.
2749                 */
2750                mv_eh_freeze(ap);
2751                abort = 1;
2752        } else if (edma_err_cause & eh_freeze_mask) {
2753                /*
2754                 * Note to self: ata_port_freeze() calls ata_port_abort()
2755                 */
2756                ata_port_freeze(ap);
2757        } else {
2758                abort = 1;
2759        }
2760
2761        if (abort) {
2762                if (qc)
2763                        ata_link_abort(qc->dev->link);
2764                else
2765                        ata_port_abort(ap);
2766        }
2767}
2768
2769static bool mv_process_crpb_response(struct ata_port *ap,
2770                struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2771{
2772        u8 ata_status;
2773        u16 edma_status = le16_to_cpu(response->flags);
2774
2775        /*
2776         * edma_status from a response queue entry:
2777         *   LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2778         *   MSB is saved ATA status from command completion.
2779         */
2780        if (!ncq_enabled) {
2781                u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2782                if (err_cause) {
2783                        /*
2784                         * Error will be seen/handled by
2785                         * mv_err_intr().  So do nothing at all here.
2786                         */
2787                        return false;
2788                }
2789        }
2790        ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2791        if (!ac_err_mask(ata_status))
2792                return true;
2793        /* else: leave it for mv_err_intr() */
2794        return false;
2795}
2796
2797static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2798{
2799        void __iomem *port_mmio = mv_ap_base(ap);
2800        struct mv_host_priv *hpriv = ap->host->private_data;
2801        u32 in_index;
2802        bool work_done = false;
2803        u32 done_mask = 0;
2804        int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2805
2806        /* Get the hardware queue position index */
2807        in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2808                        >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2809
2810        /* Process new responses from since the last time we looked */
2811        while (in_index != pp->resp_idx) {
2812                unsigned int tag;
2813                struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2814
2815                pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2816
2817                if (IS_GEN_I(hpriv)) {
2818                        /* 50xx: no NCQ, only one command active at a time */
2819                        tag = ap->link.active_tag;
2820                } else {
2821                        /* Gen II/IIE: get command tag from CRPB entry */
2822                        tag = le16_to_cpu(response->id) & 0x1f;
2823                }
2824                if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2825                        done_mask |= 1 << tag;
2826                work_done = true;
2827        }
2828
2829        if (work_done) {
2830                ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2831
2832                /* Update the software queue position index in hardware */
2833                writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2834                         (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2835                         port_mmio + EDMA_RSP_Q_OUT_PTR);
2836        }
2837}
2838
2839static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2840{
2841        struct mv_port_priv *pp;
2842        int edma_was_enabled;
2843
2844        /*
2845         * Grab a snapshot of the EDMA_EN flag setting,
2846         * so that we have a consistent view for this port,
2847         * even if something we call of our routines changes it.
2848         */
2849        pp = ap->private_data;
2850        edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2851        /*
2852         * Process completed CRPB response(s) before other events.
2853         */
2854        if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2855                mv_process_crpb_entries(ap, pp);
2856                if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2857                        mv_handle_fbs_ncq_dev_err(ap);
2858        }
2859        /*
2860         * Handle chip-reported errors, or continue on to handle PIO.
2861         */
2862        if (unlikely(port_cause & ERR_IRQ)) {
2863                mv_err_intr(ap);
2864        } else if (!edma_was_enabled) {
2865                struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2866                if (qc)
2867                        ata_bmdma_port_intr(ap, qc);
2868                else
2869                        mv_unexpected_intr(ap, edma_was_enabled);
2870        }
2871}
2872
2873/**
2874 *      mv_host_intr - Handle all interrupts on the given host controller
2875 *      @host: host specific structure
2876 *      @main_irq_cause: Main interrupt cause register for the chip.
2877 *
2878 *      LOCKING:
2879 *      Inherited from caller.
2880 */
2881static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2882{
2883        struct mv_host_priv *hpriv = host->private_data;
2884        void __iomem *mmio = hpriv->base, *hc_mmio;
2885        unsigned int handled = 0, port;
2886
2887        /* If asserted, clear the "all ports" IRQ coalescing bit */
2888        if (main_irq_cause & ALL_PORTS_COAL_DONE)
2889                writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2890
2891        for (port = 0; port < hpriv->n_ports; port++) {
2892                struct ata_port *ap = host->ports[port];
2893                unsigned int p, shift, hardport, port_cause;
2894
2895                MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2896                /*
2897                 * Each hc within the host has its own hc_irq_cause register,
2898                 * where the interrupting ports bits get ack'd.
2899                 */
2900                if (hardport == 0) {    /* first port on this hc ? */
2901                        u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2902                        u32 port_mask, ack_irqs;
2903                        /*
2904                         * Skip this entire hc if nothing pending for any ports
2905                         */
2906                        if (!hc_cause) {
2907                                port += MV_PORTS_PER_HC - 1;
2908                                continue;
2909                        }
2910                        /*
2911                         * We don't need/want to read the hc_irq_cause register,
2912                         * because doing so hurts performance, and
2913                         * main_irq_cause already gives us everything we need.
2914                         *
2915                         * But we do have to *write* to the hc_irq_cause to ack
2916                         * the ports that we are handling this time through.
2917                         *
2918                         * This requires that we create a bitmap for those
2919                         * ports which interrupted us, and use that bitmap
2920                         * to ack (only) those ports via hc_irq_cause.
2921                         */
2922                        ack_irqs = 0;
2923                        if (hc_cause & PORTS_0_3_COAL_DONE)
2924                                ack_irqs = HC_COAL_IRQ;
2925                        for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2926                                if ((port + p) >= hpriv->n_ports)
2927                                        break;
2928                                port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2929                                if (hc_cause & port_mask)
2930                                        ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2931                        }
2932                        hc_mmio = mv_hc_base_from_port(mmio, port);
2933                        writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2934                        handled = 1;
2935                }
2936                /*
2937                 * Handle interrupts signalled for this port:
2938                 */
2939                port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2940                if (port_cause)
2941                        mv_port_intr(ap, port_cause);
2942        }
2943        return handled;
2944}
2945
2946static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2947{
2948        struct mv_host_priv *hpriv = host->private_data;
2949        struct ata_port *ap;
2950        struct ata_queued_cmd *qc;
2951        struct ata_eh_info *ehi;
2952        unsigned int i, err_mask, printed = 0;
2953        u32 err_cause;
2954
2955        err_cause = readl(mmio + hpriv->irq_cause_offset);
2956
2957        dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
2958
2959        DPRINTK("All regs @ PCI error\n");
2960        mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2961
2962        writelfl(0, mmio + hpriv->irq_cause_offset);
2963
2964        for (i = 0; i < host->n_ports; i++) {
2965                ap = host->ports[i];
2966                if (!ata_link_offline(&ap->link)) {
2967                        ehi = &ap->link.eh_info;
2968                        ata_ehi_clear_desc(ehi);
2969                        if (!printed++)
2970                                ata_ehi_push_desc(ehi,
2971                                        "PCI err cause 0x%08x", err_cause);
2972                        err_mask = AC_ERR_HOST_BUS;
2973                        ehi->action = ATA_EH_RESET;
2974                        qc = ata_qc_from_tag(ap, ap->link.active_tag);
2975                        if (qc)
2976                                qc->err_mask |= err_mask;
2977                        else
2978                                ehi->err_mask |= err_mask;
2979
2980                        ata_port_freeze(ap);
2981                }
2982        }
2983        return 1;       /* handled */
2984}
2985
2986/**
2987 *      mv_interrupt - Main interrupt event handler
2988 *      @irq: unused
2989 *      @dev_instance: private data; in this case the host structure
2990 *
2991 *      Read the read only register to determine if any host
2992 *      controllers have pending interrupts.  If so, call lower level
2993 *      routine to handle.  Also check for PCI errors which are only
2994 *      reported here.
2995 *
2996 *      LOCKING:
2997 *      This routine holds the host lock while processing pending
2998 *      interrupts.
2999 */
3000static irqreturn_t mv_interrupt(int irq, void *dev_instance)
3001{
3002        struct ata_host *host = dev_instance;
3003        struct mv_host_priv *hpriv = host->private_data;
3004        unsigned int handled = 0;
3005        int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
3006        u32 main_irq_cause, pending_irqs;
3007
3008        spin_lock(&host->lock);
3009
3010        /* for MSI:  block new interrupts while in here */
3011        if (using_msi)
3012                mv_write_main_irq_mask(0, hpriv);
3013
3014        main_irq_cause = readl(hpriv->main_irq_cause_addr);
3015        pending_irqs   = main_irq_cause & hpriv->main_irq_mask;
3016        /*
3017         * Deal with cases where we either have nothing pending, or have read
3018         * a bogus register value which can indicate HW removal or PCI fault.
3019         */
3020        if (pending_irqs && main_irq_cause != 0xffffffffU) {
3021                if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
3022                        handled = mv_pci_error(host, hpriv->base);
3023                else
3024                        handled = mv_host_intr(host, pending_irqs);
3025        }
3026
3027        /* for MSI: unmask; interrupt cause bits will retrigger now */
3028        if (using_msi)
3029                mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
3030
3031        spin_unlock(&host->lock);
3032
3033        return IRQ_RETVAL(handled);
3034}
3035
3036static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3037{
3038        unsigned int ofs;
3039
3040        switch (sc_reg_in) {
3041        case SCR_STATUS:
3042        case SCR_ERROR:
3043        case SCR_CONTROL:
3044                ofs = sc_reg_in * sizeof(u32);
3045                break;
3046        default:
3047                ofs = 0xffffffffU;
3048                break;
3049        }
3050        return ofs;
3051}
3052
3053static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3054{
3055        struct mv_host_priv *hpriv = link->ap->host->private_data;
3056        void __iomem *mmio = hpriv->base;
3057        void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3058        unsigned int ofs = mv5_scr_offset(sc_reg_in);
3059
3060        if (ofs != 0xffffffffU) {
3061                *val = readl(addr + ofs);
3062                return 0;
3063        } else
3064                return -EINVAL;
3065}
3066
3067static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3068{
3069        struct mv_host_priv *hpriv = link->ap->host->private_data;
3070        void __iomem *mmio = hpriv->base;
3071        void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3072        unsigned int ofs = mv5_scr_offset(sc_reg_in);
3073
3074        if (ofs != 0xffffffffU) {
3075                writelfl(val, addr + ofs);
3076                return 0;
3077        } else
3078                return -EINVAL;
3079}
3080
3081static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3082{
3083        struct pci_dev *pdev = to_pci_dev(host->dev);
3084        int early_5080;
3085
3086        early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3087
3088        if (!early_5080) {
3089                u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3090                tmp |= (1 << 0);
3091                writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3092        }
3093
3094        mv_reset_pci_bus(host, mmio);
3095}
3096
3097static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3098{
3099        writel(0x0fcfffff, mmio + FLASH_CTL);
3100}
3101
3102static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3103                           void __iomem *mmio)
3104{
3105        void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3106        u32 tmp;
3107
3108        tmp = readl(phy_mmio + MV5_PHY_MODE);
3109
3110        hpriv->signal[idx].pre = tmp & 0x1800;  /* bits 12:11 */
3111        hpriv->signal[idx].amps = tmp & 0xe0;   /* bits 7:5 */
3112}
3113
3114static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3115{
3116        u32 tmp;
3117
3118        writel(0, mmio + GPIO_PORT_CTL);
3119
3120        /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3121
3122        tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3123        tmp |= ~(1 << 0);
3124        writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3125}
3126
3127static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3128                           unsigned int port)
3129{
3130        void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3131        const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3132        u32 tmp;
3133        int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3134
3135        if (fix_apm_sq) {
3136                tmp = readl(phy_mmio + MV5_LTMODE);
3137                tmp |= (1 << 19);
3138                writel(tmp, phy_mmio + MV5_LTMODE);
3139
3140                tmp = readl(phy_mmio + MV5_PHY_CTL);
3141                tmp &= ~0x3;
3142                tmp |= 0x1;
3143                writel(tmp, phy_mmio + MV5_PHY_CTL);
3144        }
3145
3146        tmp = readl(phy_mmio + MV5_PHY_MODE);
3147        tmp &= ~mask;
3148        tmp |= hpriv->signal[port].pre;
3149        tmp |= hpriv->signal[port].amps;
3150        writel(tmp, phy_mmio + MV5_PHY_MODE);
3151}
3152
3153
3154#undef ZERO
3155#define ZERO(reg) writel(0, port_mmio + (reg))
3156static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3157                             unsigned int port)
3158{
3159        void __iomem *port_mmio = mv_port_base(mmio, port);
3160
3161        mv_reset_channel(hpriv, mmio, port);
3162
3163        ZERO(0x028);    /* command */
3164        writel(0x11f, port_mmio + EDMA_CFG);
3165        ZERO(0x004);    /* timer */
3166        ZERO(0x008);    /* irq err cause */
3167        ZERO(0x00c);    /* irq err mask */
3168        ZERO(0x010);    /* rq bah */
3169        ZERO(0x014);    /* rq inp */
3170        ZERO(0x018);    /* rq outp */
3171        ZERO(0x01c);    /* respq bah */
3172        ZERO(0x024);    /* respq outp */
3173        ZERO(0x020);    /* respq inp */
3174        ZERO(0x02c);    /* test control */
3175        writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3176}
3177#undef ZERO
3178
3179#define ZERO(reg) writel(0, hc_mmio + (reg))
3180static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3181                        unsigned int hc)
3182{
3183        void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3184        u32 tmp;
3185
3186        ZERO(0x00c);
3187        ZERO(0x010);
3188        ZERO(0x014);
3189        ZERO(0x018);
3190
3191        tmp = readl(hc_mmio + 0x20);
3192        tmp &= 0x1c1c1c1c;
3193        tmp |= 0x03030303;
3194        writel(tmp, hc_mmio + 0x20);
3195}
3196#undef ZERO
3197
3198static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3199                        unsigned int n_hc)
3200{
3201        unsigned int hc, port;
3202
3203        for (hc = 0; hc < n_hc; hc++) {
3204                for (port = 0; port < MV_PORTS_PER_HC; port++)
3205                        mv5_reset_hc_port(hpriv, mmio,
3206                                          (hc * MV_PORTS_PER_HC) + port);
3207
3208                mv5_reset_one_hc(hpriv, mmio, hc);
3209        }
3210
3211        return 0;
3212}
3213
3214#undef ZERO
3215#define ZERO(reg) writel(0, mmio + (reg))
3216static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3217{
3218        struct mv_host_priv *hpriv = host->private_data;
3219        u32 tmp;
3220
3221        tmp = readl(mmio + MV_PCI_MODE);
3222        tmp &= 0xff00ffff;
3223        writel(tmp, mmio + MV_PCI_MODE);
3224
3225        ZERO(MV_PCI_DISC_TIMER);
3226        ZERO(MV_PCI_MSI_TRIGGER);
3227        writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3228        ZERO(MV_PCI_SERR_MASK);
3229        ZERO(hpriv->irq_cause_offset);
3230        ZERO(hpriv->irq_mask_offset);
3231        ZERO(MV_PCI_ERR_LOW_ADDRESS);
3232        ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3233        ZERO(MV_PCI_ERR_ATTRIBUTE);
3234        ZERO(MV_PCI_ERR_COMMAND);
3235}
3236#undef ZERO
3237
3238static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3239{
3240        u32 tmp;
3241
3242        mv5_reset_flash(hpriv, mmio);
3243
3244        tmp = readl(mmio + GPIO_PORT_CTL);
3245        tmp &= 0x3;
3246        tmp |= (1 << 5) | (1 << 6);
3247        writel(tmp, mmio + GPIO_PORT_CTL);
3248}
3249
3250/**
3251 *      mv6_reset_hc - Perform the 6xxx global soft reset
3252 *      @mmio: base address of the HBA
3253 *
3254 *      This routine only applies to 6xxx parts.
3255 *
3256 *      LOCKING:
3257 *      Inherited from caller.
3258 */
3259static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3260                        unsigned int n_hc)
3261{
3262        void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3263        int i, rc = 0;
3264        u32 t;
3265
3266        /* Following procedure defined in PCI "main command and status
3267         * register" table.
3268         */
3269        t = readl(reg);
3270        writel(t | STOP_PCI_MASTER, reg);
3271
3272        for (i = 0; i < 1000; i++) {
3273                udelay(1);
3274                t = readl(reg);
3275                if (PCI_MASTER_EMPTY & t)
3276                        break;
3277        }
3278        if (!(PCI_MASTER_EMPTY & t)) {
3279                printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3280                rc = 1;
3281                goto done;
3282        }
3283
3284        /* set reset */
3285        i = 5;
3286        do {
3287                writel(t | GLOB_SFT_RST, reg);
3288                t = readl(reg);
3289                udelay(1);
3290        } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3291
3292        if (!(GLOB_SFT_RST & t)) {
3293                printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3294                rc = 1;
3295                goto done;
3296        }
3297
3298        /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3299        i = 5;
3300        do {
3301                writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3302                t = readl(reg);
3303                udelay(1);
3304        } while ((GLOB_SFT_RST & t) && (i-- > 0));
3305
3306        if (GLOB_SFT_RST & t) {
3307                printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3308                rc = 1;
3309        }
3310done:
3311        return rc;
3312}
3313
3314static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3315                           void __iomem *mmio)
3316{
3317        void __iomem *port_mmio;
3318        u32 tmp;
3319
3320        tmp = readl(mmio + RESET_CFG);
3321        if ((tmp & (1 << 0)) == 0) {
3322                hpriv->signal[idx].amps = 0x7 << 8;
3323                hpriv->signal[idx].pre = 0x1 << 5;
3324                return;
3325        }
3326
3327        port_mmio = mv_port_base(mmio, idx);
3328        tmp = readl(port_mmio + PHY_MODE2);
3329
3330        hpriv->signal[idx].amps = tmp & 0x700;  /* bits 10:8 */
3331        hpriv->signal[idx].pre = tmp & 0xe0;    /* bits 7:5 */
3332}
3333
3334static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3335{
3336        writel(0x00000060, mmio + GPIO_PORT_CTL);
3337}
3338
3339static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3340                           unsigned int port)
3341{
3342        void __iomem *port_mmio = mv_port_base(mmio, port);
3343
3344        u32 hp_flags = hpriv->hp_flags;
3345        int fix_phy_mode2 =
3346                hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3347        int fix_phy_mode4 =
3348                hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3349        u32 m2, m3;
3350
3351        if (fix_phy_mode2) {
3352                m2 = readl(port_mmio + PHY_MODE2);
3353                m2 &= ~(1 << 16);
3354                m2 |= (1 << 31);
3355                writel(m2, port_mmio + PHY_MODE2);
3356
3357                udelay(200);
3358
3359                m2 = readl(port_mmio + PHY_MODE2);
3360                m2 &= ~((1 << 16) | (1 << 31));
3361                writel(m2, port_mmio + PHY_MODE2);
3362
3363                udelay(200);
3364        }
3365
3366        /*
3367         * Gen-II/IIe PHY_MODE3 errata RM#2:
3368         * Achieves better receiver noise performance than the h/w default:
3369         */
3370        m3 = readl(port_mmio + PHY_MODE3);
3371        m3 = (m3 & 0x1f) | (0x5555601 << 5);
3372
3373        /* Guideline 88F5182 (GL# SATA-S11) */
3374        if (IS_SOC(hpriv))
3375                m3 &= ~0x1c;
3376
3377        if (fix_phy_mode4) {
3378                u32 m4 = readl(port_mmio + PHY_MODE4);
3379                /*
3380                 * Enforce reserved-bit restrictions on GenIIe devices only.
3381                 * For earlier chipsets, force only the internal config field
3382                 *  (workaround for errata FEr SATA#10 part 1).
3383                 */
3384                if (IS_GEN_IIE(hpriv))
3385                        m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3386                else
3387                        m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3388                writel(m4, port_mmio + PHY_MODE4);
3389        }
3390        /*
3391         * Workaround for 60x1-B2 errata SATA#13:
3392         * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3393         * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3394         * Or ensure we use writelfl() when writing PHY_MODE4.
3395         */
3396        writel(m3, port_mmio + PHY_MODE3);
3397
3398        /* Revert values of pre-emphasis and signal amps to the saved ones */
3399        m2 = readl(port_mmio + PHY_MODE2);
3400
3401        m2 &= ~MV_M2_PREAMP_MASK;
3402        m2 |= hpriv->signal[port].amps;
3403        m2 |= hpriv->signal[port].pre;
3404        m2 &= ~(1 << 16);
3405
3406        /* according to mvSata 3.6.1, some IIE values are fixed */
3407        if (IS_GEN_IIE(hpriv)) {
3408                m2 &= ~0xC30FF01F;
3409                m2 |= 0x0000900F;
3410        }
3411
3412        writel(m2, port_mmio + PHY_MODE2);
3413}
3414
3415/* TODO: use the generic LED interface to configure the SATA Presence */
3416/* & Acitivy LEDs on the board */
3417static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3418                                      void __iomem *mmio)
3419{
3420        return;
3421}
3422
3423static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3424                           void __iomem *mmio)
3425{
3426        void __iomem *port_mmio;
3427        u32 tmp;
3428
3429        port_mmio = mv_port_base(mmio, idx);
3430        tmp = readl(port_mmio + PHY_MODE2);
3431
3432        hpriv->signal[idx].amps = tmp & 0x700;  /* bits 10:8 */
3433        hpriv->signal[idx].pre = tmp & 0xe0;    /* bits 7:5 */
3434}
3435
3436#undef ZERO
3437#define ZERO(reg) writel(0, port_mmio + (reg))
3438static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3439                                        void __iomem *mmio, unsigned int port)
3440{
3441        void __iomem *port_mmio = mv_port_base(mmio, port);
3442
3443        mv_reset_channel(hpriv, mmio, port);
3444
3445        ZERO(0x028);            /* command */
3446        writel(0x101f, port_mmio + EDMA_CFG);
3447        ZERO(0x004);            /* timer */
3448        ZERO(0x008);            /* irq err cause */
3449        ZERO(0x00c);            /* irq err mask */
3450        ZERO(0x010);            /* rq bah */
3451        ZERO(0x014);            /* rq inp */
3452        ZERO(0x018);            /* rq outp */
3453        ZERO(0x01c);            /* respq bah */
3454        ZERO(0x024);            /* respq outp */
3455        ZERO(0x020);            /* respq inp */
3456        ZERO(0x02c);            /* test control */
3457        writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3458}
3459
3460#undef ZERO
3461
3462#define ZERO(reg) writel(0, hc_mmio + (reg))
3463static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3464                                       void __iomem *mmio)
3465{
3466        void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3467
3468        ZERO(0x00c);
3469        ZERO(0x010);
3470        ZERO(0x014);
3471
3472}
3473
3474#undef ZERO
3475
3476static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3477                                  void __iomem *mmio, unsigned int n_hc)
3478{
3479        unsigned int port;
3480
3481        for (port = 0; port < hpriv->n_ports; port++)
3482                mv_soc_reset_hc_port(hpriv, mmio, port);
3483
3484        mv_soc_reset_one_hc(hpriv, mmio);
3485
3486        return 0;
3487}
3488
3489static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3490                                      void __iomem *mmio)
3491{
3492        return;
3493}
3494
3495static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3496{
3497        return;
3498}
3499
3500static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3501                                  void __iomem *mmio, unsigned int port)
3502{
3503        void __iomem *port_mmio = mv_port_base(mmio, port);
3504        u32     reg;
3505
3506        reg = readl(port_mmio + PHY_MODE3);
3507        reg &= ~(0x3 << 27);    /* SELMUPF (bits 28:27) to 1 */
3508        reg |= (0x1 << 27);
3509        reg &= ~(0x3 << 29);    /* SELMUPI (bits 30:29) to 1 */
3510        reg |= (0x1 << 29);
3511        writel(reg, port_mmio + PHY_MODE3);
3512
3513        reg = readl(port_mmio + PHY_MODE4);
3514        reg &= ~0x1;    /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3515        reg |= (0x1 << 16);
3516        writel(reg, port_mmio + PHY_MODE4);
3517
3518        reg = readl(port_mmio + PHY_MODE9_GEN2);
3519        reg &= ~0xf;    /* TXAMP[3:0] (bits 3:0) to 8 */
3520        reg |= 0x8;
3521        reg &= ~(0x1 << 14);    /* TXAMP[4] (bit 14) to 0 */
3522        writel(reg, port_mmio + PHY_MODE9_GEN2);
3523
3524        reg = readl(port_mmio + PHY_MODE9_GEN1);
3525        reg &= ~0xf;    /* TXAMP[3:0] (bits 3:0) to 8 */
3526        reg |= 0x8;
3527        reg &= ~(0x1 << 14);    /* TXAMP[4] (bit 14) to 0 */
3528        writel(reg, port_mmio + PHY_MODE9_GEN1);
3529}
3530
3531/**
3532 *      soc_is_65 - check if the soc is 65 nano device
3533 *
3534 *      Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3535 *      register, this register should contain non-zero value and it exists only
3536 *      in the 65 nano devices, when reading it from older devices we get 0.
3537 */
3538static bool soc_is_65n(struct mv_host_priv *hpriv)
3539{
3540        void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3541
3542        if (readl(port0_mmio + PHYCFG_OFS))
3543                return true;
3544        return false;
3545}
3546
3547static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3548{
3549        u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3550
3551        ifcfg = (ifcfg & 0xf7f) | 0x9b1000;     /* from chip spec */
3552        if (want_gen2i)
3553                ifcfg |= (1 << 7);              /* enable gen2i speed */
3554        writelfl(ifcfg, port_mmio + SATA_IFCFG);
3555}
3556
3557static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3558                             unsigned int port_no)
3559{
3560        void __iomem *port_mmio = mv_port_base(mmio, port_no);
3561
3562        /*
3563         * The datasheet warns against setting EDMA_RESET when EDMA is active
3564         * (but doesn't say what the problem might be).  So we first try
3565         * to disable the EDMA engine before doing the EDMA_RESET operation.
3566         */
3567        mv_stop_edma_engine(port_mmio);
3568        writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3569
3570        if (!IS_GEN_I(hpriv)) {
3571                /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3572                mv_setup_ifcfg(port_mmio, 1);
3573        }
3574        /*
3575         * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3576         * link, and physical layers.  It resets all SATA interface registers
3577         * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3578         */
3579        writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3580        udelay(25);     /* allow reset propagation */
3581        writelfl(0, port_mmio + EDMA_CMD);
3582
3583        hpriv->ops->phy_errata(hpriv, mmio, port_no);
3584
3585        if (IS_GEN_I(hpriv))
3586                usleep_range(500, 1000);
3587}
3588
3589static void mv_pmp_select(struct ata_port *ap, int pmp)
3590{
3591        if (sata_pmp_supported(ap)) {
3592                void __iomem *port_mmio = mv_ap_base(ap);
3593                u32 reg = readl(port_mmio + SATA_IFCTL);
3594                int old = reg & 0xf;
3595
3596                if (old != pmp) {
3597                        reg = (reg & ~0xf) | pmp;
3598                        writelfl(reg, port_mmio + SATA_IFCTL);
3599                }
3600        }
3601}
3602
3603static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3604                                unsigned long deadline)
3605{
3606        mv_pmp_select(link->ap, sata_srst_pmp(link));
3607        return sata_std_hardreset(link, class, deadline);
3608}
3609
3610static int mv_softreset(struct ata_link *link, unsigned int *class,
3611                                unsigned long deadline)
3612{
3613        mv_pmp_select(link->ap, sata_srst_pmp(link));
3614        return ata_sff_softreset(link, class, deadline);
3615}
3616
3617static int mv_hardreset(struct ata_link *link, unsigned int *class,
3618                        unsigned long deadline)
3619{
3620        struct ata_port *ap = link->ap;
3621        struct mv_host_priv *hpriv = ap->host->private_data;
3622        struct mv_port_priv *pp = ap->private_data;
3623        void __iomem *mmio = hpriv->base;
3624        int rc, attempts = 0, extra = 0;
3625        u32 sstatus;
3626        bool online;
3627
3628        mv_reset_channel(hpriv, mmio, ap->port_no);
3629        pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3630        pp->pp_flags &=
3631          ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3632
3633        /* Workaround for errata FEr SATA#10 (part 2) */
3634        do {
3635                const unsigned long *timing =
3636                                sata_ehc_deb_timing(&link->eh_context);
3637
3638                rc = sata_link_hardreset(link, timing, deadline + extra,
3639                                         &online, NULL);
3640                rc = online ? -EAGAIN : rc;
3641                if (rc)
3642                        return rc;
3643                sata_scr_read(link, SCR_STATUS, &sstatus);
3644                if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3645                        /* Force 1.5gb/s link speed and try again */
3646                        mv_setup_ifcfg(mv_ap_base(ap), 0);
3647                        if (time_after(jiffies + HZ, deadline))
3648                                extra = HZ; /* only extend it once, max */
3649                }
3650        } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3651        mv_save_cached_regs(ap);
3652        mv_edma_cfg(ap, 0, 0);
3653
3654        return rc;
3655}
3656
3657static void mv_eh_freeze(struct ata_port *ap)
3658{
3659        mv_stop_edma(ap);
3660        mv_enable_port_irqs(ap, 0);
3661}
3662
3663static void mv_eh_thaw(struct ata_port *ap)
3664{
3665        struct mv_host_priv *hpriv = ap->host->private_data;
3666        unsigned int port = ap->port_no;
3667        unsigned int hardport = mv_hardport_from_port(port);
3668        void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3669        void __iomem *port_mmio = mv_ap_base(ap);
3670        u32 hc_irq_cause;
3671
3672        /* clear EDMA errors on this port */
3673        writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3674
3675        /* clear pending irq events */
3676        hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3677        writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3678
3679        mv_enable_port_irqs(ap, ERR_IRQ);
3680}
3681
3682/**
3683 *      mv_port_init - Perform some early initialization on a single port.
3684 *      @port: libata data structure storing shadow register addresses
3685 *      @port_mmio: base address of the port
3686 *
3687 *      Initialize shadow register mmio addresses, clear outstanding
3688 *      interrupts on the port, and unmask interrupts for the future
3689 *      start of the port.
3690 *
3691 *      LOCKING:
3692 *      Inherited from caller.
3693 */
3694static void mv_port_init(struct ata_ioports *port,  void __iomem *port_mmio)
3695{
3696        void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3697
3698        /* PIO related setup
3699         */
3700        port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3701        port->error_addr =
3702                port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3703        port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3704        port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3705        port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3706        port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3707        port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3708        port->status_addr =
3709                port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3710        /* special case: control/altstatus doesn't have ATA_REG_ address */
3711        port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3712
3713        /* Clear any currently outstanding port interrupt conditions */
3714        serr = port_mmio + mv_scr_offset(SCR_ERROR);
3715        writelfl(readl(serr), serr);
3716        writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3717
3718        /* unmask all non-transient EDMA error interrupts */
3719        writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3720
3721        VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3722                readl(port_mmio + EDMA_CFG),
3723                readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3724                readl(port_mmio + EDMA_ERR_IRQ_MASK));
3725}
3726
3727static unsigned int mv_in_pcix_mode(struct ata_host *host)
3728{
3729        struct mv_host_priv *hpriv = host->private_data;
3730        void __iomem *mmio = hpriv->base;
3731        u32 reg;
3732
3733        if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3734                return 0;       /* not PCI-X capable */
3735        reg = readl(mmio + MV_PCI_MODE);
3736        if ((reg & MV_PCI_MODE_MASK) == 0)
3737                return 0;       /* conventional PCI mode */
3738        return 1;       /* chip is in PCI-X mode */
3739}
3740
3741static int mv_pci_cut_through_okay(struct ata_host *host)
3742{
3743        struct mv_host_priv *hpriv = host->private_data;
3744        void __iomem *mmio = hpriv->base;
3745        u32 reg;
3746
3747        if (!mv_in_pcix_mode(host)) {
3748                reg = readl(mmio + MV_PCI_COMMAND);
3749                if (reg & MV_PCI_COMMAND_MRDTRIG)
3750                        return 0; /* not okay */
3751        }
3752        return 1; /* okay */
3753}
3754
3755static void mv_60x1b2_errata_pci7(struct ata_host *host)
3756{
3757        struct mv_host_priv *hpriv = host->private_data;
3758        void __iomem *mmio = hpriv->base;
3759
3760        /* workaround for 60x1-B2 errata PCI#7 */
3761        if (mv_in_pcix_mode(host)) {
3762                u32 reg = readl(mmio + MV_PCI_COMMAND);
3763                writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3764        }
3765}
3766
3767static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3768{
3769        struct pci_dev *pdev = to_pci_dev(host->dev);
3770        struct mv_host_priv *hpriv = host->private_data;
3771        u32 hp_flags = hpriv->hp_flags;
3772
3773        switch (board_idx) {
3774        case chip_5080:
3775                hpriv->ops = &mv5xxx_ops;
3776                hp_flags |= MV_HP_GEN_I;
3777
3778                switch (pdev->revision) {
3779                case 0x1:
3780                        hp_flags |= MV_HP_ERRATA_50XXB0;
3781                        break;
3782                case 0x3:
3783                        hp_flags |= MV_HP_ERRATA_50XXB2;
3784                        break;
3785                default:
3786                        dev_warn(&pdev->dev,
3787                                 "Applying 50XXB2 workarounds to unknown rev\n");
3788                        hp_flags |= MV_HP_ERRATA_50XXB2;
3789                        break;
3790                }
3791                break;
3792
3793        case chip_504x:
3794        case chip_508x:
3795                hpriv->ops = &mv5xxx_ops;
3796                hp_flags |= MV_HP_GEN_I;
3797
3798                switch (pdev->revision) {
3799                case 0x0:
3800                        hp_flags |= MV_HP_ERRATA_50XXB0;
3801                        break;
3802                case 0x3:
3803                        hp_flags |= MV_HP_ERRATA_50XXB2;
3804                        break;
3805                default:
3806                        dev_warn(&pdev->dev,
3807                                 "Applying B2 workarounds to unknown rev\n");
3808                        hp_flags |= MV_HP_ERRATA_50XXB2;
3809                        break;
3810                }
3811                break;
3812
3813        case chip_604x:
3814        case chip_608x:
3815                hpriv->ops = &mv6xxx_ops;
3816                hp_flags |= MV_HP_GEN_II;
3817
3818                switch (pdev->revision) {
3819                case 0x7:
3820                        mv_60x1b2_errata_pci7(host);
3821                        hp_flags |= MV_HP_ERRATA_60X1B2;
3822                        break;
3823                case 0x9:
3824                        hp_flags |= MV_HP_ERRATA_60X1C0;
3825                        break;
3826                default:
3827                        dev_warn(&pdev->dev,
3828                                 "Applying B2 workarounds to unknown rev\n");
3829                        hp_flags |= MV_HP_ERRATA_60X1B2;
3830                        break;
3831                }
3832                break;
3833
3834        case chip_7042:
3835                hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3836                if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3837                    (pdev->device == 0x2300 || pdev->device == 0x2310))
3838                {
3839                        /*
3840                         * Highpoint RocketRAID PCIe 23xx series cards:
3841                         *
3842                         * Unconfigured drives are treated as "Legacy"
3843                         * by the BIOS, and it overwrites sector 8 with
3844                         * a "Lgcy" metadata block prior to Linux boot.
3845                         *
3846                         * Configured drives (RAID or JBOD) leave sector 8
3847                         * alone, but instead overwrite a high numbered
3848                         * sector for the RAID metadata.  This sector can
3849                         * be determined exactly, by truncating the physical
3850                         * drive capacity to a nice even GB value.
3851                         *
3852                         * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3853                         *
3854                         * Warn the user, lest they think we're just buggy.
3855                         */
3856                        printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3857                                " BIOS CORRUPTS DATA on all attached drives,"
3858                                " regardless of if/how they are configured."
3859                                " BEWARE!\n");
3860                        printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3861                                " use sectors 8-9 on \"Legacy\" drives,"
3862                                " and avoid the final two gigabytes on"
3863                                " all RocketRAID BIOS initialized drives.\n");
3864                }
3865                /* fall through */
3866        case chip_6042:
3867                hpriv->ops = &mv6xxx_ops;
3868                hp_flags |= MV_HP_GEN_IIE;
3869                if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3870                        hp_flags |= MV_HP_CUT_THROUGH;
3871
3872                switch (pdev->revision) {
3873                case 0x2: /* Rev.B0: the first/only public release */
3874                        hp_flags |= MV_HP_ERRATA_60X1C0;
3875                        break;
3876                default:
3877                        dev_warn(&pdev->dev,
3878                                 "Applying 60X1C0 workarounds to unknown rev\n");
3879                        hp_flags |= MV_HP_ERRATA_60X1C0;
3880                        break;
3881                }
3882                break;
3883        case chip_soc:
3884                if (soc_is_65n(hpriv))
3885                        hpriv->ops = &mv_soc_65n_ops;
3886                else
3887                        hpriv->ops = &mv_soc_ops;
3888                hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3889                        MV_HP_ERRATA_60X1C0;
3890                break;
3891
3892        default:
3893                dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
3894                return 1;
3895        }
3896
3897        hpriv->hp_flags = hp_flags;
3898        if (hp_flags & MV_HP_PCIE) {
3899                hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3900                hpriv->irq_mask_offset  = PCIE_IRQ_MASK;
3901                hpriv->unmask_all_irqs  = PCIE_UNMASK_ALL_IRQS;
3902        } else {
3903                hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3904                hpriv->irq_mask_offset  = PCI_IRQ_MASK;
3905                hpriv->unmask_all_irqs  = PCI_UNMASK_ALL_IRQS;
3906        }
3907
3908        return 0;
3909}
3910
3911/**
3912 *      mv_init_host - Perform some early initialization of the host.
3913 *      @host: ATA host to initialize
3914 *
3915 *      If possible, do an early global reset of the host.  Then do
3916 *      our port init and clear/unmask all/relevant host interrupts.
3917 *
3918 *      LOCKING:
3919 *      Inherited from caller.
3920 */
3921static int mv_init_host(struct ata_host *host)
3922{
3923        int rc = 0, n_hc, port, hc;
3924        struct mv_host_priv *hpriv = host->private_data;
3925        void __iomem *mmio = hpriv->base;
3926
3927        rc = mv_chip_id(host, hpriv->board_idx);
3928        if (rc)
3929                goto done;
3930
3931        if (IS_SOC(hpriv)) {
3932                hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3933                hpriv->main_irq_mask_addr  = mmio + SOC_HC_MAIN_IRQ_MASK;
3934        } else {
3935                hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3936                hpriv->main_irq_mask_addr  = mmio + PCI_HC_MAIN_IRQ_MASK;
3937        }
3938
3939        /* initialize shadow irq mask with register's value */
3940        hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3941
3942        /* global interrupt mask: 0 == mask everything */
3943        mv_set_main_irq_mask(host, ~0, 0);
3944
3945        n_hc = mv_get_hc_count(host->ports[0]->flags);
3946
3947        for (port = 0; port < host->n_ports; port++)
3948                if (hpriv->ops->read_preamp)
3949                        hpriv->ops->read_preamp(hpriv, port, mmio);
3950
3951        rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3952        if (rc)
3953                goto done;
3954
3955        hpriv->ops->reset_flash(hpriv, mmio);
3956        hpriv->ops->reset_bus(host, mmio);
3957        hpriv->ops->enable_leds(hpriv, mmio);
3958
3959        for (port = 0; port < host->n_ports; port++) {
3960                struct ata_port *ap = host->ports[port];
3961                void __iomem *port_mmio = mv_port_base(mmio, port);
3962
3963                mv_port_init(&ap->ioaddr, port_mmio);
3964        }
3965
3966        for (hc = 0; hc < n_hc; hc++) {
3967                void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3968
3969                VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3970                        "(before clear)=0x%08x\n", hc,
3971                        readl(hc_mmio + HC_CFG),
3972                        readl(hc_mmio + HC_IRQ_CAUSE));
3973
3974                /* Clear any currently outstanding hc interrupt conditions */
3975                writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3976        }
3977
3978        if (!IS_SOC(hpriv)) {
3979                /* Clear any currently outstanding host interrupt conditions */
3980                writelfl(0, mmio + hpriv->irq_cause_offset);
3981
3982                /* and unmask interrupt generation for host regs */
3983                writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3984        }
3985
3986        /*
3987         * enable only global host interrupts for now.
3988         * The per-port interrupts get done later as ports are set up.
3989         */
3990        mv_set_main_irq_mask(host, 0, PCI_ERR);
3991        mv_set_irq_coalescing(host, irq_coalescing_io_count,
3992                                    irq_coalescing_usecs);
3993done:
3994        return rc;
3995}
3996
3997static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3998{
3999        hpriv->crqb_pool   = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
4000                                                             MV_CRQB_Q_SZ, 0);
4001        if (!hpriv->crqb_pool)
4002                return -ENOMEM;
4003
4004        hpriv->crpb_pool   = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
4005                                                             MV_CRPB_Q_SZ, 0);
4006        if (!hpriv->crpb_pool)
4007                return -ENOMEM;
4008
4009        hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
4010                                                             MV_SG_TBL_SZ, 0);
4011        if (!hpriv->sg_tbl_pool)
4012                return -ENOMEM;
4013
4014        return 0;
4015}
4016
4017static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
4018                                 const struct mbus_dram_target_info *dram)
4019{
4020        int i;
4021
4022        for (i = 0; i < 4; i++) {
4023                writel(0, hpriv->base + WINDOW_CTRL(i));
4024                writel(0, hpriv->base + WINDOW_BASE(i));
4025        }
4026
4027        for (i = 0; i < dram->num_cs; i++) {
4028                const struct mbus_dram_window *cs = dram->cs + i;
4029
4030                writel(((cs->size - 1) & 0xffff0000) |
4031                        (cs->mbus_attr << 8) |
4032                        (dram->mbus_dram_target_id << 4) | 1,
4033                        hpriv->base + WINDOW_CTRL(i));
4034                writel(cs->base, hpriv->base + WINDOW_BASE(i));
4035        }
4036}
4037
4038/**
4039 *      mv_platform_probe - handle a positive probe of an soc Marvell
4040 *      host
4041 *      @pdev: platform device found
4042 *
4043 *      LOCKING:
4044 *      Inherited from caller.
4045 */
4046static int mv_platform_probe(struct platform_device *pdev)
4047{
4048        const struct mv_sata_platform_data *mv_platform_data;
4049        const struct mbus_dram_target_info *dram;
4050        const struct ata_port_info *ppi[] =
4051            { &mv_port_info[chip_soc], NULL };
4052        struct ata_host *host;
4053        struct mv_host_priv *hpriv;
4054        struct resource *res;
4055        int n_ports = 0, irq = 0;
4056        int rc;
4057        int port;
4058
4059        ata_print_version_once(&pdev->dev, DRV_VERSION);
4060
4061        /*
4062         * Simple resource validation ..
4063         */
4064        if (unlikely(pdev->num_resources != 2)) {
4065                dev_err(&pdev->dev, "invalid number of resources\n");
4066                return -EINVAL;
4067        }
4068
4069        /*
4070         * Get the register base first
4071         */
4072        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4073        if (res == NULL)
4074                return -EINVAL;
4075
4076        /* allocate host */
4077        if (pdev->dev.of_node) {
4078                rc = of_property_read_u32(pdev->dev.of_node, "nr-ports",
4079                                           &n_ports);
4080                if (rc) {
4081                        dev_err(&pdev->dev,
4082                                "error parsing nr-ports property: %d\n", rc);
4083                        return rc;
4084                }
4085
4086                if (n_ports <= 0) {
4087                        dev_err(&pdev->dev, "nr-ports must be positive: %d\n",
4088                                n_ports);
4089                        return -EINVAL;
4090                }
4091
4092                irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
4093        } else {
4094                mv_platform_data = dev_get_platdata(&pdev->dev);
4095                n_ports = mv_platform_data->n_ports;
4096                irq = platform_get_irq(pdev, 0);
4097        }
4098
4099        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4100        hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4101
4102        if (!host || !hpriv)
4103                return -ENOMEM;
4104        hpriv->port_clks = devm_kcalloc(&pdev->dev,
4105                                        n_ports, sizeof(struct clk *),
4106                                        GFP_KERNEL);
4107        if (!hpriv->port_clks)
4108                return -ENOMEM;
4109        hpriv->port_phys = devm_kcalloc(&pdev->dev,
4110                                        n_ports, sizeof(struct phy *),
4111                                        GFP_KERNEL);
4112        if (!hpriv->port_phys)
4113                return -ENOMEM;
4114        host->private_data = hpriv;
4115        hpriv->board_idx = chip_soc;
4116
4117        host->iomap = NULL;
4118        hpriv->base = devm_ioremap(&pdev->dev, res->start,
4119                                   resource_size(res));
4120        if (!hpriv->base)
4121                return -ENOMEM;
4122
4123        hpriv->base -= SATAHC0_REG_BASE;
4124
4125        hpriv->clk = clk_get(&pdev->dev, NULL);
4126        if (IS_ERR(hpriv->clk))
4127                dev_notice(&pdev->dev, "cannot get optional clkdev\n");
4128        else
4129                clk_prepare_enable(hpriv->clk);
4130
4131        for (port = 0; port < n_ports; port++) {
4132                char port_number[16];
4133                sprintf(port_number, "%d", port);
4134                hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4135                if (!IS_ERR(hpriv->port_clks[port]))
4136                        clk_prepare_enable(hpriv->port_clks[port]);
4137
4138                sprintf(port_number, "port%d", port);
4139                hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,
4140                                                               port_number);
4141                if (IS_ERR(hpriv->port_phys[port])) {
4142                        rc = PTR_ERR(hpriv->port_phys[port]);
4143                        hpriv->port_phys[port] = NULL;
4144                        if (rc != -EPROBE_DEFER)
4145                                dev_warn(&pdev->dev, "error getting phy %d", rc);
4146
4147                        /* Cleanup only the initialized ports */
4148                        hpriv->n_ports = port;
4149                        goto err;
4150                } else
4151                        phy_power_on(hpriv->port_phys[port]);
4152        }
4153
4154        /* All the ports have been initialized */
4155        hpriv->n_ports = n_ports;
4156
4157        /*
4158         * (Re-)program MBUS remapping windows if we are asked to.
4159         */
4160        dram = mv_mbus_dram_info();
4161        if (dram)
4162                mv_conf_mbus_windows(hpriv, dram);
4163
4164        rc = mv_create_dma_pools(hpriv, &pdev->dev);
4165        if (rc)
4166                goto err;
4167
4168        /*
4169         * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
4170         * updated in the LP_PHY_CTL register.
4171         */
4172        if (pdev->dev.of_node &&
4173                of_device_is_compatible(pdev->dev.of_node,
4174                                        "marvell,armada-370-sata"))
4175                hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
4176
4177        /* initialize adapter */
4178        rc = mv_init_host(host);
4179        if (rc)
4180                goto err;
4181
4182        dev_info(&pdev->dev, "slots %u ports %d\n",
4183                 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
4184
4185        rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
4186        if (!rc)
4187                return 0;
4188
4189err:
4190        if (!IS_ERR(hpriv->clk)) {
4191                clk_disable_unprepare(hpriv->clk);
4192                clk_put(hpriv->clk);
4193        }
4194        for (port = 0; port < hpriv->n_ports; port++) {
4195                if (!IS_ERR(hpriv->port_clks[port])) {
4196                        clk_disable_unprepare(hpriv->port_clks[port]);
4197                        clk_put(hpriv->port_clks[port]);
4198                }
4199                phy_power_off(hpriv->port_phys[port]);
4200        }
4201
4202        return rc;
4203}
4204
4205/*
4206 *
4207 *      mv_platform_remove    -       unplug a platform interface
4208 *      @pdev: platform device
4209 *
4210 *      A platform bus SATA device has been unplugged. Perform the needed
4211 *      cleanup. Also called on module unload for any active devices.
4212 */
4213static int mv_platform_remove(struct platform_device *pdev)
4214{
4215        struct ata_host *host = platform_get_drvdata(pdev);
4216        struct mv_host_priv *hpriv = host->private_data;
4217        int port;
4218        ata_host_detach(host);
4219
4220        if (!IS_ERR(hpriv->clk)) {
4221                clk_disable_unprepare(hpriv->clk);
4222                clk_put(hpriv->clk);
4223        }
4224        for (port = 0; port < host->n_ports; port++) {
4225                if (!IS_ERR(hpriv->port_clks[port])) {
4226                        clk_disable_unprepare(hpriv->port_clks[port]);
4227                        clk_put(hpriv->port_clks[port]);
4228                }
4229                phy_power_off(hpriv->port_phys[port]);
4230        }
4231        return 0;
4232}
4233
4234#ifdef CONFIG_PM_SLEEP
4235static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4236{
4237        struct ata_host *host = platform_get_drvdata(pdev);
4238        if (host)
4239                return ata_host_suspend(host, state);
4240        else
4241                return 0;
4242}
4243
4244static int mv_platform_resume(struct platform_device *pdev)
4245{
4246        struct ata_host *host = platform_get_drvdata(pdev);
4247        const struct mbus_dram_target_info *dram;
4248        int ret;
4249
4250        if (host) {
4251                struct mv_host_priv *hpriv = host->private_data;
4252
4253                /*
4254                 * (Re-)program MBUS remapping windows if we are asked to.
4255                 */
4256                dram = mv_mbus_dram_info();
4257                if (dram)
4258                        mv_conf_mbus_windows(hpriv, dram);
4259
4260                /* initialize adapter */
4261                ret = mv_init_host(host);
4262                if (ret) {
4263                        printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4264                        return ret;
4265                }
4266                ata_host_resume(host);
4267        }
4268
4269        return 0;
4270}
4271#else
4272#define mv_platform_suspend NULL
4273#define mv_platform_resume NULL
4274#endif
4275
4276#ifdef CONFIG_OF
4277static const struct of_device_id mv_sata_dt_ids[] = {
4278        { .compatible = "marvell,armada-370-sata", },
4279        { .compatible = "marvell,orion-sata", },
4280        {},
4281};
4282MODULE_DEVICE_TABLE(of, mv_sata_dt_ids);
4283#endif
4284
4285static struct platform_driver mv_platform_driver = {
4286        .probe          = mv_platform_probe,
4287        .remove         = mv_platform_remove,
4288        .suspend        = mv_platform_suspend,
4289        .resume         = mv_platform_resume,
4290        .driver         = {
4291                .name = DRV_NAME,
4292                .of_match_table = of_match_ptr(mv_sata_dt_ids),
4293        },
4294};
4295
4296
4297#ifdef CONFIG_PCI
4298static int mv_pci_init_one(struct pci_dev *pdev,
4299                           const struct pci_device_id *ent);
4300#ifdef CONFIG_PM_SLEEP
4301static int mv_pci_device_resume(struct pci_dev *pdev);
4302#endif
4303
4304
4305static struct pci_driver mv_pci_driver = {
4306        .name                   = DRV_NAME,
4307        .id_table               = mv_pci_tbl,
4308        .probe                  = mv_pci_init_one,
4309        .remove                 = ata_pci_remove_one,
4310#ifdef CONFIG_PM_SLEEP
4311        .suspend                = ata_pci_device_suspend,
4312        .resume                 = mv_pci_device_resume,
4313#endif
4314
4315};
4316
4317/**
4318 *      mv_print_info - Dump key info to kernel log for perusal.
4319 *      @host: ATA host to print info about
4320 *
4321 *      FIXME: complete this.
4322 *
4323 *      LOCKING:
4324 *      Inherited from caller.
4325 */
4326static void mv_print_info(struct ata_host *host)
4327{
4328        struct pci_dev *pdev = to_pci_dev(host->dev);
4329        struct mv_host_priv *hpriv = host->private_data;
4330        u8 scc;
4331        const char *scc_s, *gen;
4332
4333        /* Use this to determine the HW stepping of the chip so we know
4334         * what errata to workaround
4335         */
4336        pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4337        if (scc == 0)
4338                scc_s = "SCSI";
4339        else if (scc == 0x01)
4340                scc_s = "RAID";
4341        else
4342                scc_s = "?";
4343
4344        if (IS_GEN_I(hpriv))
4345                gen = "I";
4346        else if (IS_GEN_II(hpriv))
4347                gen = "II";
4348        else if (IS_GEN_IIE(hpriv))
4349                gen = "IIE";
4350        else
4351                gen = "?";
4352
4353        dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4354                 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4355                 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4356}
4357
4358/**
4359 *      mv_pci_init_one - handle a positive probe of a PCI Marvell host
4360 *      @pdev: PCI device found
4361 *      @ent: PCI device ID entry for the matched host
4362 *
4363 *      LOCKING:
4364 *      Inherited from caller.
4365 */
4366static int mv_pci_init_one(struct pci_dev *pdev,
4367                           const struct pci_device_id *ent)
4368{
4369        unsigned int board_idx = (unsigned int)ent->driver_data;
4370        const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4371        struct ata_host *host;
4372        struct mv_host_priv *hpriv;
4373        int n_ports, port, rc;
4374
4375        ata_print_version_once(&pdev->dev, DRV_VERSION);
4376
4377        /* allocate host */
4378        n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4379
4380        host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4381        hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4382        if (!host || !hpriv)
4383                return -ENOMEM;
4384        host->private_data = hpriv;
4385        hpriv->n_ports = n_ports;
4386        hpriv->board_idx = board_idx;
4387
4388        /* acquire resources */
4389        rc = pcim_enable_device(pdev);
4390        if (rc)
4391                return rc;
4392
4393        rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4394        if (rc == -EBUSY)
4395                pcim_pin_device(pdev);
4396        if (rc)
4397                return rc;
4398        host->iomap = pcim_iomap_table(pdev);
4399        hpriv->base = host->iomap[MV_PRIMARY_BAR];
4400
4401        rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4402        if (rc) {
4403                dev_err(&pdev->dev, "DMA enable failed\n");
4404                return rc;
4405        }
4406
4407        rc = mv_create_dma_pools(hpriv, &pdev->dev);
4408        if (rc)
4409                return rc;
4410
4411        for (port = 0; port < host->n_ports; port++) {
4412                struct ata_port *ap = host->ports[port];
4413                void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4414                unsigned int offset = port_mmio - hpriv->base;
4415
4416                ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4417                ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4418        }
4419
4420        /* initialize adapter */
4421        rc = mv_init_host(host);
4422        if (rc)
4423                return rc;
4424
4425        /* Enable message-switched interrupts, if requested */
4426        if (msi && pci_enable_msi(pdev) == 0)
4427                hpriv->hp_flags |= MV_HP_FLAG_MSI;
4428
4429        mv_dump_pci_cfg(pdev, 0x68);
4430        mv_print_info(host);
4431
4432        pci_set_master(pdev);
4433        pci_try_set_mwi(pdev);
4434        return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4435                                 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4436}
4437
4438#ifdef CONFIG_PM_SLEEP
4439static int mv_pci_device_resume(struct pci_dev *pdev)
4440{
4441        struct ata_host *host = pci_get_drvdata(pdev);
4442        int rc;
4443
4444        rc = ata_pci_device_do_resume(pdev);
4445        if (rc)
4446                return rc;
4447
4448        /* initialize adapter */
4449        rc = mv_init_host(host);
4450        if (rc)
4451                return rc;
4452
4453        ata_host_resume(host);
4454
4455        return 0;
4456}
4457#endif
4458#endif
4459
4460static int __init mv_init(void)
4461{
4462        int rc = -ENODEV;
4463#ifdef CONFIG_PCI
4464        rc = pci_register_driver(&mv_pci_driver);
4465        if (rc < 0)
4466                return rc;
4467#endif
4468        rc = platform_driver_register(&mv_platform_driver);
4469
4470#ifdef CONFIG_PCI
4471        if (rc < 0)
4472                pci_unregister_driver(&mv_pci_driver);
4473#endif
4474        return rc;
4475}
4476
4477static void __exit mv_exit(void)
4478{
4479#ifdef CONFIG_PCI
4480        pci_unregister_driver(&mv_pci_driver);
4481#endif
4482        platform_driver_unregister(&mv_platform_driver);
4483}
4484
4485MODULE_AUTHOR("Brett Russ");
4486MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4487MODULE_LICENSE("GPL v2");
4488MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4489MODULE_VERSION(DRV_VERSION);
4490MODULE_ALIAS("platform:" DRV_NAME);
4491
4492module_init(mv_init);
4493module_exit(mv_exit);
4494