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11#ifndef __MTIP32XX_H__
12#define __MTIP32XX_H__
13
14#include <linux/spinlock.h>
15#include <linux/rwsem.h>
16#include <linux/ata.h>
17#include <linux/interrupt.h>
18#include <linux/genhd.h>
19
20
21#define PCI_SUBSYSTEM_DEVICEID 0x2E
22
23
24#define PCIE_CONFIG_EXT_DEVICE_CONTROL_OFFSET 0x48
25
26
27#define MTIP_SEC_ERASE_MODE 0x2
28
29
30#define MTIP_MAX_RETRIES 2
31
32
33#define MTIP_NCQ_CMD_TIMEOUT_MS 15000
34#define MTIP_IOCTL_CMD_TIMEOUT_MS 5000
35#define MTIP_INT_CMD_TIMEOUT_MS 5000
36#define MTIP_QUIESCE_IO_TIMEOUT_MS (MTIP_NCQ_CMD_TIMEOUT_MS * \
37 (MTIP_MAX_RETRIES + 1))
38
39
40#define MTIP_TIMEOUT_CHECK_PERIOD 500
41
42
43#define MTIP_FTL_REBUILD_OFFSET 142
44#define MTIP_FTL_REBUILD_MAGIC 0xED51
45#define MTIP_FTL_REBUILD_TIMEOUT_MS 2400000
46
47
48#define MTIP_MAX_UNALIGNED_SLOTS 2
49
50
51#define MTIP_TAG_BIT(tag) (tag & 0x1F)
52
53
54
55
56
57
58#define MTIP_TAG_INDEX(tag) (tag >> 5)
59
60
61
62
63
64#define MTIP_MAX_SG 504
65
66
67
68
69
70#define MTIP_MAX_SLOT_GROUPS 8
71
72
73#define MTIP_TAG_INTERNAL 0
74
75
76#define PCI_VENDOR_ID_MICRON 0x1344
77#define P320H_DEVICE_ID 0x5150
78#define P320M_DEVICE_ID 0x5151
79#define P320S_DEVICE_ID 0x5152
80#define P325M_DEVICE_ID 0x5153
81#define P420H_DEVICE_ID 0x5160
82#define P420M_DEVICE_ID 0x5161
83#define P425M_DEVICE_ID 0x5163
84
85
86#define MTIP_DRV_NAME "mtip32xx"
87#define MTIP_DRV_VERSION "1.3.1"
88
89
90#define MTIP_MAX_MINORS 16
91
92
93#define MTIP_MAX_COMMAND_SLOTS (MTIP_MAX_SLOT_GROUPS * 32)
94
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101
102
103#define U32_PER_LONG (sizeof(long) / sizeof(u32))
104#define SLOTBITS_IN_LONGS ((MTIP_MAX_SLOT_GROUPS + \
105 (U32_PER_LONG-1))/U32_PER_LONG)
106
107
108#define MTIP_ABAR 5
109
110#ifdef DEBUG
111 #define dbg_printk(format, arg...) \
112 printk(pr_fmt(format), ##arg);
113#else
114 #define dbg_printk(format, arg...)
115#endif
116
117#define MTIP_DFS_MAX_BUF_SIZE 1024
118
119enum {
120
121 MTIP_PF_IC_ACTIVE_BIT = 0,
122 MTIP_PF_EH_ACTIVE_BIT = 1,
123 MTIP_PF_SE_ACTIVE_BIT = 2,
124 MTIP_PF_DM_ACTIVE_BIT = 3,
125 MTIP_PF_TO_ACTIVE_BIT = 9,
126 MTIP_PF_PAUSE_IO = ((1 << MTIP_PF_IC_ACTIVE_BIT) |
127 (1 << MTIP_PF_EH_ACTIVE_BIT) |
128 (1 << MTIP_PF_SE_ACTIVE_BIT) |
129 (1 << MTIP_PF_DM_ACTIVE_BIT) |
130 (1 << MTIP_PF_TO_ACTIVE_BIT)),
131 MTIP_PF_HOST_CAP_64 = 10,
132
133 MTIP_PF_SVC_THD_ACTIVE_BIT = 4,
134 MTIP_PF_ISSUE_CMDS_BIT = 5,
135 MTIP_PF_REBUILD_BIT = 6,
136 MTIP_PF_SVC_THD_STOP_BIT = 8,
137
138 MTIP_PF_SVC_THD_WORK = ((1 << MTIP_PF_EH_ACTIVE_BIT) |
139 (1 << MTIP_PF_ISSUE_CMDS_BIT) |
140 (1 << MTIP_PF_REBUILD_BIT) |
141 (1 << MTIP_PF_SVC_THD_STOP_BIT) |
142 (1 << MTIP_PF_TO_ACTIVE_BIT)),
143
144
145 MTIP_DDF_SEC_LOCK_BIT = 0,
146 MTIP_DDF_REMOVE_PENDING_BIT = 1,
147 MTIP_DDF_OVER_TEMP_BIT = 2,
148 MTIP_DDF_WRITE_PROTECT_BIT = 3,
149 MTIP_DDF_CLEANUP_BIT = 5,
150 MTIP_DDF_RESUME_BIT = 6,
151 MTIP_DDF_INIT_DONE_BIT = 7,
152 MTIP_DDF_REBUILD_FAILED_BIT = 8,
153 MTIP_DDF_REMOVAL_BIT = 9,
154
155 MTIP_DDF_STOP_IO = ((1 << MTIP_DDF_REMOVE_PENDING_BIT) |
156 (1 << MTIP_DDF_SEC_LOCK_BIT) |
157 (1 << MTIP_DDF_OVER_TEMP_BIT) |
158 (1 << MTIP_DDF_WRITE_PROTECT_BIT) |
159 (1 << MTIP_DDF_REBUILD_FAILED_BIT)),
160
161};
162
163struct smart_attr {
164 u8 attr_id;
165 __le16 flags;
166 u8 cur;
167 u8 worst;
168 __le32 data;
169 u8 res[3];
170} __packed;
171
172struct mtip_work {
173 struct work_struct work;
174 void *port;
175 int cpu_binding;
176 u32 completed;
177} ____cacheline_aligned_in_smp;
178
179#define DEFINE_HANDLER(group) \
180 void mtip_workq_sdbf##group(struct work_struct *work) \
181 { \
182 struct mtip_work *w = (struct mtip_work *) work; \
183 mtip_workq_sdbfx(w->port, group, w->completed); \
184 }
185
186
187struct host_to_dev_fis {
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197
198
199 unsigned char type;
200 unsigned char opts;
201 unsigned char command;
202 unsigned char features;
203
204 union {
205 unsigned char lba_low;
206 unsigned char sector;
207 };
208 union {
209 unsigned char lba_mid;
210 unsigned char cyl_low;
211 };
212 union {
213 unsigned char lba_hi;
214 unsigned char cyl_hi;
215 };
216 union {
217 unsigned char device;
218 unsigned char head;
219 };
220
221 union {
222 unsigned char lba_low_ex;
223 unsigned char sector_ex;
224 };
225 union {
226 unsigned char lba_mid_ex;
227 unsigned char cyl_low_ex;
228 };
229 union {
230 unsigned char lba_hi_ex;
231 unsigned char cyl_hi_ex;
232 };
233 unsigned char features_ex;
234
235 unsigned char sect_count;
236 unsigned char sect_cnt_ex;
237 unsigned char res2;
238 unsigned char control;
239
240 unsigned int res3;
241};
242
243
244struct mtip_cmd_hdr {
245
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254 __le32 opts;
255
256 union {
257 __le32 byte_count;
258 __le32 status;
259 };
260
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263
264 __le32 ctba;
265
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267
268
269 __le32 ctbau;
270
271 u32 res[4];
272};
273
274
275struct mtip_cmd_sg {
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280
281 __le32 dba;
282
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285
286 __le32 dba_upper;
287
288 __le32 reserved;
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294
295 __le32 info;
296};
297struct mtip_port;
298
299struct mtip_int_cmd;
300
301
302struct mtip_cmd {
303 void *command;
304
305 dma_addr_t command_dma;
306
307 int scatter_ents;
308
309 int unaligned;
310
311 union {
312 struct scatterlist sg[MTIP_MAX_SG];
313 struct mtip_int_cmd *icmd;
314 };
315
316 int retries;
317
318 int direction;
319 blk_status_t status;
320};
321
322
323struct mtip_port {
324
325 struct driver_data *dd;
326
327
328
329
330 unsigned long identify_valid;
331
332 void __iomem *mmio;
333
334 void __iomem *s_active[MTIP_MAX_SLOT_GROUPS];
335
336 void __iomem *completed[MTIP_MAX_SLOT_GROUPS];
337
338 void __iomem *cmd_issue[MTIP_MAX_SLOT_GROUPS];
339
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343 void *command_list;
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347
348 dma_addr_t command_list_dma;
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353 void *rxfis;
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358 dma_addr_t rxfis_dma;
359
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362 void *block1;
363
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365
366 dma_addr_t block1_dma;
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371 u16 *identify;
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376 dma_addr_t identify_dma;
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381 u16 *sector_buffer;
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385
386 dma_addr_t sector_buffer_dma;
387
388 u16 *log_buf;
389 dma_addr_t log_buf_dma;
390
391 u8 *smart_buf;
392 dma_addr_t smart_buf_dma;
393
394
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396
397
398 unsigned long cmds_to_issue[SLOTBITS_IN_LONGS];
399
400 wait_queue_head_t svc_wait;
401
402
403
404
405 unsigned long flags;
406
407
408
409 unsigned long ic_pause_timer;
410
411
412 atomic_t cmd_slot_unal;
413
414
415 spinlock_t cmd_issue_lock[MTIP_MAX_SLOT_GROUPS];
416};
417
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421
422
423struct driver_data {
424 void __iomem *mmio;
425
426 int major;
427
428 int instance;
429
430 struct gendisk *disk;
431
432 struct pci_dev *pdev;
433
434 struct request_queue *queue;
435
436 struct blk_mq_tag_set tags;
437
438 struct mtip_port *port;
439
440 unsigned product_type;
441
442 unsigned slot_groups;
443
444 unsigned long index;
445
446 unsigned long dd_flag;
447
448 struct task_struct *mtip_svc_handler;
449
450 struct dentry *dfs_node;
451
452 bool sr;
453
454 int numa_node;
455
456 char workq_name[32];
457
458 struct workqueue_struct *isr_workq;
459
460 atomic_t irq_workers_active;
461
462 struct mtip_work work[MTIP_MAX_SLOT_GROUPS];
463
464 int isr_binding;
465
466 struct block_device *bdev;
467
468 struct list_head online_list;
469
470 struct list_head remove_list;
471
472 int unal_qdepth;
473};
474
475#endif
476