LXR linux/drivers/clk/uniphier/clk-uniphier-sys.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2016 Socionext Inc.
   4 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5 */
   6
   7#include <linux/stddef.h>
   8
   9#include "clk-uniphier.h"
  10
  11#define UNIPHIER_LD4_SYS_CLK_SD                                 \
  12        UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8),               \
  13        UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
  14
  15#define UNIPHIER_PRO5_SYS_CLK_SD                                        \
  16        UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12),              \
  17        UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
  18
  19#define UNIPHIER_LD20_SYS_CLK_SD                                        \
  20        UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10),              \
  21        UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
  22
  23#define UNIPHIER_LD4_SYS_CLK_NAND(idx)                                  \
  24        UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32),             \
  25        UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
  26
  27#define UNIPHIER_PRO5_SYS_CLK_NAND(idx)                                 \
  28        UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48),             \
  29        UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
  30
  31#define UNIPHIER_LD11_SYS_CLK_NAND(idx)                                 \
  32        UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40),             \
  33        UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
  34
  35#define UNIPHIER_SYS_CLK_NAND_4X(idx)                                   \
  36        UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
  37
  38#define UNIPHIER_LD11_SYS_CLK_EMMC(idx)                                 \
  39        UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
  40
  41#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx)                                \
  42        UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
  43
  44#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx)                               \
  45        UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
  46
  47#define UNIPHIER_LD11_SYS_CLK_HSC(idx)                                  \
  48        UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
  49
  50#define UNIPHIER_PRO4_SYS_CLK_GIO(idx)                                  \
  51        UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
  52
  53#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch)                             \
  54        UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
  55
  56#define UNIPHIER_PRO4_SYS_CLK_AIO(idx)                                  \
  57        UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8),            \
  58        UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
  59
  60#define UNIPHIER_PRO5_SYS_CLK_AIO(idx)                                  \
  61        UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12),           \
  62        UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
  63
  64#define UNIPHIER_LD11_SYS_CLK_AIO(idx)                                  \
  65        UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10),           \
  66        UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
  67
  68#define UNIPHIER_LD11_SYS_CLK_EVEA(idx)                                 \
  69        UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),          \
  70        UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
  71
  72#define UNIPHIER_LD11_SYS_CLK_EXIV(idx)                                 \
  73        UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10),          \
  74        UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
  75
  76#define UNIPHIER_PRO4_SYS_CLK_ETHER(idx)                                \
  77        UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
  78
  79#define UNIPHIER_LD11_SYS_CLK_ETHER(idx)                                \
  80        UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
  81
  82const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
  83        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),          /* 1597.44 MHz */
  84        UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),      /* 288 MHz */
  85        UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1),         /* 589.824 MHz */
  86        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
  87        UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
  88        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
  89        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
  90        UNIPHIER_LD4_SYS_CLK_NAND(2),
  91        UNIPHIER_SYS_CLK_NAND_4X(3),
  92        UNIPHIER_LD4_SYS_CLK_SD,
  93        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
  94        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
  95        { /* sentinel */ }
  96};
  97
  98const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
  99        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),          /* 1600 MHz */
 100        UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
 101        UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125),     /* 589.824 MHz */
 102        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
 103        UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1),          /* 250 MHz */
 104        UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
 105        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
 106        UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
 107        UNIPHIER_LD4_SYS_CLK_NAND(2),
 108        UNIPHIER_SYS_CLK_NAND_4X(3),
 109        UNIPHIER_LD4_SYS_CLK_SD,
 110        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
 111        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
 112        UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
 113        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* HSC, MIO, RLE */
 114        UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
 115        UNIPHIER_PRO4_SYS_CLK_GIO(12),                  /* Ether, SATA, USB3 */
 116        UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 117        UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 118        UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
 119        UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
 120        UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),
 121        UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
 122        UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
 123        UNIPHIER_PRO4_SYS_CLK_AIO(40),
 124        { /* sentinel */ }
 125};
 126
 127const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
 128        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),          /* 1600 MHz */
 129        UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),        /* 288 MHz */
 130        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
 131        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
 132        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
 133        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
 134        UNIPHIER_LD4_SYS_CLK_NAND(2),
 135        UNIPHIER_SYS_CLK_NAND_4X(3),
 136        UNIPHIER_LD4_SYS_CLK_SD,
 137        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
 138        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
 139        { /* sentinel */ }
 140};
 141
 142const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
 143        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1),         /* 2400 MHz */
 144        UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1),       /* 2560 MHz */
 145        UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),  /* 2949.12 MHz */
 146        UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
 147        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
 148        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
 149        UNIPHIER_PRO5_SYS_CLK_NAND(2),
 150        UNIPHIER_SYS_CLK_NAND_4X(3),
 151        UNIPHIER_PRO5_SYS_CLK_SD,
 152        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC */
 153        UNIPHIER_PRO4_SYS_CLK_GIO(12),                          /* PCIe, USB3 */
 154        UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 155        UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 156        UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
 157        UNIPHIER_PRO5_SYS_CLK_AIO(40),
 158        { /* sentinel */ }
 159};
 160
 161const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 162        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1),          /* 2400 MHz */
 163        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
 164        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
 165        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
 166        UNIPHIER_PRO5_SYS_CLK_NAND(2),
 167        UNIPHIER_SYS_CLK_NAND_4X(3),
 168        UNIPHIER_PRO5_SYS_CLK_SD,
 169        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
 170        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC, RLE */
 171        /* GIO is always clock-enabled: no function for 0x2104 bit6 */
 172        UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
 173        UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
 174        /* The document mentions 0x2104 bit 18, but not functional */
 175        UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
 176        UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
 177        UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),
 178        UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
 179        UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),
 180        UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
 181        UNIPHIER_PRO5_SYS_CLK_AIO(40),
 182        { /* sentinel */ }
 183};
 184
 185const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
 186        UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5),         /* 1960 MHz */
 187        UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),          /* 1600 MHz */
 188        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 189        UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1),         /* 2000 MHz */
 190        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 191        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 192        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
 193        UNIPHIER_LD11_SYS_CLK_NAND(2),
 194        UNIPHIER_SYS_CLK_NAND_4X(3),
 195        UNIPHIER_LD11_SYS_CLK_EMMC(4),
 196        /* Index 5 reserved for eMMC PHY */
 197        UNIPHIER_LD11_SYS_CLK_ETHER(6),
 198        UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
 199        UNIPHIER_LD11_SYS_CLK_HSC(9),
 200        UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
 201        UNIPHIER_LD11_SYS_CLK_AIO(40),
 202        UNIPHIER_LD11_SYS_CLK_EVEA(41),
 203        UNIPHIER_LD11_SYS_CLK_EXIV(42),
 204        /* CPU gears */
 205        UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 206        UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
 207        UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
 208        /* Note: both gear1 and gear4 are spll/4.  This is not a bug. */
 209        UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 210                             "cpll/2", "spll/4", "cpll/3", "spll/3",
 211                             "spll/4", "spll/8", "cpll/4", "cpll/8"),
 212        UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 213                             "mpll/2", "spll/4", "mpll/3", "spll/3",
 214                             "spll/4", "spll/8", "mpll/4", "mpll/8"),
 215        { /* sentinel */ }
 216};
 217
 218const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 219        UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1),          /* ARM: 2200 MHz */
 220        UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1),         /* Mali: 1300 MHz */
 221        UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),          /* Codec: 1600 MHz */
 222        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 223        UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2200 MHz */
 224        UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5),        /* 2520 MHz */
 225        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 226        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 227        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
 228        UNIPHIER_LD11_SYS_CLK_NAND(2),
 229        UNIPHIER_SYS_CLK_NAND_4X(3),
 230        UNIPHIER_LD11_SYS_CLK_EMMC(4),
 231        /* Index 5 reserved for eMMC PHY */
 232        UNIPHIER_LD20_SYS_CLK_SD,
 233        UNIPHIER_LD11_SYS_CLK_ETHER(6),
 234        UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC */
 235        UNIPHIER_LD11_SYS_CLK_HSC(9),
 236        /* GIO is always clock-enabled: no function for 0x210c bit5 */
 237        /*
 238         * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
 239         * We do not use bit 15 here.
 240         */
 241        UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
 242        UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
 243        UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
 244        UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),
 245        UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),
 246        UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
 247        UNIPHIER_LD11_SYS_CLK_AIO(40),
 248        UNIPHIER_LD11_SYS_CLK_EVEA(41),
 249        UNIPHIER_LD11_SYS_CLK_EXIV(42),
 250        /* CPU gears */
 251        UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 252        UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
 253        UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
 254        UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
 255                             "cpll/2", "spll/2", "cpll/3", "spll/3",
 256                             "spll/4", "spll/8", "cpll/4", "cpll/8"),
 257        UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 258                             "cpll/2", "spll/2", "cpll/3", "spll/3",
 259                             "spll/4", "spll/8", "cpll/4", "cpll/8"),
 260        UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 261                             "s2pll/2", "spll/2", "s2pll/3", "spll/3",
 262                             "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
 263        { /* sentinel */ }
 264};
 265
 266const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 267        UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1),         /* ARM: 2600 MHz */
 268        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),          /* 2000 MHz */
 269        UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2400 MHz */
 270        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
 271        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
 272        UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
 273        UNIPHIER_LD20_SYS_CLK_SD,
 274        UNIPHIER_LD11_SYS_CLK_NAND(2),
 275        UNIPHIER_SYS_CLK_NAND_4X(3),
 276        UNIPHIER_LD11_SYS_CLK_EMMC(4),
 277        UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
 278        UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
 279        UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4),        /* =GIO0 */
 280        UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5),      /* =GIO1 */
 281        UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6),      /* =GIO1-1 */
 282        UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
 283        UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
 284        UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
 285        UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
 286        UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
 287        UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
 288        UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
 289        UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
 290        UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
 291        /* CPU gears */
 292        UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 293        UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
 294        UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
 295        UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
 296                             "cpll/2", "spll/2", "cpll/3", "spll/3",
 297                             "spll/4", "spll/8", "cpll/4", "cpll/8"),
 298        UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
 299                             "s2pll/2", "spll/2", "s2pll/3", "spll/3",
 300                             "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
 301        { /* sentinel */ }
 302};
 303