LXR linux/drivers/gpu/drm/amd/display/dc/clk_mgr/clk

   1/*
   2 * Copyright 2012-16 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include <linux/slab.h>
  27
  28#include "dal_asic_id.h"
  29#include "dc_types.h"
  30#include "dccg.h"
  31#include "clk_mgr_internal.h"
  32
  33#include "dce100/dce_clk_mgr.h"
  34#include "dce110/dce110_clk_mgr.h"
  35#include "dce112/dce112_clk_mgr.h"
  36#include "dce120/dce120_clk_mgr.h"
  37#include "dcn10/rv1_clk_mgr.h"
  38#include "dcn10/rv2_clk_mgr.h"
  39#include "dcn20/dcn20_clk_mgr.h"
  40#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
  41#include "dcn21/rn_clk_mgr.h"
  42#endif
  43
  44
  45int clk_mgr_helper_get_active_display_cnt(
  46                struct dc *dc,
  47                struct dc_state *context)
  48{
  49        int i, display_count;
  50
  51        display_count = 0;
  52        for (i = 0; i < context->stream_count; i++) {
  53                const struct dc_stream_state *stream = context->streams[i];
  54
  55                /*
  56                 * Only notify active stream or virtual stream.
  57                 * Need to notify virtual stream to work around
  58                 * headless case. HPD does not fire when system is in
  59                 * S0i2.
  60                 */
  61                if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
  62                        display_count++;
  63        }
  64
  65        return display_count;
  66}
  67
  68
  69struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
  70{
  71        struct hw_asic_id asic_id = ctx->asic_id;
  72
  73        struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
  74
  75        if (clk_mgr == NULL) {
  76                BREAK_TO_DEBUGGER();
  77                return NULL;
  78        }
  79
  80        switch (asic_id.chip_family) {
  81        case FAMILY_CI:
  82        case FAMILY_KV:
  83                dce_clk_mgr_construct(ctx, clk_mgr);
  84                break;
  85        case FAMILY_CZ:
  86                dce110_clk_mgr_construct(ctx, clk_mgr);
  87                break;
  88        case FAMILY_VI:
  89                if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
  90                                ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
  91                        dce_clk_mgr_construct(ctx, clk_mgr);
  92                        break;
  93                }
  94                if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
  95                                ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
  96                                ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
  97                        dce112_clk_mgr_construct(ctx, clk_mgr);
  98                        break;
  99                }
 100                if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
 101                        dce112_clk_mgr_construct(ctx, clk_mgr);
 102                        break;
 103                }
 104                break;
 105        case FAMILY_AI:
 106                if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
 107                        dce121_clk_mgr_construct(ctx, clk_mgr);
 108                else
 109                        dce120_clk_mgr_construct(ctx, clk_mgr);
 110                break;
 111
 112#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 113        case FAMILY_RV:
 114#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 115                if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
 116                        rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 117                        break;
 118                }
 119#endif  /* DCN2_1 */
 120                if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
 121                        rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 122                        break;
 123                }
 124                if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
 125                                ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
 126                        rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 127                        break;
 128                }
 129                break;
 130#endif  /* Family RV */
 131
 132#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 133        case FAMILY_NV:
 134                dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 135                break;
 136#endif /* Family NV */
 137
 138        default:
 139                ASSERT(0); /* Unknown Asic */
 140                break;
 141        }
 142
 143        return &clk_mgr->base;
 144}
 145
 146void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 147{
 148        struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 149
 150        kfree(clk_mgr);
 151}
 152
 153