linux/drivers/gpu/drm/amd/display/dc/dc.h
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   1/*
   2 * Copyright 2012-14 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef DC_INTERFACE_H_
  27#define DC_INTERFACE_H_
  28
  29#include "dc_types.h"
  30#include "grph_object_defs.h"
  31#include "logger_types.h"
  32#include "gpio_types.h"
  33#include "link_service_types.h"
  34#include "grph_object_ctrl_defs.h"
  35#include <inc/hw/opp.h>
  36
  37#include "inc/hw_sequencer.h"
  38#include "inc/compressor.h"
  39#include "inc/hw/dmcu.h"
  40#include "dml/display_mode_lib.h"
  41
  42#define DC_VER "3.2.48"
  43
  44#define MAX_SURFACES 3
  45#define MAX_PLANES 6
  46#define MAX_STREAMS 6
  47#define MAX_SINKS_PER_LINK 4
  48
  49/*******************************************************************************
  50 * Display Core Interfaces
  51 ******************************************************************************/
  52struct dc_versions {
  53        const char *dc_ver;
  54        struct dmcu_version dmcu_version;
  55};
  56
  57enum dc_plane_type {
  58        DC_PLANE_TYPE_INVALID,
  59        DC_PLANE_TYPE_DCE_RGB,
  60        DC_PLANE_TYPE_DCE_UNDERLAY,
  61        DC_PLANE_TYPE_DCN_UNIVERSAL,
  62};
  63
  64struct dc_plane_cap {
  65        enum dc_plane_type type;
  66        uint32_t blends_with_above : 1;
  67        uint32_t blends_with_below : 1;
  68        uint32_t per_pixel_alpha : 1;
  69        struct {
  70                uint32_t argb8888 : 1;
  71                uint32_t nv12 : 1;
  72                uint32_t fp16 : 1;
  73                uint32_t p010 : 1;
  74                uint32_t ayuv : 1;
  75        } pixel_format_support;
  76        // max upscaling factor x1000
  77        // upscaling factors are always >= 1
  78        // for example, 1080p -> 8K is 4.0, or 4000 raw value
  79        struct {
  80                uint32_t argb8888;
  81                uint32_t nv12;
  82                uint32_t fp16;
  83        } max_upscale_factor;
  84        // max downscale factor x1000
  85        // downscale factors are always <= 1
  86        // for example, 8K -> 1080p is 0.25, or 250 raw value
  87        struct {
  88                uint32_t argb8888;
  89                uint32_t nv12;
  90                uint32_t fp16;
  91        } max_downscale_factor;
  92};
  93
  94struct dc_caps {
  95        uint32_t max_streams;
  96        uint32_t max_links;
  97        uint32_t max_audios;
  98        uint32_t max_slave_planes;
  99        uint32_t max_planes;
 100        uint32_t max_downscale_ratio;
 101        uint32_t i2c_speed_in_khz;
 102        uint32_t dmdata_alloc_size;
 103        unsigned int max_cursor_size;
 104        unsigned int max_video_width;
 105        int linear_pitch_alignment;
 106        bool dcc_const_color;
 107        bool dynamic_audio;
 108        bool is_apu;
 109        bool dual_link_dvi;
 110        bool post_blend_color_processing;
 111        bool force_dp_tps4_for_cp2520;
 112        bool disable_dp_clk_share;
 113        bool psp_setup_panel_mode;
 114#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 115        bool hw_3d_lut;
 116#endif
 117        struct dc_plane_cap planes[MAX_PLANES];
 118};
 119
 120#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 121struct dc_bug_wa {
 122        bool no_connect_phy_config;
 123        bool dedcn20_305_wa;
 124        bool skip_clock_update;
 125};
 126#endif
 127
 128struct dc_dcc_surface_param {
 129        struct dc_size surface_size;
 130        enum surface_pixel_format format;
 131        enum swizzle_mode_values swizzle_mode;
 132        enum dc_scan_direction scan;
 133};
 134
 135struct dc_dcc_setting {
 136        unsigned int max_compressed_blk_size;
 137        unsigned int max_uncompressed_blk_size;
 138        bool independent_64b_blks;
 139};
 140
 141struct dc_surface_dcc_cap {
 142        union {
 143                struct {
 144                        struct dc_dcc_setting rgb;
 145                } grph;
 146
 147                struct {
 148                        struct dc_dcc_setting luma;
 149                        struct dc_dcc_setting chroma;
 150                } video;
 151        };
 152
 153        bool capable;
 154        bool const_color_support;
 155};
 156
 157struct dc_static_screen_events {
 158        bool force_trigger;
 159        bool cursor_update;
 160        bool surface_update;
 161        bool overlay_update;
 162};
 163
 164
 165/* Surface update type is used by dc_update_surfaces_and_stream
 166 * The update type is determined at the very beginning of the function based
 167 * on parameters passed in and decides how much programming (or updating) is
 168 * going to be done during the call.
 169 *
 170 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 171 * logical calculations or hardware register programming. This update MUST be
 172 * ISR safe on windows. Currently fast update will only be used to flip surface
 173 * address.
 174 *
 175 * UPDATE_TYPE_MED is used for slower updates which require significant hw
 176 * re-programming however do not affect bandwidth consumption or clock
 177 * requirements. At present, this is the level at which front end updates
 178 * that do not require us to run bw_calcs happen. These are in/out transfer func
 179 * updates, viewport offset changes, recout size changes and pixel depth changes.
 180 * This update can be done at ISR, but we want to minimize how often this happens.
 181 *
 182 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 183 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 184 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 185 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 186 * a full update. This cannot be done at ISR level and should be a rare event.
 187 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 188 * underscan we don't expect to see this call at all.
 189 */
 190
 191enum surface_update_type {
 192        UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
 193        UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
 194        UPDATE_TYPE_FULL, /* may need to shuffle resources */
 195};
 196
 197/* Forward declaration*/
 198struct dc;
 199struct dc_plane_state;
 200struct dc_state;
 201
 202
 203struct dc_cap_funcs {
 204        bool (*get_dcc_compression_cap)(const struct dc *dc,
 205                        const struct dc_dcc_surface_param *input,
 206                        struct dc_surface_dcc_cap *output);
 207};
 208
 209struct link_training_settings;
 210
 211
 212/* Structure to hold configuration flags set by dm at dc creation. */
 213struct dc_config {
 214        bool gpu_vm_support;
 215        bool disable_disp_pll_sharing;
 216        bool fbc_support;
 217        bool optimize_edp_link_rate;
 218        bool disable_fractional_pwm;
 219        bool allow_seamless_boot_optimization;
 220        bool power_down_display_on_boot;
 221        bool edp_not_connected;
 222        bool forced_clocks;
 223        bool multi_mon_pp_mclk_switch;
 224};
 225
 226enum visual_confirm {
 227        VISUAL_CONFIRM_DISABLE = 0,
 228        VISUAL_CONFIRM_SURFACE = 1,
 229        VISUAL_CONFIRM_HDR = 2,
 230};
 231
 232enum dcc_option {
 233        DCC_ENABLE = 0,
 234        DCC_DISABLE = 1,
 235        DCC_HALF_REQ_DISALBE = 2,
 236};
 237
 238enum pipe_split_policy {
 239        MPC_SPLIT_DYNAMIC = 0,
 240        MPC_SPLIT_AVOID = 1,
 241        MPC_SPLIT_AVOID_MULT_DISP = 2,
 242};
 243
 244enum wm_report_mode {
 245        WM_REPORT_DEFAULT = 0,
 246        WM_REPORT_OVERRIDE = 1,
 247};
 248
 249/*
 250 * For any clocks that may differ per pipe
 251 * only the max is stored in this structure
 252 */
 253struct dc_clocks {
 254        int dispclk_khz;
 255        int max_supported_dppclk_khz;
 256        int max_supported_dispclk_khz;
 257        int dppclk_khz;
 258        int bw_dppclk_khz; /*a copy of dppclk_khz*/
 259        int bw_dispclk_khz;
 260        int dcfclk_khz;
 261        int socclk_khz;
 262        int dcfclk_deep_sleep_khz;
 263        int fclk_khz;
 264        int phyclk_khz;
 265        int dramclk_khz;
 266        bool p_state_change_support;
 267
 268        /*
 269         * Elements below are not compared for the purposes of
 270         * optimization required
 271         */
 272        bool prev_p_state_change_support;
 273};
 274
 275struct dc_bw_validation_profile {
 276        bool enable;
 277
 278        unsigned long long total_ticks;
 279        unsigned long long voltage_level_ticks;
 280        unsigned long long watermark_ticks;
 281        unsigned long long rq_dlg_ticks;
 282
 283        unsigned long long total_count;
 284        unsigned long long skip_fast_count;
 285        unsigned long long skip_pass_count;
 286        unsigned long long skip_fail_count;
 287};
 288
 289#define BW_VAL_TRACE_SETUP() \
 290                unsigned long long end_tick = 0; \
 291                unsigned long long voltage_level_tick = 0; \
 292                unsigned long long watermark_tick = 0; \
 293                unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
 294                                dm_get_timestamp(dc->ctx) : 0
 295
 296#define BW_VAL_TRACE_COUNT() \
 297                if (dc->debug.bw_val_profile.enable) \
 298                        dc->debug.bw_val_profile.total_count++
 299
 300#define BW_VAL_TRACE_SKIP(status) \
 301                if (dc->debug.bw_val_profile.enable) { \
 302                        if (!voltage_level_tick) \
 303                                voltage_level_tick = dm_get_timestamp(dc->ctx); \
 304                        dc->debug.bw_val_profile.skip_ ## status ## _count++; \
 305                }
 306
 307#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
 308                if (dc->debug.bw_val_profile.enable) \
 309                        voltage_level_tick = dm_get_timestamp(dc->ctx)
 310
 311#define BW_VAL_TRACE_END_WATERMARKS() \
 312                if (dc->debug.bw_val_profile.enable) \
 313                        watermark_tick = dm_get_timestamp(dc->ctx)
 314
 315#define BW_VAL_TRACE_FINISH() \
 316                if (dc->debug.bw_val_profile.enable) { \
 317                        end_tick = dm_get_timestamp(dc->ctx); \
 318                        dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
 319                        dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
 320                        if (watermark_tick) { \
 321                                dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
 322                                dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
 323                        } \
 324                }
 325
 326struct dc_debug_options {
 327        enum visual_confirm visual_confirm;
 328        bool sanity_checks;
 329        bool max_disp_clk;
 330        bool surface_trace;
 331        bool timing_trace;
 332        bool clock_trace;
 333        bool validation_trace;
 334        bool bandwidth_calcs_trace;
 335        int max_downscale_src_width;
 336
 337        /* stutter efficiency related */
 338        bool disable_stutter;
 339        bool use_max_lb;
 340        enum dcc_option disable_dcc;
 341        enum pipe_split_policy pipe_split_policy;
 342        bool force_single_disp_pipe_split;
 343        bool voltage_align_fclk;
 344
 345        bool disable_dfs_bypass;
 346        bool disable_dpp_power_gate;
 347        bool disable_hubp_power_gate;
 348#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 349        bool disable_dsc_power_gate;
 350#endif
 351        bool disable_pplib_wm_range;
 352        enum wm_report_mode pplib_wm_report_mode;
 353        unsigned int min_disp_clk_khz;
 354        unsigned int min_dpp_clk_khz;
 355        int sr_exit_time_dpm0_ns;
 356        int sr_enter_plus_exit_time_dpm0_ns;
 357        int sr_exit_time_ns;
 358        int sr_enter_plus_exit_time_ns;
 359        int urgent_latency_ns;
 360        uint32_t underflow_assert_delay_us;
 361        int percent_of_ideal_drambw;
 362        int dram_clock_change_latency_ns;
 363        bool optimized_watermark;
 364        int always_scale;
 365        bool disable_pplib_clock_request;
 366        bool disable_clock_gate;
 367        bool disable_dmcu;
 368        bool disable_psr;
 369        bool force_abm_enable;
 370        bool disable_stereo_support;
 371        bool vsr_support;
 372        bool performance_trace;
 373        bool az_endpoint_mute_only;
 374        bool always_use_regamma;
 375        bool p010_mpo_support;
 376        bool recovery_enabled;
 377        bool avoid_vbios_exec_table;
 378        bool scl_reset_length10;
 379        bool hdmi20_disable;
 380        bool skip_detection_link_training;
 381        bool remove_disconnect_edp;
 382        unsigned int force_odm_combine; //bit vector based on otg inst
 383        unsigned int force_fclk_khz;
 384        bool disable_tri_buf;
 385        struct dc_bw_validation_profile bw_val_profile;
 386#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 387        bool disable_fec;
 388#endif
 389#ifdef CONFIG_DRM_AMD_DC_DCN2_1
 390        bool disable_48mhz_pwrdwn;
 391#endif
 392        /* This forces a hard min on the DCFCLK requested to SMU/PP
 393         * watermarks are not affected.
 394         */
 395        unsigned int force_min_dcfclk_mhz;
 396        bool disable_timing_sync;
 397#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 398        bool cm_in_bypass;
 399#endif
 400        int force_clock_mode;/*every mode change.*/
 401};
 402
 403struct dc_debug_data {
 404        uint32_t ltFailCount;
 405        uint32_t i2cErrorCount;
 406        uint32_t auxErrorCount;
 407};
 408
 409#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 410struct dc_phy_addr_space_config {
 411        struct {
 412                uint64_t start_addr;
 413                uint64_t end_addr;
 414                uint64_t fb_top;
 415                uint64_t fb_offset;
 416                uint64_t fb_base;
 417                uint64_t agp_top;
 418                uint64_t agp_bot;
 419                uint64_t agp_base;
 420        } system_aperture;
 421
 422        struct {
 423                uint64_t page_table_start_addr;
 424                uint64_t page_table_end_addr;
 425                uint64_t page_table_base_addr;
 426        } gart_config;
 427
 428        bool valid;
 429        uint64_t page_table_default_page_addr;
 430};
 431
 432struct dc_virtual_addr_space_config {
 433        uint64_t        page_table_base_addr;
 434        uint64_t        page_table_start_addr;
 435        uint64_t        page_table_end_addr;
 436        uint32_t        page_table_block_size_in_bytes;
 437        uint8_t         page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
 438};
 439#endif
 440
 441struct dc_bounding_box_overrides {
 442        int sr_exit_time_ns;
 443        int sr_enter_plus_exit_time_ns;
 444        int urgent_latency_ns;
 445        int percent_of_ideal_drambw;
 446        int dram_clock_change_latency_ns;
 447        /* This forces a hard min on the DCFCLK we use
 448         * for DML.  Unlike the debug option for forcing
 449         * DCFCLK, this override affects watermark calculations
 450         */
 451        int min_dcfclk_mhz;
 452};
 453
 454struct dc_state;
 455struct resource_pool;
 456struct dce_hwseq;
 457struct gpu_info_soc_bounding_box_v1_0;
 458struct dc {
 459        struct dc_versions versions;
 460        struct dc_caps caps;
 461        struct dc_cap_funcs cap_funcs;
 462        struct dc_config config;
 463        struct dc_debug_options debug;
 464        struct dc_bounding_box_overrides bb_overrides;
 465#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 466        struct dc_bug_wa work_arounds;
 467#endif
 468        struct dc_context *ctx;
 469#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 470        struct dc_phy_addr_space_config vm_pa_config;
 471#endif
 472
 473        uint8_t link_count;
 474        struct dc_link *links[MAX_PIPES * 2];
 475
 476        struct dc_state *current_state;
 477        struct resource_pool *res_pool;
 478
 479        struct clk_mgr *clk_mgr;
 480
 481        /* Display Engine Clock levels */
 482        struct dm_pp_clock_levels sclk_lvls;
 483
 484        /* Inputs into BW and WM calculations. */
 485        struct bw_calcs_dceip *bw_dceip;
 486        struct bw_calcs_vbios *bw_vbios;
 487#ifdef CONFIG_DRM_AMD_DC_DCN1_0
 488        struct dcn_soc_bounding_box *dcn_soc;
 489        struct dcn_ip_params *dcn_ip;
 490        struct display_mode_lib dml;
 491#endif
 492
 493        /* HW functions */
 494        struct hw_sequencer_funcs hwss;
 495        struct dce_hwseq *hwseq;
 496
 497        /* Require to optimize clocks and bandwidth for added/removed planes */
 498        bool optimized_required;
 499
 500        /* Require to maintain clocks and bandwidth for UEFI enabled HW */
 501        bool optimize_seamless_boot;
 502
 503        /* FBC compressor */
 504        struct compressor *fbc_compressor;
 505
 506        struct dc_debug_data debug_data;
 507
 508        const char *build_id;
 509#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 510        struct vm_helper *vm_helper;
 511        const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
 512#endif
 513};
 514
 515enum frame_buffer_mode {
 516        FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
 517        FRAME_BUFFER_MODE_ZFB_ONLY,
 518        FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
 519} ;
 520
 521struct dchub_init_data {
 522        int64_t zfb_phys_addr_base;
 523        int64_t zfb_mc_base_addr;
 524        uint64_t zfb_size_in_byte;
 525        enum frame_buffer_mode fb_mode;
 526        bool dchub_initialzied;
 527        bool dchub_info_valid;
 528};
 529
 530struct dc_init_data {
 531        struct hw_asic_id asic_id;
 532        void *driver; /* ctx */
 533        struct cgs_device *cgs_device;
 534        struct dc_bounding_box_overrides bb_overrides;
 535
 536        int num_virtual_links;
 537        /*
 538         * If 'vbios_override' not NULL, it will be called instead
 539         * of the real VBIOS. Intended use is Diagnostics on FPGA.
 540         */
 541        struct dc_bios *vbios_override;
 542        enum dce_environment dce_environment;
 543
 544        struct dc_config flags;
 545        uint32_t log_mask;
 546#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 547        /**
 548         * gpu_info FW provided soc bounding box struct or 0 if not
 549         * available in FW
 550         */
 551        const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
 552#endif
 553};
 554
 555struct dc_callback_init {
 556        uint8_t reserved;
 557};
 558
 559struct dc *dc_create(const struct dc_init_data *init_params);
 560int dc_get_vmid_use_vector(struct dc *dc);
 561#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 562void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
 563/* Returns the number of vmids supported */
 564int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
 565#endif
 566void dc_init_callbacks(struct dc *dc,
 567                const struct dc_callback_init *init_params);
 568void dc_destroy(struct dc **dc);
 569
 570/*******************************************************************************
 571 * Surface Interfaces
 572 ******************************************************************************/
 573
 574enum {
 575        TRANSFER_FUNC_POINTS = 1025
 576};
 577
 578struct dc_hdr_static_metadata {
 579        /* display chromaticities and white point in units of 0.00001 */
 580        unsigned int chromaticity_green_x;
 581        unsigned int chromaticity_green_y;
 582        unsigned int chromaticity_blue_x;
 583        unsigned int chromaticity_blue_y;
 584        unsigned int chromaticity_red_x;
 585        unsigned int chromaticity_red_y;
 586        unsigned int chromaticity_white_point_x;
 587        unsigned int chromaticity_white_point_y;
 588
 589        uint32_t min_luminance;
 590        uint32_t max_luminance;
 591        uint32_t maximum_content_light_level;
 592        uint32_t maximum_frame_average_light_level;
 593};
 594
 595enum dc_transfer_func_type {
 596        TF_TYPE_PREDEFINED,
 597        TF_TYPE_DISTRIBUTED_POINTS,
 598        TF_TYPE_BYPASS,
 599        TF_TYPE_HWPWL
 600};
 601
 602struct dc_transfer_func_distributed_points {
 603        struct fixed31_32 red[TRANSFER_FUNC_POINTS];
 604        struct fixed31_32 green[TRANSFER_FUNC_POINTS];
 605        struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
 606
 607        uint16_t end_exponent;
 608        uint16_t x_point_at_y1_red;
 609        uint16_t x_point_at_y1_green;
 610        uint16_t x_point_at_y1_blue;
 611};
 612
 613enum dc_transfer_func_predefined {
 614        TRANSFER_FUNCTION_SRGB,
 615        TRANSFER_FUNCTION_BT709,
 616        TRANSFER_FUNCTION_PQ,
 617        TRANSFER_FUNCTION_LINEAR,
 618        TRANSFER_FUNCTION_UNITY,
 619        TRANSFER_FUNCTION_HLG,
 620        TRANSFER_FUNCTION_HLG12,
 621        TRANSFER_FUNCTION_GAMMA22,
 622        TRANSFER_FUNCTION_GAMMA24,
 623        TRANSFER_FUNCTION_GAMMA26
 624};
 625
 626
 627struct dc_transfer_func {
 628        struct kref refcount;
 629        enum dc_transfer_func_type type;
 630        enum dc_transfer_func_predefined tf;
 631        /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
 632        uint32_t sdr_ref_white_level;
 633        struct dc_context *ctx;
 634        union {
 635                struct pwl_params pwl;
 636                struct dc_transfer_func_distributed_points tf_pts;
 637        };
 638};
 639
 640#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 641
 642union dc_3dlut_state {
 643        struct {
 644                uint32_t initialized:1;         /*if 3dlut is went through color module for initialization */
 645                uint32_t rmu_idx_valid:1;       /*if mux settings are valid*/
 646                uint32_t rmu_mux_num:3;         /*index of mux to use*/
 647                uint32_t mpc_rmu0_mux:4;        /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
 648                uint32_t mpc_rmu1_mux:4;
 649                uint32_t mpc_rmu2_mux:4;
 650                uint32_t reserved:15;
 651        } bits;
 652        uint32_t raw;
 653};
 654
 655
 656struct dc_3dlut {
 657        struct kref refcount;
 658        struct tetrahedral_params lut_3d;
 659        uint32_t hdr_multiplier;
 660        bool initialized; /*remove after diag fix*/
 661        union dc_3dlut_state state;
 662        struct dc_context *ctx;
 663};
 664#endif
 665/*
 666 * This structure is filled in by dc_surface_get_status and contains
 667 * the last requested address and the currently active address so the called
 668 * can determine if there are any outstanding flips
 669 */
 670struct dc_plane_status {
 671        struct dc_plane_address requested_address;
 672        struct dc_plane_address current_address;
 673        bool is_flip_pending;
 674        bool is_right_eye;
 675};
 676
 677union surface_update_flags {
 678
 679        struct {
 680                uint32_t addr_update:1;
 681                /* Medium updates */
 682                uint32_t dcc_change:1;
 683                uint32_t color_space_change:1;
 684                uint32_t horizontal_mirror_change:1;
 685                uint32_t per_pixel_alpha_change:1;
 686                uint32_t global_alpha_change:1;
 687                uint32_t sdr_white_level:1;
 688                uint32_t rotation_change:1;
 689                uint32_t swizzle_change:1;
 690                uint32_t scaling_change:1;
 691                uint32_t position_change:1;
 692                uint32_t in_transfer_func_change:1;
 693                uint32_t input_csc_change:1;
 694                uint32_t coeff_reduction_change:1;
 695                uint32_t output_tf_change:1;
 696                uint32_t pixel_format_change:1;
 697                uint32_t plane_size_change:1;
 698
 699                /* Full updates */
 700                uint32_t new_plane:1;
 701                uint32_t bpp_change:1;
 702                uint32_t gamma_change:1;
 703                uint32_t bandwidth_change:1;
 704                uint32_t clock_change:1;
 705                uint32_t stereo_format_change:1;
 706                uint32_t full_update:1;
 707        } bits;
 708
 709        uint32_t raw;
 710};
 711
 712struct dc_plane_state {
 713        struct dc_plane_address address;
 714        struct dc_plane_flip_time time;
 715#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 716        bool triplebuffer_flips;
 717#endif
 718        struct scaling_taps scaling_quality;
 719        struct rect src_rect;
 720        struct rect dst_rect;
 721        struct rect clip_rect;
 722
 723        struct plane_size plane_size;
 724        union dc_tiling_info tiling_info;
 725
 726        struct dc_plane_dcc_param dcc;
 727
 728        struct dc_gamma *gamma_correction;
 729        struct dc_transfer_func *in_transfer_func;
 730        struct dc_bias_and_scale *bias_and_scale;
 731        struct dc_csc_transform input_csc_color_matrix;
 732        struct fixed31_32 coeff_reduction_factor;
 733        uint32_t sdr_white_level;
 734
 735        // TODO: No longer used, remove
 736        struct dc_hdr_static_metadata hdr_static_ctx;
 737
 738        enum dc_color_space color_space;
 739
 740#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 741        struct dc_3dlut *lut3d_func;
 742        struct dc_transfer_func *in_shaper_func;
 743        struct dc_transfer_func *blend_tf;
 744#endif
 745
 746        enum surface_pixel_format format;
 747        enum dc_rotation_angle rotation;
 748        enum plane_stereo_format stereo_format;
 749
 750        bool is_tiling_rotated;
 751        bool per_pixel_alpha;
 752        bool global_alpha;
 753        int  global_alpha_value;
 754        bool visible;
 755        bool flip_immediate;
 756        bool horizontal_mirror;
 757        int layer_index;
 758
 759        union surface_update_flags update_flags;
 760        /* private to DC core */
 761        struct dc_plane_status status;
 762        struct dc_context *ctx;
 763
 764        /* HACK: Workaround for forcing full reprogramming under some conditions */
 765        bool force_full_update;
 766
 767        /* private to dc_surface.c */
 768        enum dc_irq_source irq_source;
 769        struct kref refcount;
 770};
 771
 772struct dc_plane_info {
 773        struct plane_size plane_size;
 774        union dc_tiling_info tiling_info;
 775        struct dc_plane_dcc_param dcc;
 776        enum surface_pixel_format format;
 777        enum dc_rotation_angle rotation;
 778        enum plane_stereo_format stereo_format;
 779        enum dc_color_space color_space;
 780        unsigned int sdr_white_level;
 781        bool horizontal_mirror;
 782        bool visible;
 783        bool per_pixel_alpha;
 784        bool global_alpha;
 785        int  global_alpha_value;
 786        bool input_csc_enabled;
 787        int layer_index;
 788};
 789
 790struct dc_scaling_info {
 791        struct rect src_rect;
 792        struct rect dst_rect;
 793        struct rect clip_rect;
 794        struct scaling_taps scaling_quality;
 795};
 796
 797struct dc_surface_update {
 798        struct dc_plane_state *surface;
 799
 800        /* isr safe update parameters.  null means no updates */
 801        const struct dc_flip_addrs *flip_addr;
 802        const struct dc_plane_info *plane_info;
 803        const struct dc_scaling_info *scaling_info;
 804
 805        /* following updates require alloc/sleep/spin that is not isr safe,
 806         * null means no updates
 807         */
 808        const struct dc_gamma *gamma;
 809        const struct dc_transfer_func *in_transfer_func;
 810
 811        const struct dc_csc_transform *input_csc_color_matrix;
 812        const struct fixed31_32 *coeff_reduction_factor;
 813#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 814        const struct dc_transfer_func *func_shaper;
 815        const struct dc_3dlut *lut3d_func;
 816        const struct dc_transfer_func *blend_tf;
 817#endif
 818};
 819
 820/*
 821 * Create a new surface with default parameters;
 822 */
 823struct dc_plane_state *dc_create_plane_state(struct dc *dc);
 824const struct dc_plane_status *dc_plane_get_status(
 825                const struct dc_plane_state *plane_state);
 826
 827void dc_plane_state_retain(struct dc_plane_state *plane_state);
 828void dc_plane_state_release(struct dc_plane_state *plane_state);
 829
 830void dc_gamma_retain(struct dc_gamma *dc_gamma);
 831void dc_gamma_release(struct dc_gamma **dc_gamma);
 832struct dc_gamma *dc_create_gamma(void);
 833
 834void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
 835void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
 836struct dc_transfer_func *dc_create_transfer_func(void);
 837
 838#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 839struct dc_3dlut *dc_create_3dlut_func(void);
 840void dc_3dlut_func_release(struct dc_3dlut *lut);
 841void dc_3dlut_func_retain(struct dc_3dlut *lut);
 842#endif
 843/*
 844 * This structure holds a surface address.  There could be multiple addresses
 845 * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
 846 * as frame durations and DCC format can also be set.
 847 */
 848struct dc_flip_addrs {
 849        struct dc_plane_address address;
 850        unsigned int flip_timestamp_in_us;
 851        bool flip_immediate;
 852        /* TODO: add flip duration for FreeSync */
 853};
 854
 855bool dc_post_update_surfaces_to_stream(
 856                struct dc *dc);
 857
 858#include "dc_stream.h"
 859
 860/*
 861 * Structure to store surface/stream associations for validation
 862 */
 863struct dc_validation_set {
 864        struct dc_stream_state *stream;
 865        struct dc_plane_state *plane_states[MAX_SURFACES];
 866        uint8_t plane_count;
 867};
 868
 869bool dc_validate_seamless_boot_timing(const struct dc *dc,
 870                                const struct dc_sink *sink,
 871                                struct dc_crtc_timing *crtc_timing);
 872
 873enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
 874
 875void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
 876
 877bool dc_set_generic_gpio_for_stereo(bool enable,
 878                struct gpio_service *gpio_service);
 879
 880/*
 881 * fast_validate: we return after determining if we can support the new state,
 882 * but before we populate the programming info
 883 */
 884enum dc_status dc_validate_global_state(
 885                struct dc *dc,
 886                struct dc_state *new_ctx,
 887                bool fast_validate);
 888
 889
 890void dc_resource_state_construct(
 891                const struct dc *dc,
 892                struct dc_state *dst_ctx);
 893
 894void dc_resource_state_copy_construct(
 895                const struct dc_state *src_ctx,
 896                struct dc_state *dst_ctx);
 897
 898void dc_resource_state_copy_construct_current(
 899                const struct dc *dc,
 900                struct dc_state *dst_ctx);
 901
 902void dc_resource_state_destruct(struct dc_state *context);
 903
 904/*
 905 * TODO update to make it about validation sets
 906 * Set up streams and links associated to drive sinks
 907 * The streams parameter is an absolute set of all active streams.
 908 *
 909 * After this call:
 910 *   Phy, Encoder, Timing Generator are programmed and enabled.
 911 *   New streams are enabled with blank stream; no memory read.
 912 */
 913bool dc_commit_state(struct dc *dc, struct dc_state *context);
 914
 915
 916struct dc_state *dc_create_state(struct dc *dc);
 917struct dc_state *dc_copy_state(struct dc_state *src_ctx);
 918void dc_retain_state(struct dc_state *context);
 919void dc_release_state(struct dc_state *context);
 920
 921/*******************************************************************************
 922 * Link Interfaces
 923 ******************************************************************************/
 924
 925struct dpcd_caps {
 926        union dpcd_rev dpcd_rev;
 927        union max_lane_count max_ln_count;
 928        union max_down_spread max_down_spread;
 929        union dprx_feature dprx_feature;
 930
 931        /* valid only for eDP v1.4 or higher*/
 932        uint8_t edp_supported_link_rates_count;
 933        enum dc_link_rate edp_supported_link_rates[8];
 934
 935        /* dongle type (DP converter, CV smart dongle) */
 936        enum display_dongle_type dongle_type;
 937        /* branch device or sink device */
 938        bool is_branch_dev;
 939        /* Dongle's downstream count. */
 940        union sink_count sink_count;
 941        /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
 942        indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
 943        struct dc_dongle_caps dongle_caps;
 944
 945        uint32_t sink_dev_id;
 946        int8_t sink_dev_id_str[6];
 947        int8_t sink_hw_revision;
 948        int8_t sink_fw_revision[2];
 949
 950        uint32_t branch_dev_id;
 951        int8_t branch_dev_name[6];
 952        int8_t branch_hw_revision;
 953        int8_t branch_fw_revision[2];
 954
 955        bool allow_invalid_MSA_timing_param;
 956        bool panel_mode_edp;
 957        bool dpcd_display_control_capable;
 958        bool ext_receiver_cap_field_present;
 959#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 960        union dpcd_fec_capability fec_cap;
 961        struct dpcd_dsc_capabilities dsc_caps;
 962#endif
 963};
 964
 965#include "dc_link.h"
 966
 967/*******************************************************************************
 968 * Sink Interfaces - A sink corresponds to a display output device
 969 ******************************************************************************/
 970
 971struct dc_container_id {
 972        // 128bit GUID in binary form
 973        unsigned char  guid[16];
 974        // 8 byte port ID -> ELD.PortID
 975        unsigned int   portId[2];
 976        // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
 977        unsigned short manufacturerName;
 978        // 2 byte product code -> ELD.ProductCode
 979        unsigned short productCode;
 980};
 981
 982
 983#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 984struct dc_sink_dsc_caps {
 985        // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
 986        // 'false' if they are sink's DSC caps
 987        bool is_virtual_dpcd_dsc;
 988        struct dsc_dec_dpcd_caps dsc_dec_caps;
 989};
 990#endif
 991
 992/*
 993 * The sink structure contains EDID and other display device properties
 994 */
 995struct dc_sink {
 996        enum signal_type sink_signal;
 997        struct dc_edid dc_edid; /* raw edid */
 998        struct dc_edid_caps edid_caps; /* parse display caps */
 999        struct dc_container_id *dc_container_id;
1000        uint32_t dongle_max_pix_clk;
1001        void *priv;
1002        struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1003        bool converter_disable_audio;
1004
1005#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1006        struct dc_sink_dsc_caps sink_dsc_caps;
1007#endif
1008
1009        /* private to DC core */
1010        struct dc_link *link;
1011        struct dc_context *ctx;
1012
1013        uint32_t sink_id;
1014
1015        /* private to dc_sink.c */
1016        // refcount must be the last member in dc_sink, since we want the
1017        // sink structure to be logically cloneable up to (but not including)
1018        // refcount
1019        struct kref refcount;
1020};
1021
1022void dc_sink_retain(struct dc_sink *sink);
1023void dc_sink_release(struct dc_sink *sink);
1024
1025struct dc_sink_init_data {
1026        enum signal_type sink_signal;
1027        struct dc_link *link;
1028        uint32_t dongle_max_pix_clk;
1029        bool converter_disable_audio;
1030};
1031
1032struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1033
1034/* Newer interfaces  */
1035struct dc_cursor {
1036        struct dc_plane_address address;
1037        struct dc_cursor_attributes attributes;
1038};
1039
1040
1041/*******************************************************************************
1042 * Interrupt interfaces
1043 ******************************************************************************/
1044enum dc_irq_source dc_interrupt_to_irq_source(
1045                struct dc *dc,
1046                uint32_t src_id,
1047                uint32_t ext_id);
1048bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1049void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1050enum dc_irq_source dc_get_hpd_irq_source_at_index(
1051                struct dc *dc, uint32_t link_index);
1052
1053/*******************************************************************************
1054 * Power Interfaces
1055 ******************************************************************************/
1056
1057void dc_set_power_state(
1058                struct dc *dc,
1059                enum dc_acpi_cm_power_state power_state);
1060void dc_resume(struct dc *dc);
1061unsigned int dc_get_current_backlight_pwm(struct dc *dc);
1062unsigned int dc_get_target_backlight_pwm(struct dc *dc);
1063
1064bool dc_is_dmcu_initialized(struct dc *dc);
1065
1066enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1067void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1068#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
1069/*******************************************************************************
1070 * DSC Interfaces
1071 ******************************************************************************/
1072#include "dc_dsc.h"
1073#endif
1074#endif /* DC_INTERFACE_H_ */
1075