1/* 2 * UVD_4_2 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef UVD_4_2_D_H 25#define UVD_4_2_D_H 26 27#define mmUVD_SEMA_ADDR_LOW 0x3bc0 28#define mmUVD_SEMA_ADDR_HIGH 0x3bc1 29#define mmUVD_SEMA_CMD 0x3bc2 30#define mmUVD_GPCOM_VCPU_CMD 0x3bc3 31#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 32#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 33#define mmUVD_ENGINE_CNTL 0x3bc6 34#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 35#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 37#define mmUVD_NO_OP 0x3bff 38#define mmUVD_SEMA_CNTL 0x3d00 39#define mmUVD_LMI_EXT40_ADDR 0x3d26 40#define mmUVD_CTX_INDEX 0x3d28 41#define mmUVD_CTX_DATA 0x3d29 42#define mmUVD_CGC_GATE 0x3d2a 43#define mmUVD_CGC_STATUS 0x3d2b 44#define mmUVD_CGC_CTRL 0x3d2c 45#define mmUVD_CGC_UDEC_STATUS 0x3d2d 46#define mmUVD_LMI_CTRL2 0x3d3d 47#define mmUVD_MASTINT_EN 0x3d40 48#define mmUVD_LMI_ADDR_EXT 0x3d65 49#define mmUVD_LMI_CTRL 0x3d66 50#define mmUVD_LMI_STATUS 0x3d67 51#define mmUVD_LMI_SWAP_CNTL 0x3d6d 52#define mmUVD_MP_SWAP_CNTL 0x3d6f 53#define mmUVD_MPC_CNTL 0x3d77 54#define mmUVD_MPC_SET_MUXA0 0x3d79 55#define mmUVD_MPC_SET_MUXA1 0x3d7a 56#define mmUVD_MPC_SET_MUXB0 0x3d7b 57#define mmUVD_MPC_SET_MUXB1 0x3d7c 58#define mmUVD_MPC_SET_MUX 0x3d7d 59#define mmUVD_MPC_SET_ALU 0x3d7e 60#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 61#define mmUVD_VCPU_CACHE_SIZE0 0x3d83 62#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 63#define mmUVD_VCPU_CACHE_SIZE1 0x3d85 64#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 65#define mmUVD_VCPU_CACHE_SIZE2 0x3d87 66#define mmUVD_VCPU_CNTL 0x3d98 67#define mmUVD_SOFT_RESET 0x3da0 68#define mmUVD_RBC_IB_BASE 0x3da1 69#define mmUVD_RBC_IB_SIZE 0x3da2 70#define mmUVD_RBC_RB_BASE 0x3da3 71#define mmUVD_RBC_RB_RPTR 0x3da4 72#define mmUVD_RBC_RB_WPTR 0x3da5 73#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 74#define mmUVD_RBC_RB_CNTL 0x3da9 75#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa 76#define mmUVD_STATUS 0x3daf 77#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 78#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 79#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 80#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 81#define mmUVD_CONTEXT_ID 0x3dbd 82#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 83#define ixUVD_LMI_CACHE_CTRL 0x9b 84#define ixUVD_LMI_SWAP_CNTL2 0xaa 85#define ixUVD_LMI_ADDR_EXT2 0xab 86#define ixUVD_CGC_MEM_CTRL 0xc0 87#define ixUVD_CGC_CTRL2 0xc1 88#define mmUVD_PGFSM_CONFIG 0x38f8 89#define mmUVD_PGFSM_READ_TILE1 0x38fa 90#define mmUVD_PGFSM_READ_TILE2 0x38fb 91#define mmUVD_POWER_STATUS 0x38fc 92#define ixUVD_MIF_CURR_ADDR_CONFIG 0x48 93#define ixUVD_MIF_REF_ADDR_CONFIG 0x4c 94#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x114 95 96#endif /* UVD_4_2_D_H */ 97