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24#include "pp_debug.h"
25#include <linux/firmware.h>
26#include "amdgpu.h"
27#include "amdgpu_smu.h"
28#include "atomfirmware.h"
29#include "amdgpu_atomfirmware.h"
30#include "smu_v11_0.h"
31#include "smu11_driver_if_arcturus.h"
32#include "soc15_common.h"
33#include "atom.h"
34#include "power_state.h"
35#include "arcturus_ppt.h"
36#include "smu_v11_0_pptable.h"
37#include "arcturus_ppsmc.h"
38#include "nbio/nbio_7_4_sh_mask.h"
39
40#define CTF_OFFSET_EDGE 5
41#define CTF_OFFSET_HOTSPOT 5
42#define CTF_OFFSET_HBM 5
43
44#define MSG_MAP(msg, index) \
45 [SMU_MSG_##msg] = {1, (index)}
46#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
47 [smu_feature] = {1, (arcturus_feature)}
48
49#define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
50#define SMU_FEATURES_LOW_SHIFT 0
51#define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
52#define SMU_FEATURES_HIGH_SHIFT 32
53
54#define SMC_DPM_FEATURE ( \
55 FEATURE_DPM_PREFETCHER_MASK | \
56 FEATURE_DPM_GFXCLK_MASK | \
57 FEATURE_DPM_UCLK_MASK | \
58 FEATURE_DPM_SOCCLK_MASK | \
59 FEATURE_DPM_MP0CLK_MASK | \
60 FEATURE_DPM_FCLK_MASK | \
61 FEATURE_DPM_XGMI_MASK)
62
63
64#define EPSILON 1
65
66static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
67 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
68 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
69 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
70 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
71 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
72 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
73 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
74 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
75 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
76 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
77 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
78 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
79 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
80 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
81 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
82 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
83 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
84 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
85 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
86 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
87 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
88 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
89 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
90 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
91 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
92 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
93 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
94 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
95 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
96 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
97 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
98 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
99 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
100 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
101 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType),
102 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm),
103 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive),
104 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
105 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
106 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0),
107 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0),
108 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1),
109 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1),
110 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
111 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
112 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
113 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset),
114 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc),
115 MSG_MAP(RunGfxDcBtc, PPSMC_MSG_RunGfxDcBtc),
116 MSG_MAP(RunSocDcBtc, PPSMC_MSG_RunSocDcBtc),
117 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
118 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
119 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
120 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
121 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest),
122 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode),
123 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable),
124};
125
126static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
127 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
128 CLK_MAP(SCLK, PPCLK_GFXCLK),
129 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
130 CLK_MAP(FCLK, PPCLK_FCLK),
131 CLK_MAP(UCLK, PPCLK_UCLK),
132 CLK_MAP(MCLK, PPCLK_UCLK),
133 CLK_MAP(DCLK, PPCLK_DCLK),
134 CLK_MAP(VCLK, PPCLK_VCLK),
135};
136
137static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
138 FEA_MAP(DPM_PREFETCHER),
139 FEA_MAP(DPM_GFXCLK),
140 FEA_MAP(DPM_UCLK),
141 FEA_MAP(DPM_SOCCLK),
142 FEA_MAP(DPM_FCLK),
143 FEA_MAP(DPM_MP0CLK),
144 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
145 FEA_MAP(DS_GFXCLK),
146 FEA_MAP(DS_SOCCLK),
147 FEA_MAP(DS_LCLK),
148 FEA_MAP(DS_FCLK),
149 FEA_MAP(DS_UCLK),
150 FEA_MAP(GFX_ULV),
151 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
152 FEA_MAP(RSMU_SMN_CG),
153 FEA_MAP(WAFL_CG),
154 FEA_MAP(PPT),
155 FEA_MAP(TDC),
156 FEA_MAP(APCC_PLUS),
157 FEA_MAP(VR0HOT),
158 FEA_MAP(VR1HOT),
159 FEA_MAP(FW_CTF),
160 FEA_MAP(FAN_CONTROL),
161 FEA_MAP(THERMAL),
162 FEA_MAP(OUT_OF_BAND_MONITOR),
163 FEA_MAP(TEMP_DEPENDENT_VMIN),
164};
165
166static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
167 TAB_MAP(PPTABLE),
168 TAB_MAP(AVFS),
169 TAB_MAP(AVFS_PSM_DEBUG),
170 TAB_MAP(AVFS_FUSE_OVERRIDE),
171 TAB_MAP(PMSTATUSLOG),
172 TAB_MAP(SMU_METRICS),
173 TAB_MAP(DRIVER_SMU_CONFIG),
174 TAB_MAP(OVERDRIVE),
175};
176
177static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
178 PWR_MAP(AC),
179 PWR_MAP(DC),
180};
181
182static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
183 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
184 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
185 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
188};
189
190static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
191{
192 struct smu_11_0_cmn2aisc_mapping mapping;
193
194 if (index >= SMU_MSG_MAX_COUNT)
195 return -EINVAL;
196
197 mapping = arcturus_message_map[index];
198 if (!(mapping.valid_mapping))
199 return -EINVAL;
200
201 return mapping.map_to;
202}
203
204static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
205{
206 struct smu_11_0_cmn2aisc_mapping mapping;
207
208 if (index >= SMU_CLK_COUNT)
209 return -EINVAL;
210
211 mapping = arcturus_clk_map[index];
212 if (!(mapping.valid_mapping)) {
213 pr_warn("Unsupported SMU clk: %d\n", index);
214 return -EINVAL;
215 }
216
217 return mapping.map_to;
218}
219
220static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
221{
222 struct smu_11_0_cmn2aisc_mapping mapping;
223
224 if (index >= SMU_FEATURE_COUNT)
225 return -EINVAL;
226
227 mapping = arcturus_feature_mask_map[index];
228 if (!(mapping.valid_mapping)) {
229 return -EINVAL;
230 }
231
232 return mapping.map_to;
233}
234
235static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
236{
237 struct smu_11_0_cmn2aisc_mapping mapping;
238
239 if (index >= SMU_TABLE_COUNT)
240 return -EINVAL;
241
242 mapping = arcturus_table_map[index];
243 if (!(mapping.valid_mapping)) {
244 pr_warn("Unsupported SMU table: %d\n", index);
245 return -EINVAL;
246 }
247
248 return mapping.map_to;
249}
250
251static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
252{
253 struct smu_11_0_cmn2aisc_mapping mapping;
254
255 if (index >= SMU_POWER_SOURCE_COUNT)
256 return -EINVAL;
257
258 mapping = arcturus_pwr_src_map[index];
259 if (!(mapping.valid_mapping)) {
260 pr_warn("Unsupported SMU power source: %d\n", index);
261 return -EINVAL;
262 }
263
264 return mapping.map_to;
265}
266
267
268static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
269{
270 struct smu_11_0_cmn2aisc_mapping mapping;
271
272 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
273 return -EINVAL;
274
275 mapping = arcturus_workload_map[profile];
276 if (!(mapping.valid_mapping)) {
277 pr_warn("Unsupported SMU power source: %d\n", profile);
278 return -EINVAL;
279 }
280
281 return mapping.map_to;
282}
283
284static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
285{
286 struct smu_table_context *smu_table = &smu->smu_table;
287
288 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
289 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
290
291 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
292 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
293
294 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
295 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
296
297 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
298 if (!smu_table->metrics_table)
299 return -ENOMEM;
300 smu_table->metrics_time = 0;
301
302 return 0;
303}
304
305static int arcturus_allocate_dpm_context(struct smu_context *smu)
306{
307 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
308
309 if (smu_dpm->dpm_context)
310 return -EINVAL;
311
312 smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
313 GFP_KERNEL);
314 if (!smu_dpm->dpm_context)
315 return -ENOMEM;
316
317 if (smu_dpm->golden_dpm_context)
318 return -EINVAL;
319
320 smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
321 GFP_KERNEL);
322 if (!smu_dpm->golden_dpm_context)
323 return -ENOMEM;
324
325 smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
326
327 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
328 GFP_KERNEL);
329 if (!smu_dpm->dpm_current_power_state)
330 return -ENOMEM;
331
332 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
333 GFP_KERNEL);
334 if (!smu_dpm->dpm_request_power_state)
335 return -ENOMEM;
336
337 return 0;
338}
339
340static int
341arcturus_get_allowed_feature_mask(struct smu_context *smu,
342 uint32_t *feature_mask, uint32_t num)
343{
344 if (num > 2)
345 return -EINVAL;
346
347
348 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
349
350 return 0;
351}
352
353static int
354arcturus_set_single_dpm_table(struct smu_context *smu,
355 struct arcturus_single_dpm_table *single_dpm_table,
356 PPCLK_e clk_id)
357{
358 int ret = 0;
359 uint32_t i, num_of_levels = 0, clk;
360
361 ret = smu_send_smc_msg_with_param(smu,
362 SMU_MSG_GetDpmFreqByIndex,
363 (clk_id << 16 | 0xFF));
364 if (ret) {
365 pr_err("[%s] failed to get dpm levels!\n", __func__);
366 return ret;
367 }
368
369 smu_read_smc_arg(smu, &num_of_levels);
370 if (!num_of_levels) {
371 pr_err("[%s] number of clk levels is invalid!\n", __func__);
372 return -EINVAL;
373 }
374
375 single_dpm_table->count = num_of_levels;
376 for (i = 0; i < num_of_levels; i++) {
377 ret = smu_send_smc_msg_with_param(smu,
378 SMU_MSG_GetDpmFreqByIndex,
379 (clk_id << 16 | i));
380 if (ret) {
381 pr_err("[%s] failed to get dpm freq by index!\n", __func__);
382 return ret;
383 }
384 smu_read_smc_arg(smu, &clk);
385 if (!clk) {
386 pr_err("[%s] clk value is invalid!\n", __func__);
387 return -EINVAL;
388 }
389 single_dpm_table->dpm_levels[i].value = clk;
390 single_dpm_table->dpm_levels[i].enabled = true;
391 }
392 return 0;
393}
394
395static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
396{
397 dpm_state->soft_min_level = 0x0;
398 dpm_state->soft_max_level = 0xffff;
399 dpm_state->hard_min_level = 0x0;
400 dpm_state->hard_max_level = 0xffff;
401}
402
403static int arcturus_set_default_dpm_table(struct smu_context *smu)
404{
405 int ret;
406
407 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
408 struct arcturus_dpm_table *dpm_table = NULL;
409 struct arcturus_single_dpm_table *single_dpm_table;
410
411 dpm_table = smu_dpm->dpm_context;
412
413
414 single_dpm_table = &(dpm_table->soc_table);
415 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
416 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
417 PPCLK_SOCCLK);
418 if (ret) {
419 pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
420 return ret;
421 }
422 } else {
423 single_dpm_table->count = 1;
424 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
425 }
426 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
427
428
429 single_dpm_table = &(dpm_table->gfx_table);
430 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
431 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
432 PPCLK_GFXCLK);
433 if (ret) {
434 pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
435 return ret;
436 }
437 } else {
438 single_dpm_table->count = 1;
439 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
440 }
441 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
442
443
444 single_dpm_table = &(dpm_table->mem_table);
445 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
446 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
447 PPCLK_UCLK);
448 if (ret) {
449 pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
450 return ret;
451 }
452 } else {
453 single_dpm_table->count = 1;
454 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
455 }
456 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
457
458
459 single_dpm_table = &(dpm_table->fclk_table);
460 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
461 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
462 PPCLK_FCLK);
463 if (ret) {
464 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
465 return ret;
466 }
467 } else {
468 single_dpm_table->count = 1;
469 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
470 }
471 arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
472
473 memcpy(smu_dpm->golden_dpm_context, dpm_table,
474 sizeof(struct arcturus_dpm_table));
475
476 return 0;
477}
478
479static int arcturus_check_powerplay_table(struct smu_context *smu)
480{
481 return 0;
482}
483
484static int arcturus_store_powerplay_table(struct smu_context *smu)
485{
486 struct smu_11_0_powerplay_table *powerplay_table = NULL;
487 struct smu_table_context *table_context = &smu->smu_table;
488 int ret = 0;
489
490 if (!table_context->power_play_table)
491 return -EINVAL;
492
493 powerplay_table = table_context->power_play_table;
494
495 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
496 sizeof(PPTable_t));
497
498 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
499
500 return ret;
501}
502
503static int arcturus_append_powerplay_table(struct smu_context *smu)
504{
505 struct smu_table_context *table_context = &smu->smu_table;
506 PPTable_t *smc_pptable = table_context->driver_pptable;
507 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
508 int index, ret;
509
510 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
511 smc_dpm_info);
512
513 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
514 (uint8_t **)&smc_dpm_table);
515 if (ret)
516 return ret;
517
518 pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
519 smc_dpm_table->table_header.format_revision,
520 smc_dpm_table->table_header.content_revision);
521
522 if ((smc_dpm_table->table_header.format_revision == 4) &&
523 (smc_dpm_table->table_header.content_revision == 6))
524 memcpy(&smc_pptable->MaxVoltageStepGfx,
525 &smc_dpm_table->maxvoltagestepgfx,
526 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
527
528 return 0;
529}
530
531static int arcturus_run_btc_afll(struct smu_context *smu)
532{
533 return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
534}
535
536static int arcturus_populate_umd_state_clk(struct smu_context *smu)
537{
538 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
539 struct arcturus_dpm_table *dpm_table = NULL;
540 struct arcturus_single_dpm_table *gfx_table = NULL;
541 struct arcturus_single_dpm_table *mem_table = NULL;
542
543 dpm_table = smu_dpm->dpm_context;
544 gfx_table = &(dpm_table->gfx_table);
545 mem_table = &(dpm_table->mem_table);
546
547 smu->pstate_sclk = gfx_table->dpm_levels[0].value;
548 smu->pstate_mclk = mem_table->dpm_levels[0].value;
549
550 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
551 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
552 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
553 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
554 }
555
556 smu->pstate_sclk = smu->pstate_sclk * 100;
557 smu->pstate_mclk = smu->pstate_mclk * 100;
558
559 return 0;
560}
561
562static int arcturus_get_clk_table(struct smu_context *smu,
563 struct pp_clock_levels_with_latency *clocks,
564 struct arcturus_single_dpm_table *dpm_table)
565{
566 int i, count;
567
568 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
569 clocks->num_levels = count;
570
571 for (i = 0; i < count; i++) {
572 clocks->data[i].clocks_in_khz =
573 dpm_table->dpm_levels[i].value * 1000;
574 clocks->data[i].latency_in_us = 0;
575 }
576
577 return 0;
578}
579
580static int arcturus_freqs_in_same_level(int32_t frequency1,
581 int32_t frequency2)
582{
583 return (abs(frequency1 - frequency2) <= EPSILON);
584}
585
586static int arcturus_print_clk_levels(struct smu_context *smu,
587 enum smu_clk_type type, char *buf)
588{
589 int i, now, size = 0;
590 int ret = 0;
591 struct pp_clock_levels_with_latency clocks;
592 struct arcturus_single_dpm_table *single_dpm_table;
593 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
594 struct arcturus_dpm_table *dpm_table = NULL;
595
596 dpm_table = smu_dpm->dpm_context;
597
598 switch (type) {
599 case SMU_SCLK:
600 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
601 if (ret) {
602 pr_err("Attempt to get current gfx clk Failed!");
603 return ret;
604 }
605
606 single_dpm_table = &(dpm_table->gfx_table);
607 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
608 if (ret) {
609 pr_err("Attempt to get gfx clk levels Failed!");
610 return ret;
611 }
612
613 for (i = 0; i < clocks.num_levels; i++)
614 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
615 clocks.data[i].clocks_in_khz / 1000,
616 arcturus_freqs_in_same_level(
617 clocks.data[i].clocks_in_khz / 1000,
618 now / 100) ? "*" : "");
619 break;
620
621 case SMU_MCLK:
622 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
623 if (ret) {
624 pr_err("Attempt to get current mclk Failed!");
625 return ret;
626 }
627
628 single_dpm_table = &(dpm_table->mem_table);
629 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
630 if (ret) {
631 pr_err("Attempt to get memory clk levels Failed!");
632 return ret;
633 }
634
635 for (i = 0; i < clocks.num_levels; i++)
636 size += sprintf(buf + size, "%d: %uMhz %s\n",
637 i, clocks.data[i].clocks_in_khz / 1000,
638 arcturus_freqs_in_same_level(
639 clocks.data[i].clocks_in_khz / 1000,
640 now / 100) ? "*" : "");
641 break;
642
643 case SMU_SOCCLK:
644 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
645 if (ret) {
646 pr_err("Attempt to get current socclk Failed!");
647 return ret;
648 }
649
650 single_dpm_table = &(dpm_table->soc_table);
651 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
652 if (ret) {
653 pr_err("Attempt to get socclk levels Failed!");
654 return ret;
655 }
656
657 for (i = 0; i < clocks.num_levels; i++)
658 size += sprintf(buf + size, "%d: %uMhz %s\n",
659 i, clocks.data[i].clocks_in_khz / 1000,
660 arcturus_freqs_in_same_level(
661 clocks.data[i].clocks_in_khz / 1000,
662 now / 100) ? "*" : "");
663 break;
664
665 case SMU_FCLK:
666 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
667 if (ret) {
668 pr_err("Attempt to get current fclk Failed!");
669 return ret;
670 }
671
672 single_dpm_table = &(dpm_table->fclk_table);
673 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
674 if (ret) {
675 pr_err("Attempt to get fclk levels Failed!");
676 return ret;
677 }
678
679 for (i = 0; i < single_dpm_table->count; i++)
680 size += sprintf(buf + size, "%d: %uMhz %s\n",
681 i, single_dpm_table->dpm_levels[i].value,
682 arcturus_freqs_in_same_level(
683 clocks.data[i].clocks_in_khz / 1000,
684 now / 100) ? "*" : "");
685 break;
686
687 default:
688 break;
689 }
690
691 return size;
692}
693
694static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
695 uint32_t feature_mask)
696{
697 struct arcturus_single_dpm_table *single_dpm_table;
698 struct arcturus_dpm_table *dpm_table =
699 smu->smu_dpm.dpm_context;
700 uint32_t freq;
701 int ret = 0;
702
703 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
704 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
705 single_dpm_table = &(dpm_table->gfx_table);
706 freq = max ? single_dpm_table->dpm_state.soft_max_level :
707 single_dpm_table->dpm_state.soft_min_level;
708 ret = smu_send_smc_msg_with_param(smu,
709 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
710 (PPCLK_GFXCLK << 16) | (freq & 0xffff));
711 if (ret) {
712 pr_err("Failed to set soft %s gfxclk !\n",
713 max ? "max" : "min");
714 return ret;
715 }
716 }
717
718 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
719 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
720 single_dpm_table = &(dpm_table->mem_table);
721 freq = max ? single_dpm_table->dpm_state.soft_max_level :
722 single_dpm_table->dpm_state.soft_min_level;
723 ret = smu_send_smc_msg_with_param(smu,
724 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
725 (PPCLK_UCLK << 16) | (freq & 0xffff));
726 if (ret) {
727 pr_err("Failed to set soft %s memclk !\n",
728 max ? "max" : "min");
729 return ret;
730 }
731 }
732
733 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
734 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
735 single_dpm_table = &(dpm_table->soc_table);
736 freq = max ? single_dpm_table->dpm_state.soft_max_level :
737 single_dpm_table->dpm_state.soft_min_level;
738 ret = smu_send_smc_msg_with_param(smu,
739 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
740 (PPCLK_SOCCLK << 16) | (freq & 0xffff));
741 if (ret) {
742 pr_err("Failed to set soft %s socclk !\n",
743 max ? "max" : "min");
744 return ret;
745 }
746 }
747
748 return ret;
749}
750
751static int arcturus_force_clk_levels(struct smu_context *smu,
752 enum smu_clk_type type, uint32_t mask)
753{
754 struct arcturus_dpm_table *dpm_table;
755 struct arcturus_single_dpm_table *single_dpm_table;
756 uint32_t soft_min_level, soft_max_level;
757 int ret = 0;
758
759 mutex_lock(&(smu->mutex));
760
761 soft_min_level = mask ? (ffs(mask) - 1) : 0;
762 soft_max_level = mask ? (fls(mask) - 1) : 0;
763
764 dpm_table = smu->smu_dpm.dpm_context;
765
766 switch (type) {
767 case SMU_SCLK:
768 single_dpm_table = &(dpm_table->gfx_table);
769
770 if (soft_max_level >= single_dpm_table->count) {
771 pr_err("Clock level specified %d is over max allowed %d\n",
772 soft_max_level, single_dpm_table->count - 1);
773 ret = -EINVAL;
774 break;
775 }
776
777 single_dpm_table->dpm_state.soft_min_level =
778 single_dpm_table->dpm_levels[soft_min_level].value;
779 single_dpm_table->dpm_state.soft_max_level =
780 single_dpm_table->dpm_levels[soft_max_level].value;
781
782 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
783 if (ret) {
784 pr_err("Failed to upload boot level to lowest!\n");
785 break;
786 }
787
788 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
789 if (ret)
790 pr_err("Failed to upload dpm max level to highest!\n");
791
792 break;
793
794 case SMU_MCLK:
795 single_dpm_table = &(dpm_table->mem_table);
796
797 if (soft_max_level >= single_dpm_table->count) {
798 pr_err("Clock level specified %d is over max allowed %d\n",
799 soft_max_level, single_dpm_table->count - 1);
800 ret = -EINVAL;
801 break;
802 }
803
804 single_dpm_table->dpm_state.soft_min_level =
805 single_dpm_table->dpm_levels[soft_min_level].value;
806 single_dpm_table->dpm_state.soft_max_level =
807 single_dpm_table->dpm_levels[soft_max_level].value;
808
809 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
810 if (ret) {
811 pr_err("Failed to upload boot level to lowest!\n");
812 break;
813 }
814
815 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
816 if (ret)
817 pr_err("Failed to upload dpm max level to highest!\n");
818
819 break;
820
821 case SMU_SOCCLK:
822 single_dpm_table = &(dpm_table->soc_table);
823
824 if (soft_max_level >= single_dpm_table->count) {
825 pr_err("Clock level specified %d is over max allowed %d\n",
826 soft_max_level, single_dpm_table->count - 1);
827 ret = -EINVAL;
828 break;
829 }
830
831 single_dpm_table->dpm_state.soft_min_level =
832 single_dpm_table->dpm_levels[soft_min_level].value;
833 single_dpm_table->dpm_state.soft_max_level =
834 single_dpm_table->dpm_levels[soft_max_level].value;
835
836 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
837 if (ret) {
838 pr_err("Failed to upload boot level to lowest!\n");
839 break;
840 }
841
842 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
843 if (ret)
844 pr_err("Failed to upload dpm max level to highest!\n");
845
846 break;
847
848 case SMU_FCLK:
849 single_dpm_table = &(dpm_table->fclk_table);
850
851 if (soft_max_level >= single_dpm_table->count) {
852 pr_err("Clock level specified %d is over max allowed %d\n",
853 soft_max_level, single_dpm_table->count - 1);
854 ret = -EINVAL;
855 break;
856 }
857
858 single_dpm_table->dpm_state.soft_min_level =
859 single_dpm_table->dpm_levels[soft_min_level].value;
860 single_dpm_table->dpm_state.soft_max_level =
861 single_dpm_table->dpm_levels[soft_max_level].value;
862
863 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
864 if (ret) {
865 pr_err("Failed to upload boot level to lowest!\n");
866 break;
867 }
868
869 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
870 if (ret)
871 pr_err("Failed to upload dpm max level to highest!\n");
872
873 break;
874
875 default:
876 break;
877 }
878
879 mutex_unlock(&(smu->mutex));
880 return ret;
881}
882
883static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
884 struct smu_temperature_range *range)
885{
886 PPTable_t *pptable = smu->smu_table.driver_pptable;
887
888 if (!range)
889 return -EINVAL;
890
891 range->max = pptable->TedgeLimit *
892 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
893 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
894 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
895 range->hotspot_crit_max = pptable->ThotspotLimit *
896 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
897 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
898 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
899 range->mem_crit_max = pptable->TmemLimit *
900 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
901 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
902 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
903
904 return 0;
905}
906
907static int arcturus_get_metrics_table(struct smu_context *smu,
908 SmuMetrics_t *metrics_table)
909{
910 struct smu_table_context *smu_table= &smu->smu_table;
911 int ret = 0;
912
913 if (!smu_table->metrics_time ||
914 time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
915 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
916 (void *)smu_table->metrics_table, false);
917 if (ret) {
918 pr_info("Failed to export SMU metrics table!\n");
919 return ret;
920 }
921 smu_table->metrics_time = jiffies;
922 }
923
924 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
925
926 return ret;
927}
928
929static int arcturus_get_current_activity_percent(struct smu_context *smu,
930 enum amd_pp_sensors sensor,
931 uint32_t *value)
932{
933 SmuMetrics_t metrics;
934 int ret = 0;
935
936 if (!value)
937 return -EINVAL;
938
939 ret = arcturus_get_metrics_table(smu, &metrics);
940 if (ret)
941 return ret;
942
943 switch (sensor) {
944 case AMDGPU_PP_SENSOR_GPU_LOAD:
945 *value = metrics.AverageGfxActivity;
946 break;
947 case AMDGPU_PP_SENSOR_MEM_LOAD:
948 *value = metrics.AverageUclkActivity;
949 break;
950 default:
951 pr_err("Invalid sensor for retrieving clock activity\n");
952 return -EINVAL;
953 }
954
955 return 0;
956}
957
958static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
959{
960 SmuMetrics_t metrics;
961 int ret = 0;
962
963 if (!value)
964 return -EINVAL;
965
966 ret = arcturus_get_metrics_table(smu, &metrics);
967 if (ret)
968 return ret;
969
970 *value = metrics.AverageSocketPower << 8;
971
972 return 0;
973}
974
975static int arcturus_thermal_get_temperature(struct smu_context *smu,
976 enum amd_pp_sensors sensor,
977 uint32_t *value)
978{
979 SmuMetrics_t metrics;
980 int ret = 0;
981
982 if (!value)
983 return -EINVAL;
984
985 ret = arcturus_get_metrics_table(smu, &metrics);
986 if (ret)
987 return ret;
988
989 switch (sensor) {
990 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
991 *value = metrics.TemperatureHotspot *
992 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
993 break;
994 case AMDGPU_PP_SENSOR_EDGE_TEMP:
995 *value = metrics.TemperatureEdge *
996 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
997 break;
998 case AMDGPU_PP_SENSOR_MEM_TEMP:
999 *value = metrics.TemperatureHBM *
1000 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1001 break;
1002 default:
1003 pr_err("Invalid sensor for retrieving temp\n");
1004 return -EINVAL;
1005 }
1006
1007 return 0;
1008}
1009
1010static int arcturus_read_sensor(struct smu_context *smu,
1011 enum amd_pp_sensors sensor,
1012 void *data, uint32_t *size)
1013{
1014 struct smu_table_context *table_context = &smu->smu_table;
1015 PPTable_t *pptable = table_context->driver_pptable;
1016 int ret = 0;
1017
1018 if (!data || !size)
1019 return -EINVAL;
1020
1021 mutex_lock(&smu->sensor_lock);
1022 switch (sensor) {
1023 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1024 *(uint32_t *)data = pptable->FanMaximumRpm;
1025 *size = 4;
1026 break;
1027 case AMDGPU_PP_SENSOR_MEM_LOAD:
1028 case AMDGPU_PP_SENSOR_GPU_LOAD:
1029 ret = arcturus_get_current_activity_percent(smu,
1030 sensor,
1031 (uint32_t *)data);
1032 *size = 4;
1033 break;
1034 case AMDGPU_PP_SENSOR_GPU_POWER:
1035 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1036 *size = 4;
1037 break;
1038 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1039 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1040 case AMDGPU_PP_SENSOR_MEM_TEMP:
1041 ret = arcturus_thermal_get_temperature(smu, sensor,
1042 (uint32_t *)data);
1043 *size = 4;
1044 break;
1045 default:
1046 ret = smu_smc_read_sensor(smu, sensor, data, size);
1047 }
1048 mutex_unlock(&smu->sensor_lock);
1049
1050 return ret;
1051}
1052
1053static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1054 uint32_t *speed)
1055{
1056 SmuMetrics_t metrics;
1057 int ret = 0;
1058
1059 if (!speed)
1060 return -EINVAL;
1061
1062 ret = arcturus_get_metrics_table(smu, &metrics);
1063 if (ret)
1064 return ret;
1065
1066 *speed = metrics.CurrFanSpeed;
1067
1068 return ret;
1069}
1070
1071static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1072 uint32_t *speed)
1073{
1074 PPTable_t *pptable = smu->smu_table.driver_pptable;
1075 uint32_t percent, current_rpm;
1076 int ret = 0;
1077
1078 if (!speed)
1079 return -EINVAL;
1080
1081 ret = arcturus_get_fan_speed_rpm(smu, ¤t_rpm);
1082 if (ret)
1083 return ret;
1084
1085 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1086 *speed = percent > 100 ? 100 : percent;
1087
1088 return ret;
1089}
1090
1091static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1092 enum smu_clk_type clk_type,
1093 uint32_t *value)
1094{
1095 static SmuMetrics_t metrics;
1096 int ret = 0, clk_id = 0;
1097
1098 if (!value)
1099 return -EINVAL;
1100
1101 clk_id = smu_clk_get_index(smu, clk_type);
1102 if (clk_id < 0)
1103 return -EINVAL;
1104
1105 ret = arcturus_get_metrics_table(smu, &metrics);
1106 if (ret)
1107 return ret;
1108
1109 switch (clk_id) {
1110 case PPCLK_GFXCLK:
1111
1112
1113
1114
1115
1116
1117 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1118 *value = metrics.CurrClock[PPCLK_GFXCLK];
1119 else
1120 *value = metrics.AverageGfxclkFrequency;
1121 break;
1122 case PPCLK_UCLK:
1123 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1124 *value = metrics.CurrClock[PPCLK_UCLK];
1125 else
1126 *value = metrics.AverageUclkFrequency;
1127 break;
1128 case PPCLK_SOCCLK:
1129 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1130 *value = metrics.CurrClock[PPCLK_SOCCLK];
1131 else
1132 *value = metrics.AverageSocclkFrequency;
1133 break;
1134 default:
1135 *value = metrics.CurrClock[clk_id];
1136 break;
1137 }
1138
1139 return ret;
1140}
1141
1142static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1143{
1144 uint32_t i;
1145
1146 for (i = 0; i < table->count; i++) {
1147 if (table->dpm_levels[i].enabled)
1148 break;
1149 }
1150 if (i >= table->count) {
1151 i = 0;
1152 table->dpm_levels[i].enabled = true;
1153 }
1154
1155 return i;
1156}
1157
1158static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1159{
1160 int i = 0;
1161
1162 if (table->count <= 0) {
1163 pr_err("[%s] DPM Table has no entry!", __func__);
1164 return 0;
1165 }
1166 if (table->count > MAX_DPM_NUMBER) {
1167 pr_err("[%s] DPM Table has too many entries!", __func__);
1168 return MAX_DPM_NUMBER - 1;
1169 }
1170
1171 for (i = table->count - 1; i >= 0; i--) {
1172 if (table->dpm_levels[i].enabled)
1173 break;
1174 }
1175 if (i < 0) {
1176 i = 0;
1177 table->dpm_levels[i].enabled = true;
1178 }
1179
1180 return i;
1181}
1182
1183
1184
1185static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1186{
1187 struct arcturus_dpm_table *dpm_table =
1188 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1189 uint32_t soft_level;
1190 int ret = 0;
1191
1192
1193 if (highest)
1194 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1195 else
1196 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1197
1198 dpm_table->gfx_table.dpm_state.soft_min_level =
1199 dpm_table->gfx_table.dpm_state.soft_max_level =
1200 dpm_table->gfx_table.dpm_levels[soft_level].value;
1201
1202
1203 if (highest)
1204 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1205 else
1206 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1207
1208 dpm_table->mem_table.dpm_state.soft_min_level =
1209 dpm_table->mem_table.dpm_state.soft_max_level =
1210 dpm_table->mem_table.dpm_levels[soft_level].value;
1211
1212
1213 if (highest)
1214 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1215 else
1216 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1217
1218 dpm_table->soc_table.dpm_state.soft_min_level =
1219 dpm_table->soc_table.dpm_state.soft_max_level =
1220 dpm_table->soc_table.dpm_levels[soft_level].value;
1221
1222 ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1223 if (ret) {
1224 pr_err("Failed to upload boot level to %s!\n",
1225 highest ? "highest" : "lowest");
1226 return ret;
1227 }
1228
1229 ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1230 if (ret) {
1231 pr_err("Failed to upload dpm max level to %s!\n!",
1232 highest ? "highest" : "lowest");
1233 return ret;
1234 }
1235
1236 return ret;
1237}
1238
1239static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1240{
1241 struct arcturus_dpm_table *dpm_table =
1242 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1243 uint32_t soft_min_level, soft_max_level;
1244 int ret = 0;
1245
1246
1247 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1248 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1249 dpm_table->gfx_table.dpm_state.soft_min_level =
1250 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1251 dpm_table->gfx_table.dpm_state.soft_max_level =
1252 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1253
1254
1255 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
1256 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
1257 dpm_table->mem_table.dpm_state.soft_min_level =
1258 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1259 dpm_table->mem_table.dpm_state.soft_max_level =
1260 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1261
1262
1263 soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
1264 soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
1265 dpm_table->soc_table.dpm_state.soft_min_level =
1266 dpm_table->soc_table.dpm_levels[soft_min_level].value;
1267 dpm_table->soc_table.dpm_state.soft_max_level =
1268 dpm_table->soc_table.dpm_levels[soft_max_level].value;
1269
1270 ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
1271 if (ret) {
1272 pr_err("Failed to upload DPM Bootup Levels!");
1273 return ret;
1274 }
1275
1276 ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
1277 if (ret) {
1278 pr_err("Failed to upload DPM Max Levels!");
1279 return ret;
1280 }
1281
1282 return ret;
1283}
1284
1285static int
1286arcturus_get_profiling_clk_mask(struct smu_context *smu,
1287 enum amd_dpm_forced_level level,
1288 uint32_t *sclk_mask,
1289 uint32_t *mclk_mask,
1290 uint32_t *soc_mask)
1291{
1292 struct arcturus_dpm_table *dpm_table =
1293 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1294 struct arcturus_single_dpm_table *gfx_dpm_table;
1295 struct arcturus_single_dpm_table *mem_dpm_table;
1296 struct arcturus_single_dpm_table *soc_dpm_table;
1297
1298 if (!smu->smu_dpm.dpm_context)
1299 return -EINVAL;
1300
1301 gfx_dpm_table = &dpm_table->gfx_table;
1302 mem_dpm_table = &dpm_table->mem_table;
1303 soc_dpm_table = &dpm_table->soc_table;
1304
1305 *sclk_mask = 0;
1306 *mclk_mask = 0;
1307 *soc_mask = 0;
1308
1309 if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1310 mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1311 soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1312 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1313 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1314 *soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1315 }
1316
1317 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1318 *sclk_mask = 0;
1319 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1320 *mclk_mask = 0;
1321 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1322 *sclk_mask = gfx_dpm_table->count - 1;
1323 *mclk_mask = mem_dpm_table->count - 1;
1324 *soc_mask = soc_dpm_table->count - 1;
1325 }
1326
1327 return 0;
1328}
1329
1330static int arcturus_get_power_limit(struct smu_context *smu,
1331 uint32_t *limit,
1332 bool asic_default)
1333{
1334 PPTable_t *pptable = smu->smu_table.driver_pptable;
1335 uint32_t asic_default_power_limit = 0;
1336 int ret = 0;
1337 int power_src;
1338
1339 if (!smu->default_power_limit ||
1340 !smu->power_limit) {
1341 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1342 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1343 if (power_src < 0)
1344 return -EINVAL;
1345
1346 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1347 power_src << 16);
1348 if (ret) {
1349 pr_err("[%s] get PPT limit failed!", __func__);
1350 return ret;
1351 }
1352 smu_read_smc_arg(smu, &asic_default_power_limit);
1353 } else {
1354
1355 if (!pptable) {
1356 pr_err("Cannot get PPT limit due to pptable missing!");
1357 return -EINVAL;
1358 }
1359 asic_default_power_limit =
1360 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1361 }
1362
1363 if (smu->od_enabled) {
1364 asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
1365 asic_default_power_limit /= 100;
1366 }
1367
1368 smu->default_power_limit = asic_default_power_limit;
1369 smu->power_limit = asic_default_power_limit;
1370 }
1371
1372 if (asic_default)
1373 *limit = smu->default_power_limit;
1374 else
1375 *limit = smu->power_limit;
1376
1377 return 0;
1378}
1379
1380static int arcturus_get_power_profile_mode(struct smu_context *smu,
1381 char *buf)
1382{
1383 static const char *profile_name[] = {
1384 "BOOTUP_DEFAULT",
1385 "3D_FULL_SCREEN",
1386 "POWER_SAVING",
1387 "VIDEO",
1388 "VR",
1389 "COMPUTE",
1390 "CUSTOM"};
1391 uint32_t i, size = 0;
1392 int16_t workload_type = 0;
1393
1394 if (!smu->pm_enabled || !buf)
1395 return -EINVAL;
1396
1397 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1398
1399
1400
1401
1402 workload_type = smu_workload_get_type(smu, i);
1403 if (workload_type < 0)
1404 continue;
1405
1406 size += sprintf(buf + size, "%2d %14s%s\n",
1407 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1408 }
1409
1410 return size;
1411}
1412
1413static int arcturus_set_power_profile_mode(struct smu_context *smu,
1414 long *input,
1415 uint32_t size)
1416{
1417 int workload_type = 0;
1418 uint32_t profile_mode = input[size];
1419 int ret = 0;
1420
1421 if (!smu->pm_enabled)
1422 return -EINVAL;
1423
1424 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1425 pr_err("Invalid power profile mode %d\n", profile_mode);
1426 return -EINVAL;
1427 }
1428
1429
1430
1431
1432
1433 workload_type = smu_workload_get_type(smu, profile_mode);
1434 if (workload_type < 0) {
1435 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1436 return -EINVAL;
1437 }
1438
1439 ret = smu_send_smc_msg_with_param(smu,
1440 SMU_MSG_SetWorkloadMask,
1441 1 << workload_type);
1442 if (ret) {
1443 pr_err("Fail to set workload type %d\n", workload_type);
1444 return ret;
1445 }
1446
1447 smu->power_profile_mode = profile_mode;
1448
1449 return 0;
1450}
1451
1452static void arcturus_dump_pptable(struct smu_context *smu)
1453{
1454 struct smu_table_context *table_context = &smu->smu_table;
1455 PPTable_t *pptable = table_context->driver_pptable;
1456 int i;
1457
1458 pr_info("Dumped PPTable:\n");
1459
1460 pr_info("Version = 0x%08x\n", pptable->Version);
1461
1462 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1463 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1464
1465 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1466 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1467 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1468 }
1469
1470 pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1471 pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1472 pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1473 pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1474
1475 pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1476 pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1477 pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1478 pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1479 pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1480 pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1481 pr_info("FitLimit = %d\n", pptable->FitLimit);
1482
1483 pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1484 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1485
1486 pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1487
1488 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1489 pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1490
1491 pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1492 pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1493 pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1494 pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1495
1496 pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1497 pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1498 pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1499 pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1500
1501 pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1502 pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1503
1504 pr_info("[PPCLK_GFXCLK]\n"
1505 " .VoltageMode = 0x%02x\n"
1506 " .SnapToDiscrete = 0x%02x\n"
1507 " .NumDiscreteLevels = 0x%02x\n"
1508 " .padding = 0x%02x\n"
1509 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1510 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1511 " .SsFmin = 0x%04x\n"
1512 " .Padding_16 = 0x%04x\n",
1513 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1514 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1515 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1516 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1517 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1518 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1519 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1520 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1521 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1522 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1523 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1524
1525 pr_info("[PPCLK_VCLK]\n"
1526 " .VoltageMode = 0x%02x\n"
1527 " .SnapToDiscrete = 0x%02x\n"
1528 " .NumDiscreteLevels = 0x%02x\n"
1529 " .padding = 0x%02x\n"
1530 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1531 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1532 " .SsFmin = 0x%04x\n"
1533 " .Padding_16 = 0x%04x\n",
1534 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1535 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1536 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1537 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1538 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1539 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1540 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1541 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1542 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1543 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1544 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1545
1546 pr_info("[PPCLK_DCLK]\n"
1547 " .VoltageMode = 0x%02x\n"
1548 " .SnapToDiscrete = 0x%02x\n"
1549 " .NumDiscreteLevels = 0x%02x\n"
1550 " .padding = 0x%02x\n"
1551 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1552 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1553 " .SsFmin = 0x%04x\n"
1554 " .Padding_16 = 0x%04x\n",
1555 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1556 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1557 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1558 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1559 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1560 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1561 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1562 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1563 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1564 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1565 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1566
1567 pr_info("[PPCLK_SOCCLK]\n"
1568 " .VoltageMode = 0x%02x\n"
1569 " .SnapToDiscrete = 0x%02x\n"
1570 " .NumDiscreteLevels = 0x%02x\n"
1571 " .padding = 0x%02x\n"
1572 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1573 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1574 " .SsFmin = 0x%04x\n"
1575 " .Padding_16 = 0x%04x\n",
1576 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1577 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1578 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1579 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1580 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1581 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1582 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1583 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1584 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1585 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1586 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1587
1588 pr_info("[PPCLK_UCLK]\n"
1589 " .VoltageMode = 0x%02x\n"
1590 " .SnapToDiscrete = 0x%02x\n"
1591 " .NumDiscreteLevels = 0x%02x\n"
1592 " .padding = 0x%02x\n"
1593 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1594 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1595 " .SsFmin = 0x%04x\n"
1596 " .Padding_16 = 0x%04x\n",
1597 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1598 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1599 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1600 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1601 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1602 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1603 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1604 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1605 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1606 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1607 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1608
1609 pr_info("[PPCLK_FCLK]\n"
1610 " .VoltageMode = 0x%02x\n"
1611 " .SnapToDiscrete = 0x%02x\n"
1612 " .NumDiscreteLevels = 0x%02x\n"
1613 " .padding = 0x%02x\n"
1614 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1615 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1616 " .SsFmin = 0x%04x\n"
1617 " .Padding_16 = 0x%04x\n",
1618 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1619 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1620 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1621 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1622 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1623 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1624 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1625 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1626 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1627 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1628 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1629
1630
1631 pr_info("FreqTableGfx\n");
1632 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1633 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1634
1635 pr_info("FreqTableVclk\n");
1636 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1637 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1638
1639 pr_info("FreqTableDclk\n");
1640 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1641 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1642
1643 pr_info("FreqTableSocclk\n");
1644 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1645 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1646
1647 pr_info("FreqTableUclk\n");
1648 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1649 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1650
1651 pr_info("FreqTableFclk\n");
1652 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1653 pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1654
1655 pr_info("Mp0clkFreq\n");
1656 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1657 pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1658
1659 pr_info("Mp0DpmVoltage\n");
1660 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1661 pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1662
1663 pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1664 pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1665 pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1666 pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1667 pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1668 pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1669 pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1670 pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1671 pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1672
1673 pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1674 pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1675 pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1676 pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1677
1678 pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1679 pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1680
1681 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1682 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1683 pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1684 pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1685 pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1686 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1687
1688 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1689 pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1690 pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1691 pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1692 pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1693 pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1694 pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1695 pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1696 pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1697
1698 pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1699 pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1700 pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1701 pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1702
1703 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1704 pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1705 pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1706 pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1707
1708 pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1709 pptable->dBtcGbGfxPll.a,
1710 pptable->dBtcGbGfxPll.b,
1711 pptable->dBtcGbGfxPll.c);
1712 pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1713 pptable->dBtcGbGfxAfll.a,
1714 pptable->dBtcGbGfxAfll.b,
1715 pptable->dBtcGbGfxAfll.c);
1716 pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1717 pptable->dBtcGbSoc.a,
1718 pptable->dBtcGbSoc.b,
1719 pptable->dBtcGbSoc.c);
1720
1721 pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1722 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1723 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1724 pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1725 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1726 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1727
1728 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1729 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1730 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1731 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1732 pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1733 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1734 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1735 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1736
1737 pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1738 pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1739
1740 pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1741 pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1742 pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1743 pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1744
1745 pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1746 pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1747 pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1748 pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1749
1750 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1751 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1752
1753 pr_info("XgmiDpmPstates\n");
1754 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1755 pr_info(" .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1756 pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1757 pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1758
1759 pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1760 pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1761 pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1762 pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1763 pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1764 pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1765 pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1766 pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1767
1768 pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1769 pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1770 pptable->ReservedEquation0.a,
1771 pptable->ReservedEquation0.b,
1772 pptable->ReservedEquation0.c);
1773 pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1774 pptable->ReservedEquation1.a,
1775 pptable->ReservedEquation1.b,
1776 pptable->ReservedEquation1.c);
1777 pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1778 pptable->ReservedEquation2.a,
1779 pptable->ReservedEquation2.b,
1780 pptable->ReservedEquation2.c);
1781 pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1782 pptable->ReservedEquation3.a,
1783 pptable->ReservedEquation3.b,
1784 pptable->ReservedEquation3.c);
1785
1786 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1787 pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1788
1789 pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1790 pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1791 pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1792
1793 pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1794 pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1795
1796 pr_info("Board Parameters:\n");
1797 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1798 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1799
1800 pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1801 pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1802 pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1803 pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1804
1805 pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1806 pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1807
1808 pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1809 pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1810 pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1811
1812 pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1813 pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1814 pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1815
1816 pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1817 pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1818 pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1819
1820 pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1821 pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1822 pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1823
1824 pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1825 pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1826 pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1827 pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1828
1829 pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1830 pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1831 pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1832
1833 pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1834 pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1835 pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1836
1837 pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1838 pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1839 pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1840
1841 pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1842 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1843 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1844
1845 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1846 pr_info("I2cControllers[%d]:\n", i);
1847 pr_info(" .Enabled = %d\n",
1848 pptable->I2cControllers[i].Enabled);
1849 pr_info(" .SlaveAddress = 0x%x\n",
1850 pptable->I2cControllers[i].SlaveAddress);
1851 pr_info(" .ControllerPort = %d\n",
1852 pptable->I2cControllers[i].ControllerPort);
1853 pr_info(" .ControllerName = %d\n",
1854 pptable->I2cControllers[i].ControllerName);
1855 pr_info(" .ThermalThrottler = %d\n",
1856 pptable->I2cControllers[i].ThermalThrotter);
1857 pr_info(" .I2cProtocol = %d\n",
1858 pptable->I2cControllers[i].I2cProtocol);
1859 pr_info(" .Speed = %d\n",
1860 pptable->I2cControllers[i].Speed);
1861 }
1862
1863 pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1864 pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1865
1866 pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1867
1868 pr_info("XgmiLinkSpeed\n");
1869 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1870 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1871 pr_info("XgmiLinkWidth\n");
1872 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1873 pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1874 pr_info("XgmiFclkFreq\n");
1875 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1876 pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1877 pr_info("XgmiSocVoltage\n");
1878 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1879 pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1880
1881}
1882
1883static bool arcturus_is_dpm_running(struct smu_context *smu)
1884{
1885 int ret = 0;
1886 uint32_t feature_mask[2];
1887 unsigned long feature_enabled;
1888 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1889 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1890 ((uint64_t)feature_mask[1] << 32));
1891 return !!(feature_enabled & SMC_DPM_FEATURE);
1892}
1893
1894static const struct pptable_funcs arcturus_ppt_funcs = {
1895
1896 .get_smu_msg_index = arcturus_get_smu_msg_index,
1897 .get_smu_clk_index = arcturus_get_smu_clk_index,
1898 .get_smu_feature_index = arcturus_get_smu_feature_index,
1899 .get_smu_table_index = arcturus_get_smu_table_index,
1900 .get_smu_power_index= arcturus_get_pwr_src_index,
1901 .get_workload_type = arcturus_get_workload_type,
1902
1903 .tables_init = arcturus_tables_init,
1904 .alloc_dpm_context = arcturus_allocate_dpm_context,
1905
1906 .check_powerplay_table = arcturus_check_powerplay_table,
1907 .store_powerplay_table = arcturus_store_powerplay_table,
1908 .append_powerplay_table = arcturus_append_powerplay_table,
1909
1910 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
1911
1912 .run_afll_btc = arcturus_run_btc_afll,
1913
1914 .set_default_dpm_table = arcturus_set_default_dpm_table,
1915 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
1916 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
1917 .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
1918 .print_clk_levels = arcturus_print_clk_levels,
1919 .force_clk_levels = arcturus_force_clk_levels,
1920 .read_sensor = arcturus_read_sensor,
1921 .get_fan_speed_percent = arcturus_get_fan_speed_percent,
1922 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
1923 .force_dpm_limit_value = arcturus_force_dpm_limit_value,
1924 .unforce_dpm_levels = arcturus_unforce_dpm_levels,
1925 .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
1926 .get_power_profile_mode = arcturus_get_power_profile_mode,
1927 .set_power_profile_mode = arcturus_set_power_profile_mode,
1928
1929 .dump_pptable = arcturus_dump_pptable,
1930 .get_power_limit = arcturus_get_power_limit,
1931 .is_dpm_running = arcturus_is_dpm_running,
1932};
1933
1934void arcturus_set_ppt_funcs(struct smu_context *smu)
1935{
1936 struct smu_table_context *smu_table = &smu->smu_table;
1937
1938 smu->ppt_funcs = &arcturus_ppt_funcs;
1939 smu_table->table_count = TABLE_COUNT;
1940}
1941
