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9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/module.h>
12#include <linux/of_address.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
16
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_of.h>
19#include <drm/drm_panel.h>
20#include <drm/drm_print.h>
21#include <drm/drm_probe_helper.h>
22
23#include "sun4i_crtc.h"
24#include "sun4i_drv.h"
25#include "sunxi_engine.h"
26
27#define SUN4I_TVE_EN_REG 0x000
28#define SUN4I_TVE_EN_DAC_MAP_MASK GENMASK(19, 4)
29#define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
30#define SUN4I_TVE_EN_ENABLE BIT(0)
31
32#define SUN4I_TVE_CFG0_REG 0x004
33#define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
34#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M BIT(25)
35#define SUN4I_TVE_CFG0_CORE_CONTROL_54M BIT(24)
36#define SUN4I_TVE_CFG0_YC_EN BIT(17)
37#define SUN4I_TVE_CFG0_COMP_EN BIT(16)
38#define SUN4I_TVE_CFG0_RES(x) ((x) & 0xf)
39#define SUN4I_TVE_CFG0_RES_480i SUN4I_TVE_CFG0_RES(0)
40#define SUN4I_TVE_CFG0_RES_576i SUN4I_TVE_CFG0_RES(1)
41
42#define SUN4I_TVE_DAC0_REG 0x008
43#define SUN4I_TVE_DAC0_CLOCK_INVERT BIT(24)
44#define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
45#define SUN4I_TVE_DAC0_LUMA_0_4 SUN4I_TVE_DAC0_LUMA(3)
46#define SUN4I_TVE_DAC0_CHROMA(x) (((x) & 3) << 18)
47#define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
48#define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
49#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS SUN4I_TVE_DAC0_INTERNAL_DAC(3)
50#define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
51
52#define SUN4I_TVE_NOTCH_REG 0x00c
53#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
54
55#define SUN4I_TVE_CHROMA_FREQ_REG 0x010
56
57#define SUN4I_TVE_PORCH_REG 0x014
58#define SUN4I_TVE_PORCH_BACK(x) ((x) << 16)
59#define SUN4I_TVE_PORCH_FRONT(x) (x)
60
61#define SUN4I_TVE_LINE_REG 0x01c
62#define SUN4I_TVE_LINE_FIRST(x) ((x) << 16)
63#define SUN4I_TVE_LINE_NUMBER(x) (x)
64
65#define SUN4I_TVE_LEVEL_REG 0x020
66#define SUN4I_TVE_LEVEL_BLANK(x) ((x) << 16)
67#define SUN4I_TVE_LEVEL_BLACK(x) (x)
68
69#define SUN4I_TVE_DAC1_REG 0x024
70#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x) ((x) << (dac * 8))
71
72#define SUN4I_TVE_DETECT_STA_REG 0x038
73#define SUN4I_TVE_DETECT_STA_DAC(dac) BIT((dac * 8))
74#define SUN4I_TVE_DETECT_STA_UNCONNECTED 0
75#define SUN4I_TVE_DETECT_STA_CONNECTED 1
76#define SUN4I_TVE_DETECT_STA_GROUND 2
77
78#define SUN4I_TVE_CB_CR_LVL_REG 0x10c
79#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x) ((x) << 8)
80#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x) (x)
81
82#define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
83#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x) (x)
84
85#define SUN4I_TVE_BURST_WIDTH_REG 0x114
86#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
87#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x) ((x) << 8)
88#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x) (x)
89
90#define SUN4I_TVE_CB_CR_GAIN_REG 0x118
91#define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
92#define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
93
94#define SUN4I_TVE_SYNC_VBI_REG 0x11c
95#define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
96#define SUN4I_TVE_SYNC_VBI_VBLANK(x) (x)
97
98#define SUN4I_TVE_ACTIVE_LINE_REG 0x124
99#define SUN4I_TVE_ACTIVE_LINE(x) (x)
100
101#define SUN4I_TVE_CHROMA_REG 0x128
102#define SUN4I_TVE_CHROMA_COMP_GAIN(x) ((x) & 3)
103#define SUN4I_TVE_CHROMA_COMP_GAIN_50 SUN4I_TVE_CHROMA_COMP_GAIN(2)
104
105#define SUN4I_TVE_12C_REG 0x12c
106#define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE BIT(8)
107#define SUN4I_TVE_12C_COMP_YUV_EN BIT(0)
108
109#define SUN4I_TVE_RESYNC_REG 0x130
110#define SUN4I_TVE_RESYNC_FIELD BIT(31)
111#define SUN4I_TVE_RESYNC_LINE(x) ((x) << 16)
112#define SUN4I_TVE_RESYNC_PIXEL(x) (x)
113
114#define SUN4I_TVE_SLAVE_REG 0x134
115
116#define SUN4I_TVE_WSS_DATA2_REG 0x244
117
118struct color_gains {
119 u16 cb;
120 u16 cr;
121};
122
123struct burst_levels {
124 u16 cb;
125 u16 cr;
126};
127
128struct video_levels {
129 u16 black;
130 u16 blank;
131};
132
133struct resync_parameters {
134 bool field;
135 u16 line;
136 u16 pixel;
137};
138
139struct tv_mode {
140 char *name;
141
142 u32 mode;
143 u32 chroma_freq;
144 u16 back_porch;
145 u16 front_porch;
146 u16 line_number;
147 u16 vblank_level;
148
149 u32 hdisplay;
150 u16 hfront_porch;
151 u16 hsync_len;
152 u16 hback_porch;
153
154 u32 vdisplay;
155 u16 vfront_porch;
156 u16 vsync_len;
157 u16 vback_porch;
158
159 bool yc_en;
160 bool dac3_en;
161 bool dac_bit25_en;
162
163 const struct color_gains *color_gains;
164 const struct burst_levels *burst_levels;
165 const struct video_levels *video_levels;
166 const struct resync_parameters *resync_params;
167};
168
169struct sun4i_tv {
170 struct drm_connector connector;
171 struct drm_encoder encoder;
172
173 struct clk *clk;
174 struct regmap *regs;
175 struct reset_control *reset;
176
177 struct sun4i_drv *drv;
178};
179
180static const struct video_levels ntsc_video_levels = {
181 .black = 282, .blank = 240,
182};
183
184static const struct video_levels pal_video_levels = {
185 .black = 252, .blank = 252,
186};
187
188static const struct burst_levels ntsc_burst_levels = {
189 .cb = 79, .cr = 0,
190};
191
192static const struct burst_levels pal_burst_levels = {
193 .cb = 40, .cr = 40,
194};
195
196static const struct color_gains ntsc_color_gains = {
197 .cb = 160, .cr = 160,
198};
199
200static const struct color_gains pal_color_gains = {
201 .cb = 224, .cr = 224,
202};
203
204static const struct resync_parameters ntsc_resync_parameters = {
205 .field = false, .line = 14, .pixel = 12,
206};
207
208static const struct resync_parameters pal_resync_parameters = {
209 .field = true, .line = 13, .pixel = 12,
210};
211
212static const struct tv_mode tv_modes[] = {
213 {
214 .name = "NTSC",
215 .mode = SUN4I_TVE_CFG0_RES_480i,
216 .chroma_freq = 0x21f07c1f,
217 .yc_en = true,
218 .dac3_en = true,
219 .dac_bit25_en = true,
220
221 .back_porch = 118,
222 .front_porch = 32,
223 .line_number = 525,
224
225 .hdisplay = 720,
226 .hfront_porch = 18,
227 .hsync_len = 2,
228 .hback_porch = 118,
229
230 .vdisplay = 480,
231 .vfront_porch = 26,
232 .vsync_len = 2,
233 .vback_porch = 17,
234
235 .vblank_level = 240,
236
237 .color_gains = &ntsc_color_gains,
238 .burst_levels = &ntsc_burst_levels,
239 .video_levels = &ntsc_video_levels,
240 .resync_params = &ntsc_resync_parameters,
241 },
242 {
243 .name = "PAL",
244 .mode = SUN4I_TVE_CFG0_RES_576i,
245 .chroma_freq = 0x2a098acb,
246
247 .back_porch = 138,
248 .front_porch = 24,
249 .line_number = 625,
250
251 .hdisplay = 720,
252 .hfront_porch = 3,
253 .hsync_len = 2,
254 .hback_porch = 139,
255
256 .vdisplay = 576,
257 .vfront_porch = 28,
258 .vsync_len = 2,
259 .vback_porch = 19,
260
261 .vblank_level = 252,
262
263 .color_gains = &pal_color_gains,
264 .burst_levels = &pal_burst_levels,
265 .video_levels = &pal_video_levels,
266 .resync_params = &pal_resync_parameters,
267 },
268};
269
270static inline struct sun4i_tv *
271drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
272{
273 return container_of(encoder, struct sun4i_tv,
274 encoder);
275}
276
277static inline struct sun4i_tv *
278drm_connector_to_sun4i_tv(struct drm_connector *connector)
279{
280 return container_of(connector, struct sun4i_tv,
281 connector);
282}
283
284
285
286
287
288
289
290
291static const struct tv_mode *sun4i_tv_find_tv_by_mode(const struct drm_display_mode *mode)
292{
293 int i;
294
295
296 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
297 const struct tv_mode *tv_mode = &tv_modes[i];
298
299 DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
300 mode->name, tv_mode->name);
301
302 if (!strcmp(mode->name, tv_mode->name))
303 return tv_mode;
304 }
305
306
307 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
308 const struct tv_mode *tv_mode = &tv_modes[i];
309
310 DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
311 mode->name, tv_mode->name,
312 mode->vdisplay, tv_mode->vdisplay);
313
314 if (mode->vdisplay == tv_mode->vdisplay)
315 return tv_mode;
316 }
317
318 return NULL;
319}
320
321static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
322 struct drm_display_mode *mode)
323{
324 DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);
325
326 mode->type = DRM_MODE_TYPE_DRIVER;
327 mode->clock = 13500;
328 mode->flags = DRM_MODE_FLAG_INTERLACE;
329
330 mode->hdisplay = tv_mode->hdisplay;
331 mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
332 mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
333 mode->htotal = mode->hsync_end + tv_mode->hback_porch;
334
335 mode->vdisplay = tv_mode->vdisplay;
336 mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
337 mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
338 mode->vtotal = mode->vsync_end + tv_mode->vback_porch;
339}
340
341static void sun4i_tv_disable(struct drm_encoder *encoder)
342{
343 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
344 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
345
346 DRM_DEBUG_DRIVER("Disabling the TV Output\n");
347
348 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
349 SUN4I_TVE_EN_ENABLE,
350 0);
351
352 sunxi_engine_disable_color_correction(crtc->engine);
353}
354
355static void sun4i_tv_enable(struct drm_encoder *encoder)
356{
357 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
358 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
359
360 DRM_DEBUG_DRIVER("Enabling the TV Output\n");
361
362 sunxi_engine_apply_color_correction(crtc->engine);
363
364 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
365 SUN4I_TVE_EN_ENABLE,
366 SUN4I_TVE_EN_ENABLE);
367}
368
369static void sun4i_tv_mode_set(struct drm_encoder *encoder,
370 struct drm_display_mode *mode,
371 struct drm_display_mode *adjusted_mode)
372{
373 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
374 const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
375
376
377 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
378 SUN4I_TVE_EN_DAC_MAP_MASK,
379 SUN4I_TVE_EN_DAC_MAP(0, 1) |
380 SUN4I_TVE_EN_DAC_MAP(1, 2) |
381 SUN4I_TVE_EN_DAC_MAP(2, 3) |
382 SUN4I_TVE_EN_DAC_MAP(3, 4));
383
384
385 regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
386 tv_mode->mode |
387 (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
388 SUN4I_TVE_CFG0_COMP_EN |
389 SUN4I_TVE_CFG0_DAC_CONTROL_54M |
390 SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
391 SUN4I_TVE_CFG0_CORE_CONTROL_54M);
392
393
394 regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
395 SUN4I_TVE_DAC0_DAC_EN(0) |
396 (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
397 SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
398 SUN4I_TVE_DAC0_CHROMA_0_75 |
399 SUN4I_TVE_DAC0_LUMA_0_4 |
400 SUN4I_TVE_DAC0_CLOCK_INVERT |
401 (tv_mode->dac_bit25_en ? BIT(25) : 0) |
402 BIT(30));
403
404
405 regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
406 SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
407 SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
408
409 regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
410 tv_mode->chroma_freq);
411
412
413 regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
414 SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
415 SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
416
417
418 regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
419 SUN4I_TVE_LINE_FIRST(22) |
420 SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));
421
422 regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
423 SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
424 SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
425
426 regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
427 SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
428 SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
429 SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
430 SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
431
432 regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
433 SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
434 SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
435
436
437 regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
438 SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
439 SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
440 SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
441
442 regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
443 SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
444 SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
445
446 regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
447 SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
448 SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
449
450 regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
451 SUN4I_TVE_ACTIVE_LINE(1440));
452
453
454 regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
455 SUN4I_TVE_CHROMA_COMP_GAIN_50);
456
457 regmap_write(tv->regs, SUN4I_TVE_12C_REG,
458 SUN4I_TVE_12C_COMP_YUV_EN |
459 SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
460
461 regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
462 SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
463 SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
464 (tv_mode->resync_params->field ?
465 SUN4I_TVE_RESYNC_FIELD : 0));
466
467 regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
468}
469
470static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
471 .disable = sun4i_tv_disable,
472 .enable = sun4i_tv_enable,
473 .mode_set = sun4i_tv_mode_set,
474};
475
476static void sun4i_tv_destroy(struct drm_encoder *encoder)
477{
478 drm_encoder_cleanup(encoder);
479}
480
481static struct drm_encoder_funcs sun4i_tv_funcs = {
482 .destroy = sun4i_tv_destroy,
483};
484
485static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
486{
487 int i;
488
489 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
490 struct drm_display_mode *mode;
491 const struct tv_mode *tv_mode = &tv_modes[i];
492
493 mode = drm_mode_create(connector->dev);
494 if (!mode) {
495 DRM_ERROR("Failed to create a new display mode\n");
496 return 0;
497 }
498
499 strcpy(mode->name, tv_mode->name);
500
501 sun4i_tv_mode_to_drm_mode(tv_mode, mode);
502 drm_mode_probed_add(connector, mode);
503 }
504
505 return i;
506}
507
508static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
509 struct drm_display_mode *mode)
510{
511
512 return MODE_OK;
513}
514
515static struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
516 .get_modes = sun4i_tv_comp_get_modes,
517 .mode_valid = sun4i_tv_comp_mode_valid,
518};
519
520static void
521sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
522{
523 drm_connector_cleanup(connector);
524}
525
526static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
527 .fill_modes = drm_helper_probe_single_connector_modes,
528 .destroy = sun4i_tv_comp_connector_destroy,
529 .reset = drm_atomic_helper_connector_reset,
530 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
531 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
532};
533
534static struct regmap_config sun4i_tv_regmap_config = {
535 .reg_bits = 32,
536 .val_bits = 32,
537 .reg_stride = 4,
538 .max_register = SUN4I_TVE_WSS_DATA2_REG,
539 .name = "tv-encoder",
540};
541
542static int sun4i_tv_bind(struct device *dev, struct device *master,
543 void *data)
544{
545 struct platform_device *pdev = to_platform_device(dev);
546 struct drm_device *drm = data;
547 struct sun4i_drv *drv = drm->dev_private;
548 struct sun4i_tv *tv;
549 struct resource *res;
550 void __iomem *regs;
551 int ret;
552
553 tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
554 if (!tv)
555 return -ENOMEM;
556 tv->drv = drv;
557 dev_set_drvdata(dev, tv);
558
559 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
560 regs = devm_ioremap_resource(dev, res);
561 if (IS_ERR(regs)) {
562 dev_err(dev, "Couldn't map the TV encoder registers\n");
563 return PTR_ERR(regs);
564 }
565
566 tv->regs = devm_regmap_init_mmio(dev, regs,
567 &sun4i_tv_regmap_config);
568 if (IS_ERR(tv->regs)) {
569 dev_err(dev, "Couldn't create the TV encoder regmap\n");
570 return PTR_ERR(tv->regs);
571 }
572
573 tv->reset = devm_reset_control_get(dev, NULL);
574 if (IS_ERR(tv->reset)) {
575 dev_err(dev, "Couldn't get our reset line\n");
576 return PTR_ERR(tv->reset);
577 }
578
579 ret = reset_control_deassert(tv->reset);
580 if (ret) {
581 dev_err(dev, "Couldn't deassert our reset line\n");
582 return ret;
583 }
584
585 tv->clk = devm_clk_get(dev, NULL);
586 if (IS_ERR(tv->clk)) {
587 dev_err(dev, "Couldn't get the TV encoder clock\n");
588 ret = PTR_ERR(tv->clk);
589 goto err_assert_reset;
590 }
591 clk_prepare_enable(tv->clk);
592
593 drm_encoder_helper_add(&tv->encoder,
594 &sun4i_tv_helper_funcs);
595 ret = drm_encoder_init(drm,
596 &tv->encoder,
597 &sun4i_tv_funcs,
598 DRM_MODE_ENCODER_TVDAC,
599 NULL);
600 if (ret) {
601 dev_err(dev, "Couldn't initialise the TV encoder\n");
602 goto err_disable_clk;
603 }
604
605 tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
606 dev->of_node);
607 if (!tv->encoder.possible_crtcs) {
608 ret = -EPROBE_DEFER;
609 goto err_disable_clk;
610 }
611
612 drm_connector_helper_add(&tv->connector,
613 &sun4i_tv_comp_connector_helper_funcs);
614 ret = drm_connector_init(drm, &tv->connector,
615 &sun4i_tv_comp_connector_funcs,
616 DRM_MODE_CONNECTOR_Composite);
617 if (ret) {
618 dev_err(dev,
619 "Couldn't initialise the Composite connector\n");
620 goto err_cleanup_connector;
621 }
622 tv->connector.interlace_allowed = true;
623
624 drm_connector_attach_encoder(&tv->connector, &tv->encoder);
625
626 return 0;
627
628err_cleanup_connector:
629 drm_encoder_cleanup(&tv->encoder);
630err_disable_clk:
631 clk_disable_unprepare(tv->clk);
632err_assert_reset:
633 reset_control_assert(tv->reset);
634 return ret;
635}
636
637static void sun4i_tv_unbind(struct device *dev, struct device *master,
638 void *data)
639{
640 struct sun4i_tv *tv = dev_get_drvdata(dev);
641
642 drm_connector_cleanup(&tv->connector);
643 drm_encoder_cleanup(&tv->encoder);
644 clk_disable_unprepare(tv->clk);
645}
646
647static const struct component_ops sun4i_tv_ops = {
648 .bind = sun4i_tv_bind,
649 .unbind = sun4i_tv_unbind,
650};
651
652static int sun4i_tv_probe(struct platform_device *pdev)
653{
654 return component_add(&pdev->dev, &sun4i_tv_ops);
655}
656
657static int sun4i_tv_remove(struct platform_device *pdev)
658{
659 component_del(&pdev->dev, &sun4i_tv_ops);
660
661 return 0;
662}
663
664static const struct of_device_id sun4i_tv_of_table[] = {
665 { .compatible = "allwinner,sun4i-a10-tv-encoder" },
666 { }
667};
668MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
669
670static struct platform_driver sun4i_tv_platform_driver = {
671 .probe = sun4i_tv_probe,
672 .remove = sun4i_tv_remove,
673 .driver = {
674 .name = "sun4i-tve",
675 .of_match_table = sun4i_tv_of_table,
676 },
677};
678module_platform_driver(sun4i_tv_platform_driver);
679
680MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
681MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
682MODULE_LICENSE("GPL");
683
