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15#include <linux/clk.h>
16#include <linux/device.h>
17#include <linux/dma-mapping.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/reset.h>
24
25#include <drm/drm_drv.h>
26#include <drm/drm_fb_cma_helper.h>
27#include <drm/drm_fb_helper.h>
28#include <uapi/drm/v3d_drm.h>
29
30#include "v3d_drv.h"
31#include "v3d_regs.h"
32
33#define DRIVER_NAME "v3d"
34#define DRIVER_DESC "Broadcom V3D graphics"
35#define DRIVER_DATE "20180419"
36#define DRIVER_MAJOR 1
37#define DRIVER_MINOR 0
38#define DRIVER_PATCHLEVEL 0
39
40#ifdef CONFIG_PM
41static int v3d_runtime_suspend(struct device *dev)
42{
43 struct drm_device *drm = dev_get_drvdata(dev);
44 struct v3d_dev *v3d = to_v3d_dev(drm);
45
46 v3d_irq_disable(v3d);
47
48 clk_disable_unprepare(v3d->clk);
49
50 return 0;
51}
52
53static int v3d_runtime_resume(struct device *dev)
54{
55 struct drm_device *drm = dev_get_drvdata(dev);
56 struct v3d_dev *v3d = to_v3d_dev(drm);
57 int ret;
58
59 ret = clk_prepare_enable(v3d->clk);
60 if (ret != 0)
61 return ret;
62
63
64
65 v3d_mmu_set_page_table(v3d);
66 v3d_irq_enable(v3d);
67
68 return 0;
69}
70#endif
71
72static const struct dev_pm_ops v3d_v3d_pm_ops = {
73 SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)
74};
75
76static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
77 struct drm_file *file_priv)
78{
79 struct v3d_dev *v3d = to_v3d_dev(dev);
80 struct drm_v3d_get_param *args = data;
81 int ret;
82 static const u32 reg_map[] = {
83 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
84 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
85 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
86 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
87 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
88 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
89 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
90 };
91
92 if (args->pad != 0)
93 return -EINVAL;
94
95
96
97
98
99 if (args->param < ARRAY_SIZE(reg_map) &&
100 (reg_map[args->param] ||
101 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
102 u32 offset = reg_map[args->param];
103
104 if (args->value != 0)
105 return -EINVAL;
106
107 ret = pm_runtime_get_sync(v3d->dev);
108 if (ret < 0)
109 return ret;
110 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
111 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
112 args->value = V3D_CORE_READ(0, offset);
113 } else {
114 args->value = V3D_READ(offset);
115 }
116 pm_runtime_mark_last_busy(v3d->dev);
117 pm_runtime_put_autosuspend(v3d->dev);
118 return 0;
119 }
120
121
122 switch (args->param) {
123 case DRM_V3D_PARAM_SUPPORTS_TFU:
124 args->value = 1;
125 return 0;
126 case DRM_V3D_PARAM_SUPPORTS_CSD:
127 args->value = v3d_has_csd(v3d);
128 return 0;
129 default:
130 DRM_DEBUG("Unknown parameter %d\n", args->param);
131 return -EINVAL;
132 }
133}
134
135static int
136v3d_open(struct drm_device *dev, struct drm_file *file)
137{
138 struct v3d_dev *v3d = to_v3d_dev(dev);
139 struct v3d_file_priv *v3d_priv;
140 struct drm_sched_rq *rq;
141 int i;
142
143 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
144 if (!v3d_priv)
145 return -ENOMEM;
146
147 v3d_priv->v3d = v3d;
148
149 for (i = 0; i < V3D_MAX_QUEUES; i++) {
150 rq = &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
151 drm_sched_entity_init(&v3d_priv->sched_entity[i], &rq, 1, NULL);
152 }
153
154 file->driver_priv = v3d_priv;
155
156 return 0;
157}
158
159static void
160v3d_postclose(struct drm_device *dev, struct drm_file *file)
161{
162 struct v3d_file_priv *v3d_priv = file->driver_priv;
163 enum v3d_queue q;
164
165 for (q = 0; q < V3D_MAX_QUEUES; q++) {
166 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
167 }
168
169 kfree(v3d_priv);
170}
171
172DEFINE_DRM_GEM_SHMEM_FOPS(v3d_drm_fops);
173
174
175
176
177
178
179
180static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
181 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
182 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
183 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
184 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
185 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
186 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
187 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
188 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
189};
190
191static struct drm_driver v3d_drm_driver = {
192 .driver_features = (DRIVER_GEM |
193 DRIVER_RENDER |
194 DRIVER_SYNCOBJ),
195
196 .open = v3d_open,
197 .postclose = v3d_postclose,
198
199#if defined(CONFIG_DEBUG_FS)
200 .debugfs_init = v3d_debugfs_init,
201#endif
202
203 .gem_create_object = v3d_create_object,
204 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
205 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
206 .gem_prime_import_sg_table = v3d_prime_import_sg_table,
207 .gem_prime_mmap = drm_gem_prime_mmap,
208
209 .ioctls = v3d_drm_ioctls,
210 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
211 .fops = &v3d_drm_fops,
212
213 .name = DRIVER_NAME,
214 .desc = DRIVER_DESC,
215 .date = DRIVER_DATE,
216 .major = DRIVER_MAJOR,
217 .minor = DRIVER_MINOR,
218 .patchlevel = DRIVER_PATCHLEVEL,
219};
220
221static const struct of_device_id v3d_of_match[] = {
222 { .compatible = "brcm,7268-v3d" },
223 { .compatible = "brcm,7278-v3d" },
224 {},
225};
226MODULE_DEVICE_TABLE(of, v3d_of_match);
227
228static int
229map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
230{
231 struct resource *res =
232 platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name);
233
234 *regs = devm_ioremap_resource(v3d->dev, res);
235 return PTR_ERR_OR_ZERO(*regs);
236}
237
238static int v3d_platform_drm_probe(struct platform_device *pdev)
239{
240 struct device *dev = &pdev->dev;
241 struct drm_device *drm;
242 struct v3d_dev *v3d;
243 int ret;
244 u32 mmu_debug;
245 u32 ident1;
246
247
248 v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
249 if (!v3d)
250 return -ENOMEM;
251 v3d->dev = dev;
252 v3d->pdev = pdev;
253 drm = &v3d->drm;
254
255 ret = map_regs(v3d, &v3d->hub_regs, "hub");
256 if (ret)
257 goto dev_free;
258
259 ret = map_regs(v3d, &v3d->core_regs[0], "core0");
260 if (ret)
261 goto dev_free;
262
263 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
264 dev->coherent_dma_mask =
265 DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
266 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
267
268 ident1 = V3D_READ(V3D_HUB_IDENT1);
269 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
270 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
271 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
272 WARN_ON(v3d->cores > 1);
273
274 v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
275 if (IS_ERR(v3d->reset)) {
276 ret = PTR_ERR(v3d->reset);
277
278 if (ret == -EPROBE_DEFER)
279 goto dev_free;
280
281 v3d->reset = NULL;
282 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
283 if (ret) {
284 dev_err(dev,
285 "Failed to get reset control or bridge regs\n");
286 goto dev_free;
287 }
288 }
289
290 if (v3d->ver < 41) {
291 ret = map_regs(v3d, &v3d->gca_regs, "gca");
292 if (ret)
293 goto dev_free;
294 }
295
296 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
297 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
298 if (!v3d->mmu_scratch) {
299 dev_err(dev, "Failed to allocate MMU scratch page\n");
300 ret = -ENOMEM;
301 goto dev_free;
302 }
303
304 pm_runtime_use_autosuspend(dev);
305 pm_runtime_set_autosuspend_delay(dev, 50);
306 pm_runtime_enable(dev);
307
308 ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev);
309 if (ret)
310 goto dma_free;
311
312 platform_set_drvdata(pdev, drm);
313 drm->dev_private = v3d;
314
315 ret = v3d_gem_init(drm);
316 if (ret)
317 goto dev_destroy;
318
319 ret = v3d_irq_init(v3d);
320 if (ret)
321 goto gem_destroy;
322
323 ret = drm_dev_register(drm, 0);
324 if (ret)
325 goto irq_disable;
326
327 return 0;
328
329irq_disable:
330 v3d_irq_disable(v3d);
331gem_destroy:
332 v3d_gem_destroy(drm);
333dev_destroy:
334 drm_dev_put(drm);
335dma_free:
336 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
337dev_free:
338 kfree(v3d);
339 return ret;
340}
341
342static int v3d_platform_drm_remove(struct platform_device *pdev)
343{
344 struct drm_device *drm = platform_get_drvdata(pdev);
345 struct v3d_dev *v3d = to_v3d_dev(drm);
346
347 drm_dev_unregister(drm);
348
349 v3d_gem_destroy(drm);
350
351 drm_dev_put(drm);
352
353 dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
354
355 return 0;
356}
357
358static struct platform_driver v3d_platform_driver = {
359 .probe = v3d_platform_drm_probe,
360 .remove = v3d_platform_drm_remove,
361 .driver = {
362 .name = "v3d",
363 .of_match_table = v3d_of_match,
364 },
365};
366
367static int __init v3d_drm_register(void)
368{
369 return platform_driver_register(&v3d_platform_driver);
370}
371
372static void __exit v3d_drm_unregister(void)
373{
374 platform_driver_unregister(&v3d_platform_driver);
375}
376
377module_init(v3d_drm_register);
378module_exit(v3d_drm_unregister);
379
380MODULE_ALIAS("platform:v3d-drm");
381MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
382MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
383MODULE_LICENSE("GPL v2");
384
