1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright 2016 Linaro Ltd. 4 * Copyright 2016 ZTE Corporation. 5 */ 6 7#ifndef __ZX_HDMI_REGS_H__ 8#define __ZX_HDMI_REGS_H__ 9 10#define FUNC_SEL 0x000b 11#define FUNC_HDMI_EN BIT(0) 12#define CLKPWD 0x000d 13#define CLKPWD_PDIDCK BIT(2) 14#define P2T_CTRL 0x0066 15#define P2T_DC_PKT_EN BIT(7) 16#define L1_INTR_STAT 0x007e 17#define L1_INTR_STAT_INTR1 BIT(0) 18#define INTR1_STAT 0x008f 19#define INTR1_MASK 0x0095 20#define INTR1_MONITOR_DETECT (BIT(5) | BIT(6)) 21#define ZX_DDC_ADDR 0x00ed 22#define ZX_DDC_SEGM 0x00ee 23#define ZX_DDC_OFFSET 0x00ef 24#define ZX_DDC_DIN_CNT1 0x00f0 25#define ZX_DDC_DIN_CNT2 0x00f1 26#define ZX_DDC_CMD 0x00f3 27#define DDC_CMD_MASK 0xf 28#define DDC_CMD_CLEAR_FIFO 0x9 29#define DDC_CMD_SEQUENTIAL_READ 0x2 30#define ZX_DDC_DATA 0x00f4 31#define ZX_DDC_DOUT_CNT 0x00f5 32#define DDC_DOUT_CNT_MASK 0x1f 33#define TEST_TXCTRL 0x00f7 34#define TEST_TXCTRL_HDMI_MODE BIT(1) 35#define HDMICTL4 0x0235 36#define TPI_HPD_RSEN 0x063b 37#define TPI_HPD_CONNECTION (BIT(1) | BIT(2)) 38#define TPI_INFO_FSEL 0x06bf 39#define FSEL_AVI 0 40#define FSEL_GBD 1 41#define FSEL_AUDIO 2 42#define FSEL_SPD 3 43#define FSEL_MPEG 4 44#define FSEL_VSIF 5 45#define TPI_INFO_B0 0x06c0 46#define TPI_INFO_EN 0x06df 47#define TPI_INFO_TRANS_EN BIT(7) 48#define TPI_INFO_TRANS_RPT BIT(6) 49#define TPI_DDC_MASTER_EN 0x06f8 50#define HW_DDC_MASTER BIT(7) 51#define N_SVAL1 0xa03 52#define N_SVAL2 0xa04 53#define N_SVAL3 0xa05 54#define AUD_EN 0xa13 55#define AUD_IN_EN BIT(0) 56#define AUD_MODE 0xa14 57#define SPDIF_EN BIT(1) 58#define TPI_AUD_CONFIG 0xa62 59#define SPDIF_SAMPLE_SIZE_SHIFT 6 60#define SPDIF_SAMPLE_SIZE_MASK (0x3 << SPDIF_SAMPLE_SIZE_SHIFT) 61#define SPDIF_SAMPLE_SIZE_16BIT (0x1 << SPDIF_SAMPLE_SIZE_SHIFT) 62#define SPDIF_SAMPLE_SIZE_20BIT (0x2 << SPDIF_SAMPLE_SIZE_SHIFT) 63#define SPDIF_SAMPLE_SIZE_24BIT (0x3 << SPDIF_SAMPLE_SIZE_SHIFT) 64#define TPI_AUD_MUTE BIT(4) 65 66#endif /* __ZX_HDMI_REGS_H__ */ 67