LXR linux/drivers/i2c/busses/i2c-sh

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * SuperH Mobile I2C Controller
   4 *
   5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
   6 * Copyright (C) 2008 Magnus Damm
   7 *
   8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
   9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
  10 */
  11
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/dmaengine.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/err.h>
  17#include <linux/i2c.h>
  18#include <linux/init.h>
  19#include <linux/interrupt.h>
  20#include <linux/io.h>
  21#include <linux/kernel.h>
  22#include <linux/module.h>
  23#include <linux/of_device.h>
  24#include <linux/platform_device.h>
  25#include <linux/pm_runtime.h>
  26#include <linux/slab.h>
  27
  28/* Transmit operation:                                                      */
  29/*                                                                          */
  30/* 0 byte transmit                                                          */
  31/* BUS:     S     A8     ACK   P(*)                                         */
  32/* IRQ:       DTE   WAIT                                                    */
  33/* ICIC:                                                                    */
  34/* ICCR: 0x94       0x90                                                    */
  35/* ICDR:      A8                                                            */
  36/*                                                                          */
  37/* 1 byte transmit                                                          */
  38/* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  39/* IRQ:       DTE   WAIT         WAIT                                       */
  40/* ICIC:      -DTE                                                          */
  41/* ICCR: 0x94                    0x90                                       */
  42/* ICDR:      A8    D8(1)                                                   */
  43/*                                                                          */
  44/* 2 byte transmit                                                          */
  45/* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  46/* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  47/* ICIC:      -DTE                                                          */
  48/* ICCR: 0x94                                  0x90                         */
  49/* ICDR:      A8    D8(1)        D8(2)                                      */
  50/*                                                                          */
  51/* 3 bytes or more, +---------+ gets repeated                               */
  52/*                                                                          */
  53/*                                                                          */
  54/* Receive operation:                                                       */
  55/*                                                                          */
  56/* 0 byte receive - not supported since slave may hold SDA low              */
  57/*                                                                          */
  58/* 1 byte receive       [TX] | [RX]                                         */
  59/* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  60/* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  61/* ICIC:      -DTE           |   +DTE                                       */
  62/* ICCR: 0x94       0x81     |   0xc0                                       */
  63/* ICDR:      A8             |            D8(1)                             */
  64/*                                                                          */
  65/* 2 byte receive        [TX]| [RX]                                         */
  66/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  67/* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  68/* ICIC:      -DTE           |                 +DTE                         */
  69/* ICCR: 0x94       0x81     |                 0xc0                         */
  70/* ICDR:      A8             |                 D8(1)    D8(2)               */
  71/*                                                                          */
  72/* 3 byte receive       [TX] | [RX]                                     (*) */
  73/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  74/* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  75/* ICIC:      -DTE           |                              +DTE            */
  76/* ICCR: 0x94       0x81     |                              0xc0            */
  77/* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  78/*                                                                          */
  79/* 4 bytes or more, this part is repeated    +---------+                    */
  80/*                                                                          */
  81/*                                                                          */
  82/* Interrupt order and BUSY flag                                            */
  83/*     ___                                                 _                */
  84/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  85/* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  86/*                                                                          */
  87/*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  88/*                                           ___                            */
  89/* WAIT IRQ ________________________________/   \___________                */
  90/* TACK IRQ ____________________________________/   \_______                */
  91/* DTE  IRQ __________________________________________/   \_                */
  92/* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
  93/*         _______________________________________________                  */
  94/* BUSY __/                                               \_                */
  95/*                                                                          */
  96/* (*) The STOP condition is only sent by the master at the end of the last */
  97/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
  98/* only cleared after the STOP condition, so, between messages we have to   */
  99/* poll for the DTE bit.                                                    */
 100/*                                                                          */
 101
 102enum sh_mobile_i2c_op {
 103        OP_START = 0,
 104        OP_TX_FIRST,
 105        OP_TX,
 106        OP_TX_STOP,
 107        OP_TX_TO_RX,
 108        OP_RX,
 109        OP_RX_STOP,
 110        OP_RX_STOP_DATA,
 111};
 112
 113struct sh_mobile_i2c_data {
 114        struct device *dev;
 115        void __iomem *reg;
 116        struct i2c_adapter adap;
 117        unsigned long bus_speed;
 118        unsigned int clks_per_count;
 119        struct clk *clk;
 120        u_int8_t icic;
 121        u_int8_t flags;
 122        u_int16_t iccl;
 123        u_int16_t icch;
 124
 125        spinlock_t lock;
 126        wait_queue_head_t wait;
 127        struct i2c_msg *msg;
 128        int pos;
 129        int sr;
 130        bool send_stop;
 131        bool stop_after_dma;
 132
 133        struct resource *res;
 134        struct dma_chan *dma_tx;
 135        struct dma_chan *dma_rx;
 136        struct scatterlist sg;
 137        enum dma_data_direction dma_direction;
 138        u8 *dma_buf;
 139};
 140
 141struct sh_mobile_dt_config {
 142        int clks_per_count;
 143        int (*setup)(struct sh_mobile_i2c_data *pd);
 144};
 145
 146#define IIC_FLAG_HAS_ICIC67     (1 << 0)
 147
 148#define STANDARD_MODE           100000
 149#define FAST_MODE               400000
 150
 151/* Register offsets */
 152#define ICDR                    0x00
 153#define ICCR                    0x04
 154#define ICSR                    0x08
 155#define ICIC                    0x0c
 156#define ICCL                    0x10
 157#define ICCH                    0x14
 158#define ICSTART                 0x70
 159
 160/* Register bits */
 161#define ICCR_ICE                0x80
 162#define ICCR_RACK               0x40
 163#define ICCR_TRS                0x10
 164#define ICCR_BBSY               0x04
 165#define ICCR_SCP                0x01
 166
 167#define ICSR_SCLM               0x80
 168#define ICSR_SDAM               0x40
 169#define SW_DONE                 0x20
 170#define ICSR_BUSY               0x10
 171#define ICSR_AL                 0x08
 172#define ICSR_TACK               0x04
 173#define ICSR_WAIT               0x02
 174#define ICSR_DTE                0x01
 175
 176#define ICIC_ICCLB8             0x80
 177#define ICIC_ICCHB8             0x40
 178#define ICIC_TDMAE              0x20
 179#define ICIC_RDMAE              0x10
 180#define ICIC_ALE                0x08
 181#define ICIC_TACKE              0x04
 182#define ICIC_WAITE              0x02
 183#define ICIC_DTEE               0x01
 184
 185#define ICSTART_ICSTART         0x10
 186
 187static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 188{
 189        if (offs == ICIC)
 190                data |= pd->icic;
 191
 192        iowrite8(data, pd->reg + offs);
 193}
 194
 195static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 196{
 197        return ioread8(pd->reg + offs);
 198}
 199
 200static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 201                        unsigned char set, unsigned char clr)
 202{
 203        iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 204}
 205
 206static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 207{
 208        /*
 209         * Conditional expression:
 210         *   ICCL >= COUNT_CLK * (tLOW + tf)
 211         *
 212         * SH-Mobile IIC hardware starts counting the LOW period of
 213         * the SCL signal (tLOW) as soon as it pulls the SCL line.
 214         * In order to meet the tLOW timing spec, we need to take into
 215         * account the fall time of SCL signal (tf).  Default tf value
 216         * should be 0.3 us, for safety.
 217         */
 218        return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 219}
 220
 221static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 222{
 223        /*
 224         * Conditional expression:
 225         *   ICCH >= COUNT_CLK * (tHIGH + tf)
 226         *
 227         * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 228         * and can ignore it.  SH-Mobile IIC controller starts counting
 229         * the HIGH period of the SCL signal (tHIGH) after the SCL input
 230         * voltage increases at VIH.
 231         *
 232         * Afterward it turned out calculating ICCH using only tHIGH spec
 233         * will result in violation of the tHD;STA timing spec.  We need
 234         * to take into account the fall time of SDA signal (tf) at START
 235         * condition, in order to meet both tHIGH and tHD;STA specs.
 236         */
 237        return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 238}
 239
 240static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
 241{
 242        u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 243
 244        if (pd->iccl > max_val || pd->icch > max_val) {
 245                dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 246                        pd->iccl, pd->icch);
 247                return -EINVAL;
 248        }
 249
 250        /* one more bit of ICCL in ICIC */
 251        if (pd->iccl & 0x100)
 252                pd->icic |= ICIC_ICCLB8;
 253        else
 254                pd->icic &= ~ICIC_ICCLB8;
 255
 256        /* one more bit of ICCH in ICIC */
 257        if (pd->icch & 0x100)
 258                pd->icic |= ICIC_ICCHB8;
 259        else
 260                pd->icic &= ~ICIC_ICCHB8;
 261
 262        dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 263        return 0;
 264}
 265
 266static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 267{
 268        unsigned long i2c_clk_khz;
 269        u32 tHIGH, tLOW, tf;
 270
 271        i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
 272
 273        if (pd->bus_speed == STANDARD_MODE) {
 274                tLOW    = 47;   /* tLOW = 4.7 us */
 275                tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 276                tf      = 3;    /* tf = 0.3 us */
 277        } else if (pd->bus_speed == FAST_MODE) {
 278                tLOW    = 13;   /* tLOW = 1.3 us */
 279                tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 280                tf      = 3;    /* tf = 0.3 us */
 281        } else {
 282                dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 283                        pd->bus_speed);
 284                return -EINVAL;
 285        }
 286
 287        pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 288        pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 289
 290        return sh_mobile_i2c_check_timing(pd);
 291}
 292
 293static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
 294{
 295        unsigned long clks_per_cycle;
 296
 297        /* L = 5, H = 4, L + H = 9 */
 298        clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
 299        pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
 300        pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
 301
 302        return sh_mobile_i2c_check_timing(pd);
 303}
 304
 305static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op)
 306{
 307        unsigned char ret = 0;
 308        unsigned long flags;
 309
 310        dev_dbg(pd->dev, "op %d\n", op);
 311
 312        spin_lock_irqsave(&pd->lock, flags);
 313
 314        switch (op) {
 315        case OP_START: /* issue start and trigger DTE interrupt */
 316                iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 317                break;
 318        case OP_TX_FIRST: /* disable DTE interrupt and write client address */
 319                iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 320                iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg));
 321                break;
 322        case OP_TX: /* write data */
 323                iic_wr(pd, ICDR, pd->msg->buf[pd->pos]);
 324                break;
 325        case OP_TX_STOP: /* issue a stop (or rep_start) */
 326                iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 327                                               : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 328                break;
 329        case OP_TX_TO_RX: /* select read mode */
 330                iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 331                break;
 332        case OP_RX: /* just read data */
 333                ret = iic_rd(pd, ICDR);
 334                break;
 335        case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 336                iic_wr(pd, ICIC,
 337                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 338                iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 339                break;
 340        case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 341                iic_wr(pd, ICIC,
 342                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 343                ret = iic_rd(pd, ICDR);
 344                iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 345                break;
 346        }
 347
 348        spin_unlock_irqrestore(&pd->lock, flags);
 349
 350        dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 351        return ret;
 352}
 353
 354static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 355{
 356        if (pd->pos == pd->msg->len) {
 357                i2c_op(pd, OP_TX_STOP);
 358                return 1;
 359        }
 360
 361        if (pd->pos == -1)
 362                i2c_op(pd, OP_TX_FIRST);
 363        else
 364                i2c_op(pd, OP_TX);
 365
 366        pd->pos++;
 367        return 0;
 368}
 369
 370static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 371{
 372        unsigned char data;
 373        int real_pos;
 374
 375        /* switch from TX (address) to RX (data) adds two interrupts */
 376        real_pos = pd->pos - 2;
 377
 378        if (pd->pos == -1) {
 379                i2c_op(pd, OP_TX_FIRST);
 380        } else if (pd->pos == 0) {
 381                i2c_op(pd, OP_TX_TO_RX);
 382        } else if (pd->pos == pd->msg->len) {
 383                if (pd->stop_after_dma) {
 384                        /* Simulate PIO end condition after DMA transfer */
 385                        i2c_op(pd, OP_RX_STOP);
 386                        pd->pos++;
 387                        goto done;
 388                }
 389
 390                if (real_pos < 0)
 391                        i2c_op(pd, OP_RX_STOP);
 392                else
 393                        data = i2c_op(pd, OP_RX_STOP_DATA);
 394        } else if (real_pos >= 0) {
 395                data = i2c_op(pd, OP_RX);
 396        }
 397
 398        if (real_pos >= 0)
 399                pd->msg->buf[real_pos] = data;
 400 done:
 401        pd->pos++;
 402        return pd->pos == (pd->msg->len + 2);
 403}
 404
 405static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 406{
 407        struct sh_mobile_i2c_data *pd = dev_id;
 408        unsigned char sr;
 409        int wakeup = 0;
 410
 411        sr = iic_rd(pd, ICSR);
 412        pd->sr |= sr; /* remember state */
 413
 414        dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 415               (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 416               pd->pos, pd->msg->len);
 417
 418        /* Kick off TxDMA after preface was done */
 419        if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 420                iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 421        else if (sr & (ICSR_AL | ICSR_TACK))
 422                /* don't interrupt transaction - continue to issue stop */
 423                iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 424        else if (pd->msg->flags & I2C_M_RD)
 425                wakeup = sh_mobile_i2c_isr_rx(pd);
 426        else
 427                wakeup = sh_mobile_i2c_isr_tx(pd);
 428
 429        /* Kick off RxDMA after preface was done */
 430        if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 431                iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 432
 433        if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 434                iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 435
 436        if (wakeup) {
 437                pd->sr |= SW_DONE;
 438                wake_up(&pd->wait);
 439        }
 440
 441        /* defeat write posting to avoid spurious WAIT interrupts */
 442        iic_rd(pd, ICSR);
 443
 444        return IRQ_HANDLED;
 445}
 446
 447static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 448{
 449        struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 450                                ? pd->dma_rx : pd->dma_tx;
 451
 452        dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 453                         pd->msg->len, pd->dma_direction);
 454
 455        pd->dma_direction = DMA_NONE;
 456}
 457
 458static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 459{
 460        if (pd->dma_direction == DMA_NONE)
 461                return;
 462        else if (pd->dma_direction == DMA_FROM_DEVICE)
 463                dmaengine_terminate_all(pd->dma_rx);
 464        else if (pd->dma_direction == DMA_TO_DEVICE)
 465                dmaengine_terminate_all(pd->dma_tx);
 466
 467        sh_mobile_i2c_dma_unmap(pd);
 468}
 469
 470static void sh_mobile_i2c_dma_callback(void *data)
 471{
 472        struct sh_mobile_i2c_data *pd = data;
 473
 474        sh_mobile_i2c_dma_unmap(pd);
 475        pd->pos = pd->msg->len;
 476        pd->stop_after_dma = true;
 477
 478        iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 479}
 480
 481static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 482                                enum dma_transfer_direction dir, dma_addr_t port_addr)
 483{
 484        struct dma_chan *chan;
 485        struct dma_slave_config cfg;
 486        char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 487        int ret;
 488
 489        chan = dma_request_slave_channel_reason(dev, chan_name);
 490        if (IS_ERR(chan)) {
 491                dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
 492                        PTR_ERR(chan));
 493                return chan;
 494        }
 495
 496        memset(&cfg, 0, sizeof(cfg));
 497        cfg.direction = dir;
 498        if (dir == DMA_MEM_TO_DEV) {
 499                cfg.dst_addr = port_addr;
 500                cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 501        } else {
 502                cfg.src_addr = port_addr;
 503                cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 504        }
 505
 506        ret = dmaengine_slave_config(chan, &cfg);
 507        if (ret) {
 508                dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 509                dma_release_channel(chan);
 510                return ERR_PTR(ret);
 511        }
 512
 513        dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 514        return chan;
 515}
 516
 517static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 518{
 519        bool read = pd->msg->flags & I2C_M_RD;
 520        enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 521        struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 522        struct dma_async_tx_descriptor *txdesc;
 523        dma_addr_t dma_addr;
 524        dma_cookie_t cookie;
 525
 526        if (PTR_ERR(chan) == -EPROBE_DEFER) {
 527                if (read)
 528                        chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 529                                                                           pd->res->start + ICDR);
 530                else
 531                        chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 532                                                                           pd->res->start + ICDR);
 533        }
 534
 535        if (IS_ERR(chan))
 536                return;
 537
 538        dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
 539        if (dma_mapping_error(chan->device->dev, dma_addr)) {
 540                dev_dbg(pd->dev, "dma map failed, using PIO\n");
 541                return;
 542        }
 543
 544        sg_dma_len(&pd->sg) = pd->msg->len;
 545        sg_dma_address(&pd->sg) = dma_addr;
 546
 547        pd->dma_direction = dir;
 548
 549        txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 550                                         read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 551                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 552        if (!txdesc) {
 553                dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 554                sh_mobile_i2c_cleanup_dma(pd);
 555                return;
 556        }
 557
 558        txdesc->callback = sh_mobile_i2c_dma_callback;
 559        txdesc->callback_param = pd;
 560
 561        cookie = dmaengine_submit(txdesc);
 562        if (dma_submit_error(cookie)) {
 563                dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 564                sh_mobile_i2c_cleanup_dma(pd);
 565                return;
 566        }
 567
 568        dma_async_issue_pending(chan);
 569}
 570
 571static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 572                     bool do_init)
 573{
 574        if (do_init) {
 575                /* Initialize channel registers */
 576                iic_wr(pd, ICCR, ICCR_SCP);
 577
 578                /* Enable channel and configure rx ack */
 579                iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 580
 581                /* Set the clock */
 582                iic_wr(pd, ICCL, pd->iccl & 0xff);
 583                iic_wr(pd, ICCH, pd->icch & 0xff);
 584        }
 585
 586        pd->msg = usr_msg;
 587        pd->pos = -1;
 588        pd->sr = 0;
 589
 590        pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
 591        if (pd->dma_buf)
 592                sh_mobile_i2c_xfer_dma(pd);
 593
 594        /* Enable all interrupts to begin with */
 595        iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 596}
 597
 598static int poll_dte(struct sh_mobile_i2c_data *pd)
 599{
 600        int i;
 601
 602        for (i = 1000; i; i--) {
 603                u_int8_t val = iic_rd(pd, ICSR);
 604
 605                if (val & ICSR_DTE)
 606                        break;
 607
 608                if (val & ICSR_TACK)
 609                        return -ENXIO;
 610
 611                udelay(10);
 612        }
 613
 614        return i ? 0 : -ETIMEDOUT;
 615}
 616
 617static int poll_busy(struct sh_mobile_i2c_data *pd)
 618{
 619        int i;
 620
 621        for (i = 1000; i; i--) {
 622                u_int8_t val = iic_rd(pd, ICSR);
 623
 624                dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 625
 626                /* the interrupt handler may wake us up before the
 627                 * transfer is finished, so poll the hardware
 628                 * until we're done.
 629                 */
 630                if (!(val & ICSR_BUSY)) {
 631                        /* handle missing acknowledge and arbitration lost */
 632                        val |= pd->sr;
 633                        if (val & ICSR_TACK)
 634                                return -ENXIO;
 635                        if (val & ICSR_AL)
 636                                return -EAGAIN;
 637                        break;
 638                }
 639
 640                udelay(10);
 641        }
 642
 643        return i ? 0 : -ETIMEDOUT;
 644}
 645
 646static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 647                              struct i2c_msg *msgs,
 648                              int num)
 649{
 650        struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 651        struct i2c_msg  *msg;
 652        int err = 0;
 653        int i;
 654        long timeout;
 655
 656        /* Wake up device and enable clock */
 657        pm_runtime_get_sync(pd->dev);
 658
 659        /* Process all messages */
 660        for (i = 0; i < num; i++) {
 661                bool do_start = pd->send_stop || !i;
 662                msg = &msgs[i];
 663                pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 664                pd->stop_after_dma = false;
 665
 666                start_ch(pd, msg, do_start);
 667
 668                if (do_start)
 669                        i2c_op(pd, OP_START);
 670
 671                /* The interrupt handler takes care of the rest... */
 672                timeout = wait_event_timeout(pd->wait,
 673                                       pd->sr & (ICSR_TACK | SW_DONE),
 674                                       adapter->timeout);
 675
 676                /* 'stop_after_dma' tells if DMA transfer was complete */
 677                i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma);
 678
 679                if (!timeout) {
 680                        dev_err(pd->dev, "Transfer request timed out\n");
 681                        if (pd->dma_direction != DMA_NONE)
 682                                sh_mobile_i2c_cleanup_dma(pd);
 683
 684                        err = -ETIMEDOUT;
 685                        break;
 686                }
 687
 688                if (pd->send_stop)
 689                        err = poll_busy(pd);
 690                else
 691                        err = poll_dte(pd);
 692                if (err < 0)
 693                        break;
 694        }
 695
 696        /* Disable channel */
 697        iic_wr(pd, ICCR, ICCR_SCP);
 698
 699        /* Disable clock and mark device as idle */
 700        pm_runtime_put_sync(pd->dev);
 701
 702        return err ?: num;
 703}
 704
 705static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 706{
 707        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 708}
 709
 710static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
 711        .functionality  = sh_mobile_i2c_func,
 712        .master_xfer    = sh_mobile_i2c_xfer,
 713};
 714
 715static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
 716        .flags = I2C_AQ_NO_ZERO_LEN_READ,
 717};
 718
 719/*
 720 * r8a7740 has an errata regarding I2C I/O pad reset needing this workaround.
 721 */
 722static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
 723{
 724        iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 725        iic_rd(pd, ICCR); /* dummy read */
 726
 727        iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
 728        iic_rd(pd, ICSTART); /* dummy read */
 729
 730        udelay(10);
 731
 732        iic_wr(pd, ICCR, ICCR_SCP);
 733        iic_wr(pd, ICSTART, 0);
 734
 735        udelay(10);
 736
 737        iic_wr(pd, ICCR, ICCR_TRS);
 738        udelay(10);
 739        iic_wr(pd, ICCR, 0);
 740        udelay(10);
 741        iic_wr(pd, ICCR, ICCR_TRS);
 742        udelay(10);
 743
 744        return sh_mobile_i2c_init(pd);
 745}
 746
 747static const struct sh_mobile_dt_config default_dt_config = {
 748        .clks_per_count = 1,
 749        .setup = sh_mobile_i2c_init,
 750};
 751
 752static const struct sh_mobile_dt_config fast_clock_dt_config = {
 753        .clks_per_count = 2,
 754        .setup = sh_mobile_i2c_init,
 755};
 756
 757static const struct sh_mobile_dt_config v2_freq_calc_dt_config = {
 758        .clks_per_count = 2,
 759        .setup = sh_mobile_i2c_v2_init,
 760};
 761
 762static const struct sh_mobile_dt_config r8a7740_dt_config = {
 763        .clks_per_count = 1,
 764        .setup = sh_mobile_i2c_r8a7740_workaround,
 765};
 766
 767static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 768        { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 769        { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
 770        { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config },
 771        { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
 772        { .compatible = "renesas,iic-r8a7791", .data = &v2_freq_calc_dt_config },
 773        { .compatible = "renesas,iic-r8a7792", .data = &v2_freq_calc_dt_config },
 774        { .compatible = "renesas,iic-r8a7793", .data = &v2_freq_calc_dt_config },
 775        { .compatible = "renesas,iic-r8a7794", .data = &v2_freq_calc_dt_config },
 776        { .compatible = "renesas,iic-r8a7795", .data = &v2_freq_calc_dt_config },
 777        { .compatible = "renesas,iic-r8a77990", .data = &v2_freq_calc_dt_config },
 778        { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 779        { .compatible = "renesas,rcar-gen2-iic", .data = &v2_freq_calc_dt_config },
 780        { .compatible = "renesas,rcar-gen3-iic", .data = &v2_freq_calc_dt_config },
 781        { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 782        {},
 783};
 784MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 785
 786static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 787{
 788        if (!IS_ERR(pd->dma_tx)) {
 789                dma_release_channel(pd->dma_tx);
 790                pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 791        }
 792
 793        if (!IS_ERR(pd->dma_rx)) {
 794                dma_release_channel(pd->dma_rx);
 795                pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 796        }
 797}
 798
 799static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 800{
 801        struct resource *res;
 802        resource_size_t n;
 803        int k = 0, ret;
 804
 805        while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 806                for (n = res->start; n <= res->end; n++) {
 807                        ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 808                                          0, dev_name(&dev->dev), pd);
 809                        if (ret) {
 810                                dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 811                                return ret;
 812                        }
 813                }
 814                k++;
 815        }
 816
 817        return k > 0 ? 0 : -ENOENT;
 818}
 819
 820static int sh_mobile_i2c_probe(struct platform_device *dev)
 821{
 822        struct sh_mobile_i2c_data *pd;
 823        struct i2c_adapter *adap;
 824        struct resource *res;
 825        const struct sh_mobile_dt_config *config;
 826        int ret;
 827        u32 bus_speed;
 828
 829        pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 830        if (!pd)
 831                return -ENOMEM;
 832
 833        pd->clk = devm_clk_get(&dev->dev, NULL);
 834        if (IS_ERR(pd->clk)) {
 835                dev_err(&dev->dev, "cannot get clock\n");
 836                return PTR_ERR(pd->clk);
 837        }
 838
 839        ret = sh_mobile_i2c_hook_irqs(dev, pd);
 840        if (ret)
 841                return ret;
 842
 843        pd->dev = &dev->dev;
 844        platform_set_drvdata(dev, pd);
 845
 846        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 847
 848        pd->res = res;
 849        pd->reg = devm_ioremap_resource(&dev->dev, res);
 850        if (IS_ERR(pd->reg))
 851                return PTR_ERR(pd->reg);
 852
 853        ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 854        pd->bus_speed = (ret || !bus_speed) ? STANDARD_MODE : bus_speed;
 855        pd->clks_per_count = 1;
 856
 857        /* Newer variants come with two new bits in ICIC */
 858        if (resource_size(res) > 0x17)
 859                pd->flags |= IIC_FLAG_HAS_ICIC67;
 860
 861        pm_runtime_enable(&dev->dev);
 862        pm_runtime_get_sync(&dev->dev);
 863
 864        config = of_device_get_match_data(&dev->dev);
 865        if (config) {
 866                pd->clks_per_count = config->clks_per_count;
 867                ret = config->setup(pd);
 868        } else {
 869                ret = sh_mobile_i2c_init(pd);
 870        }
 871
 872        pm_runtime_put_sync(&dev->dev);
 873        if (ret)
 874                return ret;
 875
 876        /* Init DMA */
 877        sg_init_table(&pd->sg, 1);
 878        pd->dma_direction = DMA_NONE;
 879        pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 880
 881        /* setup the private data */
 882        adap = &pd->adap;
 883        i2c_set_adapdata(adap, pd);
 884
 885        adap->owner = THIS_MODULE;
 886        adap->algo = &sh_mobile_i2c_algorithm;
 887        adap->quirks = &sh_mobile_i2c_quirks;
 888        adap->dev.parent = &dev->dev;
 889        adap->retries = 5;
 890        adap->nr = dev->id;
 891        adap->dev.of_node = dev->dev.of_node;
 892
 893        strlcpy(adap->name, dev->name, sizeof(adap->name));
 894
 895        spin_lock_init(&pd->lock);
 896        init_waitqueue_head(&pd->wait);
 897
 898        ret = i2c_add_numbered_adapter(adap);
 899        if (ret < 0) {
 900                sh_mobile_i2c_release_dma(pd);
 901                return ret;
 902        }
 903
 904        dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 905
 906        return 0;
 907}
 908
 909static int sh_mobile_i2c_remove(struct platform_device *dev)
 910{
 911        struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 912
 913        i2c_del_adapter(&pd->adap);
 914        sh_mobile_i2c_release_dma(pd);
 915        pm_runtime_disable(&dev->dev);
 916        return 0;
 917}
 918
 919static struct platform_driver sh_mobile_i2c_driver = {
 920        .driver         = {
 921                .name           = "i2c-sh_mobile",
 922                .of_match_table = sh_mobile_i2c_dt_ids,
 923        },
 924        .probe          = sh_mobile_i2c_probe,
 925        .remove         = sh_mobile_i2c_remove,
 926};
 927
 928static int __init sh_mobile_i2c_adap_init(void)
 929{
 930        return platform_driver_register(&sh_mobile_i2c_driver);
 931}
 932subsys_initcall(sh_mobile_i2c_adap_init);
 933
 934static void __exit sh_mobile_i2c_adap_exit(void)
 935{
 936        platform_driver_unregister(&sh_mobile_i2c_driver);
 937}
 938module_exit(sh_mobile_i2c_adap_exit);
 939
 940MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
 941MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
 942MODULE_LICENSE("GPL v2");
 943MODULE_ALIAS("platform:i2c-sh_mobile");
 944