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34static const char version[] =
35"atp.c:v1.09=ac 2002/10/01 Donald Becker <becker@scyld.com>\n";
36
37
38
39
40static int debug = 1;
41#define net_debug debug
42
43
44static int max_interrupt_work = 15;
45
46#define NUM_UNITS 2
47
48static int io[NUM_UNITS];
49static int irq[NUM_UNITS];
50static int xcvr[NUM_UNITS];
51
52
53
54
55#define TX_TIMEOUT (400*HZ/1000)
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125#include <linux/kernel.h>
126#include <linux/module.h>
127#include <linux/types.h>
128#include <linux/fcntl.h>
129#include <linux/interrupt.h>
130#include <linux/ioport.h>
131#include <linux/in.h>
132#include <linux/string.h>
133#include <linux/errno.h>
134#include <linux/init.h>
135#include <linux/crc32.h>
136#include <linux/netdevice.h>
137#include <linux/etherdevice.h>
138#include <linux/skbuff.h>
139#include <linux/spinlock.h>
140#include <linux/delay.h>
141#include <linux/bitops.h>
142
143#include <asm/io.h>
144#include <asm/dma.h>
145
146#include "atp.h"
147
148MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
149MODULE_DESCRIPTION("RealTek RTL8002/8012 parallel port Ethernet driver");
150MODULE_LICENSE("GPL");
151
152module_param(max_interrupt_work, int, 0);
153module_param(debug, int, 0);
154module_param_hw_array(io, int, ioport, NULL, 0);
155module_param_hw_array(irq, int, irq, NULL, 0);
156module_param_array(xcvr, int, NULL, 0);
157MODULE_PARM_DESC(max_interrupt_work, "ATP maximum events handled per interrupt");
158MODULE_PARM_DESC(debug, "ATP debug level (0-7)");
159MODULE_PARM_DESC(io, "ATP I/O base address(es)");
160MODULE_PARM_DESC(irq, "ATP IRQ number(s)");
161MODULE_PARM_DESC(xcvr, "ATP transceiver(s) (0=internal, 1=external)");
162
163
164#define ETHERCARD_TOTAL_SIZE 3
165
166
167static char mux_8012[] = { 0xff, 0xf7, 0xff, 0xfb, 0xf3, 0xfb, 0xff, 0xf7,};
168
169struct net_local {
170 spinlock_t lock;
171 struct net_device *next_module;
172 struct timer_list timer;
173 struct net_device *dev;
174 unsigned long last_rx_time;
175 int saved_tx_size;
176 unsigned int tx_unit_busy:1;
177 unsigned char re_tx,
178 addr_mode,
179 pac_cnt_in_tx_buf;
180};
181
182
183
184
185#define TIMED_CHECKER (HZ/4)
186#ifdef TIMED_CHECKER
187#include <linux/timer.h>
188static void atp_timed_checker(struct timer_list *t);
189#endif
190
191
192
193static int atp_probe1(long ioaddr);
194static void get_node_ID(struct net_device *dev);
195static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
196static int net_open(struct net_device *dev);
197static void hardware_init(struct net_device *dev);
198static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
199static void trigger_send(long ioaddr, int length);
200static netdev_tx_t atp_send_packet(struct sk_buff *skb,
201 struct net_device *dev);
202static irqreturn_t atp_interrupt(int irq, void *dev_id);
203static void net_rx(struct net_device *dev);
204static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
205static int net_close(struct net_device *dev);
206static void set_rx_mode(struct net_device *dev);
207static void tx_timeout(struct net_device *dev);
208
209
210
211static struct net_device *root_atp_dev;
212
213
214
215
216
217
218
219
220
221static int __init atp_init(void)
222{
223 int *port, ports[] = {0x378, 0x278, 0x3bc, 0};
224 int base_addr = io[0];
225
226 if (base_addr > 0x1ff)
227 return atp_probe1(base_addr);
228 else if (base_addr == 1)
229 return -ENXIO;
230
231 for (port = ports; *port; port++) {
232 long ioaddr = *port;
233 outb(0x57, ioaddr + PAR_DATA);
234 if (inb(ioaddr + PAR_DATA) != 0x57)
235 continue;
236 if (atp_probe1(ioaddr) == 0)
237 return 0;
238 }
239
240 return -ENODEV;
241}
242
243static const struct net_device_ops atp_netdev_ops = {
244 .ndo_open = net_open,
245 .ndo_stop = net_close,
246 .ndo_start_xmit = atp_send_packet,
247 .ndo_set_rx_mode = set_rx_mode,
248 .ndo_tx_timeout = tx_timeout,
249 .ndo_set_mac_address = eth_mac_addr,
250 .ndo_validate_addr = eth_validate_addr,
251};
252
253static int __init atp_probe1(long ioaddr)
254{
255 struct net_device *dev = NULL;
256 struct net_local *lp;
257 int saved_ctrl_reg, status, i;
258 int res;
259
260 outb(0xff, ioaddr + PAR_DATA);
261
262
263 saved_ctrl_reg = inb(ioaddr + PAR_CONTROL);
264 if (net_debug > 3)
265 printk("atp: Control register was %#2.2x.\n", saved_ctrl_reg);
266
267 outb(0x04, ioaddr + PAR_CONTROL);
268#ifndef final_version
269 if (net_debug > 3) {
270
271 for (i = 0; i < 8; i++)
272 outb(mux_8012[i], ioaddr + PAR_DATA);
273 write_reg(ioaddr, MODSEL, 0x00);
274 printk("atp: Registers are ");
275 for (i = 0; i < 32; i++)
276 printk(" %2.2x", read_nibble(ioaddr, i));
277 printk(".\n");
278 }
279#endif
280
281 for (i = 0; i < 8; i++)
282 outb(mux_8012[i], ioaddr + PAR_DATA);
283 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
284
285 status = read_nibble(ioaddr, CMR1);
286
287 if (net_debug > 3) {
288 printk(KERN_DEBUG "atp: Status nibble was %#2.2x..", status);
289 for (i = 0; i < 32; i++)
290 printk(" %2.2x", read_nibble(ioaddr, i));
291 printk("\n");
292 }
293
294 if ((status & 0x78) != 0x08) {
295
296 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
297 return -ENODEV;
298 }
299 status = read_nibble(ioaddr, CMR2_h);
300 if ((status & 0x78) != 0x10) {
301 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
302 return -ENODEV;
303 }
304
305 dev = alloc_etherdev(sizeof(struct net_local));
306 if (!dev)
307 return -ENOMEM;
308
309
310 write_reg_byte(ioaddr, CMR2, 0x01);
311 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
312
313
314 if (irq[0])
315 dev->irq = irq[0];
316 else if (ioaddr == 0x378)
317 dev->irq = 7;
318 else
319 dev->irq = 5;
320 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF);
321 write_reg(ioaddr, CMR2, CMR2_NULL);
322
323 dev->base_addr = ioaddr;
324
325
326 get_node_ID(dev);
327
328#ifndef MODULE
329 if (net_debug)
330 printk(KERN_INFO "%s", version);
331#endif
332
333 printk(KERN_NOTICE "%s: Pocket adapter found at %#3lx, IRQ %d, "
334 "SAPROM %pM.\n",
335 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
336
337
338 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
339
340 lp = netdev_priv(dev);
341 lp->addr_mode = CMR2h_Normal;
342 spin_lock_init(&lp->lock);
343
344
345 if (xcvr[0])
346 dev->if_port = xcvr[0];
347 else
348 dev->if_port = (dev->mem_start & 0xf) ? (dev->mem_start & 0x7) : 4;
349 if (dev->mem_end & 0xf)
350 net_debug = dev->mem_end & 7;
351
352 dev->netdev_ops = &atp_netdev_ops;
353 dev->watchdog_timeo = TX_TIMEOUT;
354
355 res = register_netdev(dev);
356 if (res) {
357 free_netdev(dev);
358 return res;
359 }
360
361 lp->next_module = root_atp_dev;
362 root_atp_dev = dev;
363
364 return 0;
365}
366
367
368static void __init get_node_ID(struct net_device *dev)
369{
370 long ioaddr = dev->base_addr;
371 int sa_offset = 0;
372 int i;
373
374 write_reg(ioaddr, CMR2, CMR2_EEPROM);
375
376
377
378 if (eeprom_op(ioaddr, EE_READ(0)) == 0xffff)
379 sa_offset = 15;
380
381 for (i = 0; i < 3; i++)
382 ((__be16 *)dev->dev_addr)[i] =
383 cpu_to_be16(eeprom_op(ioaddr, EE_READ(sa_offset + i)));
384
385 write_reg(ioaddr, CMR2, CMR2_NULL);
386}
387
388
389
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395
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397
398
399
400static unsigned short __init eeprom_op(long ioaddr, u32 cmd)
401{
402 unsigned eedata_out = 0;
403 int num_bits = EE_CMD_SIZE;
404
405 while (--num_bits >= 0) {
406 char outval = (cmd & (1<<num_bits)) ? EE_DATA_WRITE : 0;
407 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
408 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
409 eedata_out <<= 1;
410 if (read_nibble(ioaddr, PROM_DATA) & EE_DATA_READ)
411 eedata_out++;
412 }
413 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
414 return eedata_out;
415}
416
417
418
419
420
421
422
423
424
425
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427
428static int net_open(struct net_device *dev)
429{
430 struct net_local *lp = netdev_priv(dev);
431 int ret;
432
433
434
435
436 ret = request_irq(dev->irq, atp_interrupt, 0, dev->name, dev);
437 if (ret)
438 return ret;
439
440 hardware_init(dev);
441
442 lp->dev = dev;
443 timer_setup(&lp->timer, atp_timed_checker, 0);
444 lp->timer.expires = jiffies + TIMED_CHECKER;
445 add_timer(&lp->timer);
446
447 netif_start_queue(dev);
448 return 0;
449}
450
451
452
453static void hardware_init(struct net_device *dev)
454{
455 struct net_local *lp = netdev_priv(dev);
456 long ioaddr = dev->base_addr;
457 int i;
458
459
460 for (i = 0; i < 8; i++)
461 outb(mux_8012[i], ioaddr + PAR_DATA);
462 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
463
464 for (i = 0; i < 6; i++)
465 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
466
467 write_reg_high(ioaddr, CMR2, lp->addr_mode);
468
469 if (net_debug > 2) {
470 printk(KERN_DEBUG "%s: Reset: current Rx mode %d.\n", dev->name,
471 (read_nibble(ioaddr, CMR2_h) >> 3) & 0x0f);
472 }
473
474 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
475 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
476
477
478 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
479
480
481 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
482 write_reg_high(ioaddr, IMR, ISRh_RxErr);
483
484 lp->tx_unit_busy = 0;
485 lp->pac_cnt_in_tx_buf = 0;
486 lp->saved_tx_size = 0;
487}
488
489static void trigger_send(long ioaddr, int length)
490{
491 write_reg_byte(ioaddr, TxCNT0, length & 0xff);
492 write_reg(ioaddr, TxCNT1, length >> 8);
493 write_reg(ioaddr, CMR1, CMR1_Xmit);
494}
495
496static void write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode)
497{
498 if (length & 1)
499 {
500 length++;
501 pad_len++;
502 }
503
504 outb(EOC+MAR, ioaddr + PAR_DATA);
505 if ((data_mode & 1) == 0) {
506
507 outb(WrAddr+MAR, ioaddr + PAR_DATA);
508 do {
509 write_byte_mode0(ioaddr, *packet++);
510 } while (--length > pad_len) ;
511 do {
512 write_byte_mode0(ioaddr, 0);
513 } while (--length > 0) ;
514 } else {
515
516 unsigned char outbyte = *packet++;
517
518 outb(Ctrl_LNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
519 outb(WrAddr+MAR, ioaddr + PAR_DATA);
520
521 outb((outbyte & 0x0f)|0x40, ioaddr + PAR_DATA);
522 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
523 outbyte >>= 4;
524 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
525 outb(Ctrl_HNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
526 while (--length > pad_len)
527 write_byte_mode1(ioaddr, *packet++);
528 while (--length > 0)
529 write_byte_mode1(ioaddr, 0);
530 }
531
532 outb(0xff, ioaddr + PAR_DATA);
533 outb(Ctrl_HNibWrite | Ctrl_SelData | Ctrl_IRQEN, ioaddr + PAR_CONTROL);
534}
535
536static void tx_timeout(struct net_device *dev)
537{
538 long ioaddr = dev->base_addr;
539
540 printk(KERN_WARNING "%s: Transmit timed out, %s?\n", dev->name,
541 inb(ioaddr + PAR_CONTROL) & 0x10 ? "network cable problem"
542 : "IRQ conflict");
543 dev->stats.tx_errors++;
544
545 hardware_init(dev);
546 netif_trans_update(dev);
547 netif_wake_queue(dev);
548 dev->stats.tx_errors++;
549}
550
551static netdev_tx_t atp_send_packet(struct sk_buff *skb,
552 struct net_device *dev)
553{
554 struct net_local *lp = netdev_priv(dev);
555 long ioaddr = dev->base_addr;
556 int length;
557 unsigned long flags;
558
559 length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
560
561 netif_stop_queue(dev);
562
563
564
565
566 spin_lock_irqsave(&lp->lock, flags);
567 write_reg(ioaddr, IMR, 0);
568 write_reg_high(ioaddr, IMR, 0);
569 spin_unlock_irqrestore(&lp->lock, flags);
570
571 write_packet(ioaddr, length, skb->data, length-skb->len, dev->if_port);
572
573 lp->pac_cnt_in_tx_buf++;
574 if (lp->tx_unit_busy == 0) {
575 trigger_send(ioaddr, length);
576 lp->saved_tx_size = 0;
577 lp->re_tx = 0;
578 lp->tx_unit_busy = 1;
579 } else
580 lp->saved_tx_size = length;
581
582 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
583 write_reg_high(ioaddr, IMR, ISRh_RxErr);
584
585 dev_kfree_skb (skb);
586 return NETDEV_TX_OK;
587}
588
589
590
591
592static irqreturn_t atp_interrupt(int irq, void *dev_instance)
593{
594 struct net_device *dev = dev_instance;
595 struct net_local *lp;
596 long ioaddr;
597 static int num_tx_since_rx;
598 int boguscount = max_interrupt_work;
599 int handled = 0;
600
601 ioaddr = dev->base_addr;
602 lp = netdev_priv(dev);
603
604 spin_lock(&lp->lock);
605
606
607 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
608
609
610 write_reg(ioaddr, CMR2, CMR2_NULL);
611 write_reg(ioaddr, IMR, 0);
612
613 if (net_debug > 5)
614 printk(KERN_DEBUG "%s: In interrupt ", dev->name);
615 while (--boguscount > 0) {
616 int status = read_nibble(ioaddr, ISR);
617 if (net_debug > 5)
618 printk("loop status %02x..", status);
619
620 if (status & (ISR_RxOK<<3)) {
621 handled = 1;
622 write_reg(ioaddr, ISR, ISR_RxOK);
623 do {
624 int read_status = read_nibble(ioaddr, CMR1);
625 if (net_debug > 6)
626 printk("handling Rx packet %02x..", read_status);
627
628
629 if (read_status & (CMR1_IRQ << 3)) {
630 dev->stats.rx_over_errors++;
631
632 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
633 net_rx(dev);
634
635 write_reg_high(ioaddr, ISR, ISRh_RxErr);
636 write_reg_high(ioaddr, CMR2, lp->addr_mode);
637 } else if ((read_status & (CMR1_BufEnb << 3)) == 0) {
638 net_rx(dev);
639 num_tx_since_rx = 0;
640 } else
641 break;
642 } while (--boguscount > 0);
643 } else if (status & ((ISR_TxErr + ISR_TxOK)<<3)) {
644 handled = 1;
645 if (net_debug > 6)
646 printk("handling Tx done..");
647
648
649 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK);
650 if (status & (ISR_TxErr<<3)) {
651 dev->stats.collisions++;
652 if (++lp->re_tx > 15) {
653 dev->stats.tx_aborted_errors++;
654 hardware_init(dev);
655 break;
656 }
657
658 if (net_debug > 6) printk("attempting to ReTx");
659 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit);
660 } else {
661
662 dev->stats.tx_packets++;
663 lp->pac_cnt_in_tx_buf--;
664 if ( lp->saved_tx_size) {
665 trigger_send(ioaddr, lp->saved_tx_size);
666 lp->saved_tx_size = 0;
667 lp->re_tx = 0;
668 } else
669 lp->tx_unit_busy = 0;
670 netif_wake_queue(dev);
671 }
672 num_tx_since_rx++;
673 } else if (num_tx_since_rx > 8 &&
674 time_after(jiffies, lp->last_rx_time + HZ)) {
675 if (net_debug > 2)
676 printk(KERN_DEBUG "%s: Missed packet? No Rx after %d Tx and "
677 "%ld jiffies status %02x CMR1 %02x.\n", dev->name,
678 num_tx_since_rx, jiffies - lp->last_rx_time, status,
679 (read_nibble(ioaddr, CMR1) >> 3) & 15);
680 dev->stats.rx_missed_errors++;
681 hardware_init(dev);
682 num_tx_since_rx = 0;
683 break;
684 } else
685 break;
686 }
687
688
689
690 {
691 int i;
692 for (i = 0; i < 6; i++)
693 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
694#if 0 && defined(TIMED_CHECKER)
695 mod_timer(&lp->timer, jiffies + TIMED_CHECKER);
696#endif
697 }
698
699
700 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
701
702 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
703
704 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
705 write_reg_high(ioaddr, IMR, ISRh_RxErr);
706
707 spin_unlock(&lp->lock);
708
709 if (net_debug > 5) printk("exiting interrupt.\n");
710 return IRQ_RETVAL(handled);
711}
712
713#ifdef TIMED_CHECKER
714
715
716static void atp_timed_checker(struct timer_list *t)
717{
718 struct net_local *lp = from_timer(lp, t, timer);
719 struct net_device *dev = lp->dev;
720 long ioaddr = dev->base_addr;
721 int tickssofar = jiffies - lp->last_rx_time;
722 int i;
723
724 spin_lock(&lp->lock);
725 if (tickssofar > 2*HZ) {
726#if 1
727 for (i = 0; i < 6; i++)
728 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
729 lp->last_rx_time = jiffies;
730#else
731 for (i = 0; i < 6; i++)
732 if (read_cmd_byte(ioaddr, PAR0 + i) != atp_timed_dev->dev_addr[i])
733 {
734 struct net_local *lp = netdev_priv(atp_timed_dev);
735 write_reg_byte(ioaddr, PAR0 + i, atp_timed_dev->dev_addr[i]);
736 if (i == 2)
737 dev->stats.tx_errors++;
738 else if (i == 3)
739 dev->stats.tx_dropped++;
740 else if (i == 4)
741 dev->stats.collisions++;
742 else
743 dev->stats.rx_errors++;
744 }
745#endif
746 }
747 spin_unlock(&lp->lock);
748 lp->timer.expires = jiffies + TIMED_CHECKER;
749 add_timer(&lp->timer);
750}
751#endif
752
753
754static void net_rx(struct net_device *dev)
755{
756 struct net_local *lp = netdev_priv(dev);
757 long ioaddr = dev->base_addr;
758 struct rx_header rx_head;
759
760
761 outb(EOC+MAR, ioaddr + PAR_DATA);
762 read_block(ioaddr, 8, (unsigned char*)&rx_head, dev->if_port);
763 if (net_debug > 5)
764 printk(KERN_DEBUG " rx_count %04x %04x %04x %04x..", rx_head.pad,
765 rx_head.rx_count, rx_head.rx_status, rx_head.cur_addr);
766 if ((rx_head.rx_status & 0x77) != 0x01) {
767 dev->stats.rx_errors++;
768 if (rx_head.rx_status & 0x0004) dev->stats.rx_frame_errors++;
769 else if (rx_head.rx_status & 0x0002) dev->stats.rx_crc_errors++;
770 if (net_debug > 3)
771 printk(KERN_DEBUG "%s: Unknown ATP Rx error %04x.\n",
772 dev->name, rx_head.rx_status);
773 if (rx_head.rx_status & 0x0020) {
774 dev->stats.rx_fifo_errors++;
775 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
776 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
777 } else if (rx_head.rx_status & 0x0050)
778 hardware_init(dev);
779 return;
780 } else {
781
782 int pkt_len = (rx_head.rx_count & 0x7ff) - 4;
783 struct sk_buff *skb;
784
785 skb = netdev_alloc_skb(dev, pkt_len + 2);
786 if (skb == NULL) {
787 dev->stats.rx_dropped++;
788 goto done;
789 }
790
791 skb_reserve(skb, 2);
792 read_block(ioaddr, pkt_len, skb_put(skb,pkt_len), dev->if_port);
793 skb->protocol = eth_type_trans(skb, dev);
794 netif_rx(skb);
795 dev->stats.rx_packets++;
796 dev->stats.rx_bytes += pkt_len;
797 }
798 done:
799 write_reg(ioaddr, CMR1, CMR1_NextPkt);
800 lp->last_rx_time = jiffies;
801}
802
803static void read_block(long ioaddr, int length, unsigned char *p, int data_mode)
804{
805 if (data_mode <= 3) {
806 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
807 outb(length == 8 ? RdAddr | HNib | MAR : RdAddr | MAR,
808 ioaddr + PAR_DATA);
809 if (data_mode <= 1) {
810 do { *p++ = read_byte_mode0(ioaddr); } while (--length > 0);
811 } else {
812 do { *p++ = read_byte_mode2(ioaddr); } while (--length > 0);
813 }
814 } else if (data_mode <= 5) {
815 do { *p++ = read_byte_mode4(ioaddr); } while (--length > 0);
816 } else {
817 do { *p++ = read_byte_mode6(ioaddr); } while (--length > 0);
818 }
819
820 outb(EOC+HNib+MAR, ioaddr + PAR_DATA);
821 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
822}
823
824
825static int
826net_close(struct net_device *dev)
827{
828 struct net_local *lp = netdev_priv(dev);
829 long ioaddr = dev->base_addr;
830
831 netif_stop_queue(dev);
832
833 del_timer_sync(&lp->timer);
834
835
836 lp->addr_mode = CMR2h_OFF;
837 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
838
839
840 outb(0x00, ioaddr + PAR_CONTROL);
841 free_irq(dev->irq, dev);
842
843
844 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
845 return 0;
846}
847
848
849
850
851
852static void set_rx_mode(struct net_device *dev)
853{
854 struct net_local *lp = netdev_priv(dev);
855 long ioaddr = dev->base_addr;
856
857 if (!netdev_mc_empty(dev) || (dev->flags & (IFF_ALLMULTI|IFF_PROMISC)))
858 lp->addr_mode = CMR2h_PROMISC;
859 else
860 lp->addr_mode = CMR2h_Normal;
861 write_reg_high(ioaddr, CMR2, lp->addr_mode);
862}
863
864static int __init atp_init_module(void) {
865 if (debug)
866 printk(KERN_INFO "%s", version);
867 return atp_init();
868}
869
870static void __exit atp_cleanup_module(void) {
871 struct net_device *next_dev;
872
873 while (root_atp_dev) {
874 struct net_local *atp_local = netdev_priv(root_atp_dev);
875 next_dev = atp_local->next_module;
876 unregister_netdev(root_atp_dev);
877
878 free_netdev(root_atp_dev);
879 root_atp_dev = next_dev;
880 }
881}
882
883module_init(atp_init_module);
884module_exit(atp_cleanup_module);
885