1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#ifndef __RTL8723E_REG_H__ 5#define __RTL8723E_REG_H__ 6 7#define REG_SYS_ISO_CTRL 0x0000 8#define REG_SYS_FUNC_EN 0x0002 9#define REG_APS_FSMCO 0x0004 10#define REG_SYS_CLKR 0x0008 11#define REG_9346CR 0x000A 12#define REG_EE_VPD 0x000C 13#define REG_AFE_MISC 0x0010 14#define REG_SPS0_CTRL 0x0011 15#define REG_SPS_OCP_CFG 0x0018 16#define REG_RSV_CTRL 0x001C 17#define REG_RF_CTRL 0x001F 18#define REG_LDOA15_CTRL 0x0020 19#define REG_LDOV12D_CTRL 0x0021 20#define REG_LDOHCI12_CTRL 0x0022 21#define REG_LPLDO_CTRL 0x0023 22#define REG_AFE_XTAL_CTRL 0x0024 23#define REG_AFE_PLL_CTRL 0x0028 24#define REG_EFUSE_CTRL 0x0030 25#define REG_EFUSE_TEST 0x0034 26#define REG_PWR_DATA 0x0038 27#define REG_CAL_TIMER 0x003C 28#define REG_ACLK_MON 0x003E 29#define REG_GPIO_MUXCFG 0x0040 30#define REG_GPIO_IO_SEL 0x0042 31#define REG_MAC_PINMUX_CFG 0x0043 32#define REG_GPIO_PIN_CTRL 0x0044 33#define REG_GPIO_INTM 0x0048 34#define REG_LEDCFG0 0x004C 35#define REG_LEDCFG1 0x004D 36#define REG_LEDCFG2 0x004E 37#define REG_LEDCFG3 0x004F 38#define REG_FSIMR 0x0050 39#define REG_FSISR 0x0054 40#define REG_GPIO_PIN_CTRL_2 0x0060 41#define REG_GPIO_IO_SEL_2 0x0062 42#define REG_MULTI_FUNC_CTRL 0x0068 43 44#define REG_MCUFWDL 0x0080 45 46#define REG_HMEBOX_EXT_0 0x0088 47#define REG_HMEBOX_EXT_1 0x008A 48#define REG_HMEBOX_EXT_2 0x008C 49#define REG_HMEBOX_EXT_3 0x008E 50 51#define REG_BIST_SCAN 0x00D0 52#define REG_BIST_RPT 0x00D4 53#define REG_BIST_ROM_RPT 0x00D8 54#define REG_USB_SIE_INTF 0x00E0 55#define REG_PCIE_MIO_INTF 0x00E4 56#define REG_PCIE_MIO_INTD 0x00E8 57#define REG_SYS_CFG 0x00F0 58#define REG_GPIO_OUTSTS 0x00F4 59 60#define REG_CR 0x0100 61#define REG_PBP 0x0104 62#define REG_TRXDMA_CTRL 0x010C 63#define REG_TRXFF_BNDY 0x0114 64#define REG_TRXFF_STATUS 0x0118 65#define REG_RXFF_PTR 0x011C 66#define REG_HIMR 0x0120 67#define REG_HISR 0x0124 68#define REG_HIMRE 0x0128 69#define REG_HISRE 0x012C 70#define REG_CPWM 0x012F 71#define REG_FWIMR 0x0130 72#define REG_FWISR 0x0134 73#define REG_PKTBUF_DBG_CTRL 0x0140 74#define REG_PKTBUF_DBG_DATA_L 0x0144 75#define REG_PKTBUF_DBG_DATA_H 0x0148 76 77#define REG_TC0_CTRL 0x0150 78#define REG_TC1_CTRL 0x0154 79#define REG_TC2_CTRL 0x0158 80#define REG_TC3_CTRL 0x015C 81#define REG_TC4_CTRL 0x0160 82#define REG_TCUNIT_BASE 0x0164 83#define REG_MBIST_START 0x0174 84#define REG_MBIST_DONE 0x0178 85#define REG_MBIST_FAIL 0x017C 86#define REG_C2HEVT_MSG_NORMAL 0x01A0 87#define REG_C2HEVT_MSG_TEST 0x01B8 88#define REG_MCUTST_1 0x01c0 89#define REG_FMETHR 0x01C8 90#define REG_HMETFR 0x01CC 91#define REG_HMEBOX_0 0x01D0 92#define REG_HMEBOX_1 0x01D4 93#define REG_HMEBOX_2 0x01D8 94#define REG_HMEBOX_3 0x01DC 95 96#define REG_LLT_INIT 0x01E0 97#define REG_BB_ACCEESS_CTRL 0x01E8 98#define REG_BB_ACCESS_DATA 0x01EC 99 100#define REG_RQPN 0x0200 101#define REG_FIFOPAGE 0x0204 102#define REG_TDECTRL 0x0208 103#define REG_TXDMA_OFFSET_CHK 0x020C 104#define REG_TXDMA_STATUS 0x0210 105#define REG_RQPN_NPQ 0x0214 106 107#define REG_RXDMA_AGG_PG_TH 0x0280 108#define REG_RXPKT_NUM 0x0284 109#define REG_RXDMA_STATUS 0x0288 110 111#define REG_PCIE_CTRL_REG 0x0300 112#define REG_INT_MIG 0x0304 113#define REG_BCNQ_DESA 0x0308 114#define REG_HQ_DESA 0x0310 115#define REG_MGQ_DESA 0x0318 116#define REG_VOQ_DESA 0x0320 117#define REG_VIQ_DESA 0x0328 118#define REG_BEQ_DESA 0x0330 119#define REG_BKQ_DESA 0x0338 120#define REG_RX_DESA 0x0340 121#define REG_DBI 0x0348 122#define REG_MDIO 0x0354 123#define REG_DBG_SEL 0x0360 124#define REG_PCIE_HRPWM 0x0361 125#define REG_PCIE_HCPWM 0x0363 126#define REG_UART_CTRL 0x0364 127#define REG_UART_TX_DESA 0x0370 128#define REG_UART_RX_DESA 0x0378 129 130#define REG_HDAQ_DESA_NODEF 0x0000 131#define REG_CMDQ_DESA_NODEF 0x0000 132 133#define REG_VOQ_INFORMATION 0x0400 134#define REG_VIQ_INFORMATION 0x0404 135#define REG_BEQ_INFORMATION 0x0408 136#define REG_BKQ_INFORMATION 0x040C 137#define REG_MGQ_INFORMATION 0x0410 138#define REG_HGQ_INFORMATION 0x0414 139#define REG_BCNQ_INFORMATION 0x0418 140 141#define REG_CPU_MGQ_INFORMATION 0x041C 142#define REG_FWHW_TXQ_CTRL 0x0420 143#define REG_HWSEQ_CTRL 0x0423 144#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 145#define REG_TXPKTBUF_MGQ_BDNY 0x0425 146#define REG_MULTI_BCNQ_EN 0x0426 147#define REG_MULTI_BCNQ_OFFSET 0x0427 148#define REG_SPEC_SIFS 0x0428 149#define REG_RL 0x042A 150#define REG_DARFRC 0x0430 151#define REG_RARFRC 0x0438 152#define REG_RRSR 0x0440 153#define REG_ARFR0 0x0444 154#define REG_ARFR1 0x0448 155#define REG_ARFR2 0x044C 156#define REG_ARFR3 0x0450 157#define REG_AGGLEN_LMT 0x0458 158#define REG_AMPDU_MIN_SPACE 0x045C 159#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 160#define REG_FAST_EDCA_CTRL 0x0460 161#define REG_RD_RESP_PKT_TH 0x0463 162#define REG_INIRTS_RATE_SEL 0x0480 163#define REG_INIDATA_RATE_SEL 0x0484 164#define REG_POWER_STATUS 0x04A4 165#define REG_POWER_STAGE1 0x04B4 166#define REG_POWER_STAGE2 0x04B8 167#define REG_PKT_LIFE_TIME 0x04C0 168#define REG_STBC_SETTING 0x04C4 169#define REG_PROT_MODE_CTRL 0x04C8 170#define REG_BAR_MODE_CTRL 0x04CC 171#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 172#define REG_NQOS_SEQ 0x04DC 173#define REG_QOS_SEQ 0x04DE 174#define REG_NEED_CPU_HANDLE 0x04E0 175#define REG_PKT_LOSE_RPT 0x04E1 176#define REG_PTCL_ERR_STATUS 0x04E2 177#define REG_DUMMY 0x04FC 178 179#define REG_EDCA_VO_PARAM 0x0500 180#define REG_EDCA_VI_PARAM 0x0504 181#define REG_EDCA_BE_PARAM 0x0508 182#define REG_EDCA_BK_PARAM 0x050C 183#define REG_BCNTCFG 0x0510 184#define REG_PIFS 0x0512 185#define REG_RDG_PIFS 0x0513 186#define REG_SIFS_CTX 0x0514 187#define REG_SIFS_TRX 0x0516 188#define REG_AGGR_BREAK_TIME 0x051A 189#define REG_SLOT 0x051B 190#define REG_TX_PTCL_CTRL 0x0520 191#define REG_TXPAUSE 0x0522 192#define REG_DIS_TXREQ_CLR 0x0523 193#define REG_RD_CTRL 0x0524 194#define REG_TBTT_PROHIBIT 0x0540 195#define REG_RD_NAV_NXT 0x0544 196#define REG_NAV_PROT_LEN 0x0546 197#define REG_BCN_CTRL 0x0550 198#define REG_MBID_NUM 0x0552 199#define REG_DUAL_TSF_RST 0x0553 200#define REG_BCN_INTERVAL 0x0554 201#define REG_MBSSID_BCN_SPACE 0x0554 202#define REG_DRVERLYINT 0x0558 203#define REG_BCNDMATIM 0x0559 204#define REG_ATIMWND 0x055A 205#define REG_USTIME_TSF 0x055C 206#define REG_BCN_MAX_ERR 0x055D 207#define REG_RXTSF_OFFSET_CCK 0x055E 208#define REG_RXTSF_OFFSET_OFDM 0x055F 209#define REG_TSFTR 0x0560 210#define REG_INIT_TSFTR 0x0564 211#define REG_PSTIMER 0x0580 212#define REG_TIMER0 0x0584 213#define REG_TIMER1 0x0588 214#define REG_ACMHWCTRL 0x05C0 215#define REG_ACMRSTCTRL 0x05C1 216#define REG_ACMAVG 0x05C2 217#define REG_VO_ADMTIME 0x05C4 218#define REG_VI_ADMTIME 0x05C6 219#define REG_BE_ADMTIME 0x05C8 220#define REG_EDCA_RANDOM_GEN 0x05CC 221#define REG_SCH_TXCMD 0x05D0 222 223#define REG_APSD_CTRL 0x0600 224#define REG_BWOPMODE 0x0603 225#define REG_TCR 0x0604 226#define REG_RCR 0x0608 227#define REG_RX_PKT_LIMIT 0x060C 228#define REG_RX_DLK_TIME 0x060D 229#define REG_RX_DRVINFO_SZ 0x060F 230 231#define REG_MACID 0x0610 232#define REG_BSSID 0x0618 233#define REG_MAR 0x0620 234#define REG_MBIDCAMCFG 0x0628 235 236#define REG_USTIME_EDCA 0x0638 237#define REG_MAC_SPEC_SIFS 0x063A 238#define REG_RESP_SIFS_CCK 0x063C 239#define REG_RESP_SIFS_OFDM 0x063E 240#define REG_ACKTO 0x0640 241#define REG_CTS2TO 0x0641 242#define REG_EIFS 0x0642 243 244#define REG_NAV_CTRL 0x0650 245#define REG_BACAMCMD 0x0654 246#define REG_BACAMCONTENT 0x0658 247#define REG_LBDLY 0x0660 248#define REG_FWDLY 0x0661 249#define REG_RXERR_RPT 0x0664 250#define REG_WMAC_TRXPTCL_CTL 0x0668 251 252#define REG_CAMCMD 0x0670 253#define REG_CAMWRITE 0x0674 254#define REG_CAMREAD 0x0678 255#define REG_CAMDBG 0x067C 256#define REG_SECCFG 0x0680 257 258#define REG_WOW_CTRL 0x0690 259#define REG_PSSTATUS 0x0691 260#define REG_PS_RX_INFO 0x0692 261#define REG_LPNAV_CTRL 0x0694 262#define REG_WKFMCAM_CMD 0x0698 263#define REG_WKFMCAM_RWD 0x069C 264#define REG_RXFLTMAP0 0x06A0 265#define REG_RXFLTMAP1 0x06A2 266#define REG_RXFLTMAP2 0x06A4 267#define REG_BCN_PSR_RPT 0x06A8 268#define REG_CALB32K_CTRL 0x06AC 269#define REG_PKT_MON_CTRL 0x06B4 270#define REG_BT_COEX_TABLE 0x06C0 271#define REG_WMAC_RESP_TXINFO 0x06D8 272 273#define REG_USB_INFO 0xFE17 274#define REG_USB_SPECIAL_OPTION 0xFE55 275#define REG_USB_DMA_AGG_TO 0xFE5B 276#define REG_USB_AGG_TO 0xFE5C 277#define REG_USB_AGG_TH 0xFE5D 278 279#define REG_TEST_USB_TXQS 0xFE48 280#define REG_TEST_SIE_VID 0xFE60 281#define REG_TEST_SIE_PID 0xFE62 282#define REG_TEST_SIE_OPTIONAL 0xFE64 283#define REG_TEST_SIE_CHIRP_K 0xFE65 284#define REG_TEST_SIE_PHY 0xFE66 285#define REG_TEST_SIE_MAC_ADDR 0xFE70 286#define REG_TEST_SIE_STRING 0xFE80 287 288#define REG_NORMAL_SIE_VID 0xFE60 289#define REG_NORMAL_SIE_PID 0xFE62 290#define REG_NORMAL_SIE_OPTIONAL 0xFE64 291#define REG_NORMAL_SIE_EP 0xFE65 292#define REG_NORMAL_SIE_PHY 0xFE68 293#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 294#define REG_NORMAL_SIE_STRING 0xFE80 295 296#define CR9346 REG_9346CR 297#define MSR (REG_CR + 2) 298#define ISR REG_HISR 299#define TSFR REG_TSFTR 300 301#define MACIDR0 REG_MACID 302#define MACIDR4 (REG_MACID + 4) 303 304#define PBP REG_PBP 305 306#define IDR0 MACIDR0 307#define IDR4 MACIDR4 308 309#define UNUSED_REGISTER 0x1BF 310#define DCAM UNUSED_REGISTER 311#define PSR UNUSED_REGISTER 312#define BBADDR UNUSED_REGISTER 313#define PHYDATAR UNUSED_REGISTER 314 315#define INVALID_BBRF_VALUE 0x12345678 316 317#define MAX_MSS_DENSITY_2T 0x13 318#define MAX_MSS_DENSITY_1T 0x0A 319 320#define CMDEEPROM_EN BIT(5) 321#define CMDEEPROM_SEL BIT(4) 322#define CMD9346CR_9356SEL BIT(4) 323#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 324#define AUTOLOAD_EFUSE CMDEEPROM_EN 325 326#define GPIOSEL_GPIO 0 327#define GPIOSEL_ENBT BIT(5) 328 329#define GPIO_IN REG_GPIO_PIN_CTRL 330#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 331#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 332#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 333 334#define MSR_NOLINK 0x00 335#define MSR_ADHOC 0x01 336#define MSR_INFRA 0x02 337#define MSR_AP 0x03 338 339#define RRSR_RSC_OFFSET 21 340#define RRSR_SHORT_OFFSET 23 341#define RRSR_RSC_BW_40M 0x600000 342#define RRSR_RSC_UPSUBCHNL 0x400000 343#define RRSR_RSC_LOWSUBCHNL 0x200000 344#define RRSR_SHORT 0x800000 345#define RRSR_1M BIT(0) 346#define RRSR_2M BIT(1) 347#define RRSR_5_5M BIT(2) 348#define RRSR_11M BIT(3) 349#define RRSR_6M BIT(4) 350#define RRSR_9M BIT(5) 351#define RRSR_12M BIT(6) 352#define RRSR_18M BIT(7) 353#define RRSR_24M BIT(8) 354#define RRSR_36M BIT(9) 355#define RRSR_48M BIT(10) 356#define RRSR_54M BIT(11) 357#define RRSR_MCS0 BIT(12) 358#define RRSR_MCS1 BIT(13) 359#define RRSR_MCS2 BIT(14) 360#define RRSR_MCS3 BIT(15) 361#define RRSR_MCS4 BIT(16) 362#define RRSR_MCS5 BIT(17) 363#define RRSR_MCS6 BIT(18) 364#define RRSR_MCS7 BIT(19) 365#define BRSR_ACKSHORTPMB BIT(23) 366 367#define RATR_1M 0x00000001 368#define RATR_2M 0x00000002 369#define RATR_55M 0x00000004 370#define RATR_11M 0x00000008 371#define RATR_6M 0x00000010 372#define RATR_9M 0x00000020 373#define RATR_12M 0x00000040 374#define RATR_18M 0x00000080 375#define RATR_24M 0x00000100 376#define RATR_36M 0x00000200 377#define RATR_48M 0x00000400 378#define RATR_54M 0x00000800 379#define RATR_MCS0 0x00001000 380#define RATR_MCS1 0x00002000 381#define RATR_MCS2 0x00004000 382#define RATR_MCS3 0x00008000 383#define RATR_MCS4 0x00010000 384#define RATR_MCS5 0x00020000 385#define RATR_MCS6 0x00040000 386#define RATR_MCS7 0x00080000 387#define RATR_MCS8 0x00100000 388#define RATR_MCS9 0x00200000 389#define RATR_MCS10 0x00400000 390#define RATR_MCS11 0x00800000 391#define RATR_MCS12 0x01000000 392#define RATR_MCS13 0x02000000 393#define RATR_MCS14 0x04000000 394#define RATR_MCS15 0x08000000 395 396#define RATE_1M BIT(0) 397#define RATE_2M BIT(1) 398#define RATE_5_5M BIT(2) 399#define RATE_11M BIT(3) 400#define RATE_6M BIT(4) 401#define RATE_9M BIT(5) 402#define RATE_12M BIT(6) 403#define RATE_18M BIT(7) 404#define RATE_24M BIT(8) 405#define RATE_36M BIT(9) 406#define RATE_48M BIT(10) 407#define RATE_54M BIT(11) 408#define RATE_MCS0 BIT(12) 409#define RATE_MCS1 BIT(13) 410#define RATE_MCS2 BIT(14) 411#define RATE_MCS3 BIT(15) 412#define RATE_MCS4 BIT(16) 413#define RATE_MCS5 BIT(17) 414#define RATE_MCS6 BIT(18) 415#define RATE_MCS7 BIT(19) 416#define RATE_MCS8 BIT(20) 417#define RATE_MCS9 BIT(21) 418#define RATE_MCS10 BIT(22) 419#define RATE_MCS11 BIT(23) 420#define RATE_MCS12 BIT(24) 421#define RATE_MCS13 BIT(25) 422#define RATE_MCS14 BIT(26) 423#define RATE_MCS15 BIT(27) 424 425#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 426#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 427 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 428#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 429 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 430 RATR_MCS6 | RATR_MCS7) 431#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 432 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 433 RATR_MCS14 | RATR_MCS15) 434 435#define BW_OPMODE_20MHZ BIT(2) 436#define BW_OPMODE_5G BIT(1) 437#define BW_OPMODE_11J BIT(0) 438 439#define CAM_VALID BIT(15) 440#define CAM_NOTVALID 0x0000 441#define CAM_USEDK BIT(5) 442 443#define CAM_NONE 0x0 444#define CAM_WEP40 0x01 445#define CAM_TKIP 0x02 446#define CAM_AES 0x04 447#define CAM_WEP104 0x05 448 449#define TOTAL_CAM_ENTRY 32 450#define HALF_CAM_ENTRY 16 451 452#define CAM_WRITE BIT(16) 453#define CAM_READ 0x00000000 454#define CAM_POLLINIG BIT(31) 455 456#define SCR_USEDK 0x01 457#define SCR_TXSEC_ENABLE 0x02 458#define SCR_RXSEC_ENABLE 0x04 459 460#define WOW_PMEN BIT(0) 461#define WOW_WOMEN BIT(1) 462#define WOW_MAGIC BIT(2) 463#define WOW_UWF BIT(3) 464 465#define IMR8190_DISABLED 0x0 466#define IMR_BCNDMAINT6 BIT(31) 467#define IMR_BCNDMAINT5 BIT(30) 468#define IMR_BCNDMAINT4 BIT(29) 469#define IMR_BCNDMAINT3 BIT(28) 470#define IMR_BCNDMAINT2 BIT(27) 471#define IMR_BCNDMAINT1 BIT(26) 472#define IMR_BCNDOK8 BIT(25) 473#define IMR_BCNDOK7 BIT(24) 474#define IMR_BCNDOK6 BIT(23) 475#define IMR_BCNDOK5 BIT(22) 476#define IMR_BCNDOK4 BIT(21) 477#define IMR_BCNDOK3 BIT(20) 478#define IMR_BCNDOK2 BIT(19) 479#define IMR_BCNDOK1 BIT(18) 480#define IMR_TIMEOUT2 BIT(17) 481#define IMR_TIMEOUT1 BIT(16) 482#define IMR_TXFOVW BIT(15) 483#define IMR_PSTIMEOUT BIT(14) 484#define IMR_BCNINT BIT(13) 485#define IMR_RXFOVW BIT(12) 486#define IMR_RDU BIT(11) 487#define IMR_ATIMEND BIT(10) 488#define IMR_BDOK BIT(9) 489#define IMR_HIGHDOK BIT(8) 490#define IMR_TBDOK BIT(7) 491#define IMR_MGNTDOK BIT(6) 492#define IMR_TBDER BIT(5) 493#define IMR_BKDOK BIT(4) 494#define IMR_BEDOK BIT(3) 495#define IMR_VIDOK BIT(2) 496#define IMR_VODOK BIT(1) 497#define IMR_ROK BIT(0) 498 499#define IMR_TXERR BIT(11) 500#define IMR_RXERR BIT(10) 501#define IMR_CPWM BIT(8) 502#define IMR_OCPINT BIT(1) 503#define IMR_WLANOFF BIT(0) 504 505/* 8723E series PCIE Host IMR/ISR bit */ 506/* IMR DW0 Bit 0-31 */ 507#define PHIMR_TIMEOUT2 BIT(31) 508#define PHIMR_TIMEOUT1 BIT(30) 509#define PHIMR_PSTIMEOUT BIT(29) 510#define PHIMR_GTINT4 BIT(28) 511#define PHIMR_GTINT3 BIT(27) 512#define PHIMR_TXBCNERR BIT(26) 513#define PHIMR_TXBCNOK BIT(25) 514#define PHIMR_TSF_BIT32_TOGGLE BIT(24) 515#define PHIMR_BCNDMAINT3 BIT(23) 516#define PHIMR_BCNDMAINT2 BIT(22) 517#define PHIMR_BCNDMAINT1 BIT(21) 518#define PHIMR_BCNDMAINT0 BIT(20) 519#define PHIMR_BCNDOK3 BIT(19) 520#define PHIMR_BCNDOK2 BIT(18) 521#define PHIMR_BCNDOK1 BIT(17) 522#define PHIMR_BCNDOK0 BIT(16) 523#define PHIMR_HSISR_IND_ON BIT(15) 524#define PHIMR_BCNDMAINT_E BIT(14) 525#define PHIMR_ATIMEND_E BIT(13) 526#define PHIMR_ATIM_CTW_END BIT(12) 527#define PHIMR_HISRE_IND BIT(11) 528#define PHIMR_C2HCMD BIT(10) 529#define PHIMR_CPWM2 BIT(9) 530#define PHIMR_CPWM BIT(8) 531#define PHIMR_HIGHDOK BIT(7) 532#define PHIMR_MGNTDOK BIT(6) 533#define PHIMR_BKDOK BIT(5) 534#define PHIMR_BEDOK BIT(4) 535#define PHIMR_VIDOK BIT(3) 536#define PHIMR_VODOK BIT(2) 537#define PHIMR_RDU BIT(1) 538#define PHIMR_ROK BIT(0) 539 540/* PCIE Host Interrupt Status Extension bit */ 541#define PHIMR_BCNDMAINT7 BIT(23) 542#define PHIMR_BCNDMAINT6 BIT(22) 543#define PHIMR_BCNDMAINT5 BIT(21) 544#define PHIMR_BCNDMAINT4 BIT(20) 545#define PHIMR_BCNDOK7 BIT(19) 546#define PHIMR_BCNDOK6 BIT(18) 547#define PHIMR_BCNDOK5 BIT(17) 548#define PHIMR_BCNDOK4 BIT(16) 549/* bit12-15: RSVD */ 550#define PHIMR_TXERR BIT(11) 551#define PHIMR_RXERR BIT(10) 552#define PHIMR_TXFOVW BIT(9) 553#define PHIMR_RXFOVW BIT(8) 554/* bit2-7: RSVD */ 555#define PHIMR_OCPINT BIT(1) 556 557#define HWSET_MAX_SIZE 256 558#define EFUSE_MAX_SECTION 32 559#define EFUSE_REAL_CONTENT_LEN 512 560#define EFUSE_OOB_PROTECT_BYTES 15 561 562#define EEPROM_DEFAULT_TSSI 0x0 563#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 564#define EEPROM_DEFAULT_CRYSTALCAP 0x5 565#define EEPROM_DEFAULT_BOARDTYPE 0x02 566#define EEPROM_DEFAULT_TXPOWER 0x1010 567#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 568 569#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 570#define EEPROM_DEFAULT_THERMALMETER 0x12 571#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 572#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 573#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 574#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 575#define EEPROM_DEFAULT_HT20_DIFF 2 576#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 577#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 578#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 579 580#define EEPROM_DEFAULT_PID 0x1234 581#define EEPROM_DEFAULT_VID 0x5678 582#define EEPROM_DEFAULT_CUSTOMERID 0xAB 583#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 584#define EEPROM_DEFAULT_VERSION 0 585 586#define EEPROM_CHANNEL_PLAN_FCC 0x0 587#define EEPROM_CHANNEL_PLAN_IC 0x1 588#define EEPROM_CHANNEL_PLAN_ETSI 0x2 589#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 590#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 591#define EEPROM_CHANNEL_PLAN_MKK 0x5 592#define EEPROM_CHANNEL_PLAN_MKK1 0x6 593#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 594#define EEPROM_CHANNEL_PLAN_TELEC 0x8 595#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 596#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 597#define EEPROM_CHANNEL_PLAN_NCC 0xB 598#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 599 600#define EEPROM_CID_DEFAULT 0x0 601#define EEPROM_CID_TOSHIBA 0x4 602#define EEPROM_CID_CCX 0x10 603#define EEPROM_CID_QMI 0x0D 604#define EEPROM_CID_WHQL 0xFE 605 606#define RTL8192_EEPROM_ID 0x8129 607 608#define RTL8190_EEPROM_ID 0x8129 609#define EEPROM_HPON 0x02 610#define EEPROM_CLK 0x06 611#define EEPROM_TESTR 0x08 612 613#define EEPROM_VID 0x49 614#define EEPROM_DID 0x4B 615#define EEPROM_SVID 0x4D 616#define EEPROM_SMID 0x4F 617 618#define EEPROM_MAC_ADDR 0x67 619 620#define EEPROM_CCK_TX_PWR_INX 0x5A 621#define EEPROM_HT40_1S_TX_PWR_INX 0x60 622#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 623#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 624#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 625#define EEPROM_HT40_MAX_PWR_OFFSET 0x25 626#define EEPROM_HT20_MAX_PWR_OFFSET 0x22 627 628#define EEPROM_THERMAL_METER 0x2a 629#define EEPROM_XTAL_K 0x78 630#define EEPROM_RF_OPT1 0x79 631#define EEPROM_RF_OPT2 0x7A 632#define EEPROM_RF_OPT3 0x7B 633#define EEPROM_RF_OPT4 0x7C 634#define EEPROM_CHANNEL_PLAN 0x28 635#define EEPROM_VERSION 0x30 636#define EEPROM_CUSTOMER_ID 0x31 637 638#define EEPROM_PWRDIFF 0x54 639 640#define EEPROM_TXPOWERCCK 0x10 641#define EEPROM_TXPOWERHT40_1S 0x16 642#define EEPROM_TXPOWERHT40_2SDIFF 0x66 643#define EEPROM_TXPOWERHT20DIFF 0x1C 644#define EEPROM_TXPOWER_OFDMDIFF 0x1F 645 646#define EEPROM_TXPWR_GROUP 0x22 647 648#define EEPROM_TSSI_A 0x29 649#define EEPROM_TSSI_B 0x77 650 651#define EEPROM_CHANNELPLAN 0x28 652 653#define RF_OPTION1 0x2B 654#define RF_OPTION2 0x2C 655#define RF_OPTION3 0x2D 656#define RF_OPTION4 0x2E 657 658#define STOPBECON BIT(6) 659#define STOPHIGHT BIT(5) 660#define STOPMGT BIT(4) 661#define STOPVO BIT(3) 662#define STOPVI BIT(2) 663#define STOPBE BIT(1) 664#define STOPBK BIT(0) 665 666#define RCR_APPFCS BIT(31) 667#define RCR_APP_MIC BIT(30) 668#define RCR_APP_ICV BIT(29) 669#define RCR_APP_PHYST_RXFF BIT(28) 670#define RCR_APP_BA_SSN BIT(27) 671#define RCR_ENMBID BIT(24) 672#define RCR_LSIGEN BIT(23) 673#define RCR_MFBEN BIT(22) 674#define RCR_HTC_LOC_CTRL BIT(14) 675#define RCR_AMF BIT(13) 676#define RCR_ACF BIT(12) 677#define RCR_ADF BIT(11) 678#define RCR_AICV BIT(9) 679#define RCR_ACRC32 BIT(8) 680#define RCR_CBSSID_BCN BIT(7) 681#define RCR_CBSSID_DATA BIT(6) 682#define RCR_CBSSID RCR_CBSSID_DATA 683#define RCR_APWRMGT BIT(5) 684#define RCR_ADD3 BIT(4) 685#define RCR_AB BIT(3) 686#define RCR_AM BIT(2) 687#define RCR_APM BIT(1) 688#define RCR_AAP BIT(0) 689#define RCR_MXDMA_OFFSET 8 690#define RCR_FIFO_OFFSET 13 691 692#define RSV_CTRL 0x001C 693#define RD_CTRL 0x0524 694 695#define REG_USB_INFO 0xFE17 696#define REG_USB_SPECIAL_OPTION 0xFE55 697#define REG_USB_DMA_AGG_TO 0xFE5B 698#define REG_USB_AGG_TO 0xFE5C 699#define REG_USB_AGG_TH 0xFE5D 700 701#define REG_USB_VID 0xFE60 702#define REG_USB_PID 0xFE62 703#define REG_USB_OPTIONAL 0xFE64 704#define REG_USB_CHIRP_K 0xFE65 705#define REG_USB_PHY 0xFE66 706#define REG_USB_MAC_ADDR 0xFE70 707#define REG_USB_HRPWM 0xFE58 708#define REG_USB_HCPWM 0xFE57 709 710#define SW18_FPWM BIT(3) 711 712#define ISO_MD2PP BIT(0) 713#define ISO_UA2USB BIT(1) 714#define ISO_UD2CORE BIT(2) 715#define ISO_PA2PCIE BIT(3) 716#define ISO_PD2CORE BIT(4) 717#define ISO_IP2MAC BIT(5) 718#define ISO_DIOP BIT(6) 719#define ISO_DIOE BIT(7) 720#define ISO_EB2CORE BIT(8) 721#define ISO_DIOR BIT(9) 722 723#define PWC_EV25V BIT(14) 724#define PWC_EV12V BIT(15) 725 726#define FEN_BBRSTB BIT(0) 727#define FEN_BB_GLB_RSTN BIT(1) 728#define FEN_USBA BIT(2) 729#define FEN_UPLL BIT(3) 730#define FEN_USBD BIT(4) 731#define FEN_DIO_PCIE BIT(5) 732#define FEN_PCIEA BIT(6) 733#define FEN_PPLL BIT(7) 734#define FEN_PCIED BIT(8) 735#define FEN_DIOE BIT(9) 736#define FEN_CPUEN BIT(10) 737#define FEN_DCORE BIT(11) 738#define FEN_ELDR BIT(12) 739#define FEN_DIO_RF BIT(13) 740#define FEN_HWPDN BIT(14) 741#define FEN_MREGEN BIT(15) 742 743#define PFM_LDALL BIT(0) 744#define PFM_ALDN BIT(1) 745#define PFM_LDKP BIT(2) 746#define PFM_WOWL BIT(3) 747#define ENPDN BIT(4) 748#define PDN_PL BIT(5) 749#define APFM_ONMAC BIT(8) 750#define APFM_OFF BIT(9) 751#define APFM_RSM BIT(10) 752#define AFSM_HSUS BIT(11) 753#define AFSM_PCIE BIT(12) 754#define APDM_MAC BIT(13) 755#define APDM_HOST BIT(14) 756#define APDM_HPDN BIT(15) 757#define RDY_MACON BIT(16) 758#define SUS_HOST BIT(17) 759#define ROP_ALD BIT(20) 760#define ROP_PWR BIT(21) 761#define ROP_SPS BIT(22) 762#define SOP_MRST BIT(25) 763#define SOP_FUSE BIT(26) 764#define SOP_ABG BIT(27) 765#define SOP_AMB BIT(28) 766#define SOP_RCK BIT(29) 767#define SOP_A8M BIT(30) 768#define XOP_BTCK BIT(31) 769 770#define ANAD16V_EN BIT(0) 771#define ANA8M BIT(1) 772#define MACSLP BIT(4) 773#define LOADER_CLK_EN BIT(5) 774#define _80M_SSC_DIS BIT(7) 775#define _80M_SSC_EN_HO BIT(8) 776#define PHY_SSC_RSTB BIT(9) 777#define SEC_CLK_EN BIT(10) 778#define MAC_CLK_EN BIT(11) 779#define SYS_CLK_EN BIT(12) 780#define RING_CLK_EN BIT(13) 781 782#define BOOT_FROM_EEPROM BIT(4) 783#define EEPROM_EN BIT(5) 784 785#define AFE_BGEN BIT(0) 786#define AFE_MBEN BIT(1) 787#define MAC_ID_EN BIT(7) 788 789#define WLOCK_ALL BIT(0) 790#define WLOCK_00 BIT(1) 791#define WLOCK_04 BIT(2) 792#define WLOCK_08 BIT(3) 793#define WLOCK_40 BIT(4) 794#define R_DIS_PRST_0 BIT(5) 795#define R_DIS_PRST_1 BIT(6) 796#define LOCK_ALL_EN BIT(7) 797 798#define RF_EN BIT(0) 799#define RF_RSTB BIT(1) 800#define RF_SDMRSTB BIT(2) 801 802#define LDA15_EN BIT(0) 803#define LDA15_STBY BIT(1) 804#define LDA15_OBUF BIT(2) 805#define LDA15_REG_VOS BIT(3) 806#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 807 808#define LDV12_EN BIT(0) 809#define LDV12_SDBY BIT(1) 810#define LPLDO_HSM BIT(2) 811#define LPLDO_LSM_DIS BIT(3) 812#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 813 814#define XTAL_EN BIT(0) 815#define XTAL_BSEL BIT(1) 816#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 817#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 818#define XTAL_GATE_USB BIT(8) 819#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 820#define XTAL_GATE_AFE BIT(11) 821#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 822#define XTAL_RF_GATE BIT(14) 823#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 824#define XTAL_GATE_DIG BIT(17) 825#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 826#define XTAL_BT_GATE BIT(20) 827#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 828#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 829 830#define CKDLY_AFE BIT(26) 831#define CKDLY_USB BIT(27) 832#define CKDLY_DIG BIT(28) 833#define CKDLY_BT BIT(29) 834 835#define APLL_EN BIT(0) 836#define APLL_320_EN BIT(1) 837#define APLL_FREF_SEL BIT(2) 838#define APLL_EDGE_SEL BIT(3) 839#define APLL_WDOGB BIT(4) 840#define APLL_LPFEN BIT(5) 841 842#define APLL_REF_CLK_13MHZ 0x1 843#define APLL_REF_CLK_19_2MHZ 0x2 844#define APLL_REF_CLK_20MHZ 0x3 845#define APLL_REF_CLK_25MHZ 0x4 846#define APLL_REF_CLK_26MHZ 0x5 847#define APLL_REF_CLK_38_4MHZ 0x6 848#define APLL_REF_CLK_40MHZ 0x7 849 850#define APLL_320EN BIT(14) 851#define APLL_80EN BIT(15) 852#define APLL_1MEN BIT(24) 853 854#define ALD_EN BIT(18) 855#define EF_PD BIT(19) 856#define EF_FLAG BIT(31) 857 858#define EF_TRPT BIT(7) 859#define LDOE25_EN BIT(31) 860 861#define RSM_EN BIT(0) 862#define TIMER_EN BIT(4) 863 864#define TRSW0EN BIT(2) 865#define TRSW1EN BIT(3) 866#define EROM_EN BIT(4) 867#define ENBT BIT(5) 868#define ENUART BIT(8) 869#define UART_910 BIT(9) 870#define ENPMAC BIT(10) 871#define SIC_SWRST BIT(11) 872#define ENSIC BIT(12) 873#define SIC_23 BIT(13) 874#define ENHDP BIT(14) 875#define SIC_LBK BIT(15) 876 877#define LED0PL BIT(4) 878#define LED1PL BIT(12) 879#define LED0DIS BIT(7) 880 881#define MCUFWDL_EN BIT(0) 882#define MCUFWDL_RDY BIT(1) 883#define FWDL_CHKSUM_RPT BIT(2) 884#define MACINI_RDY BIT(3) 885#define BBINI_RDY BIT(4) 886#define RFINI_RDY BIT(5) 887#define WINTINI_RDY BIT(6) 888#define CPRST BIT(23) 889 890#define XCLK_VLD BIT(0) 891#define ACLK_VLD BIT(1) 892#define UCLK_VLD BIT(2) 893#define PCLK_VLD BIT(3) 894#define PCIRSTB BIT(4) 895#define V15_VLD BIT(5) 896#define TRP_B15V_EN BIT(7) 897#define SIC_IDLE BIT(8) 898#define BD_MAC2 BIT(9) 899#define BD_MAC1 BIT(10) 900#define IC_MACPHY_MODE BIT(11) 901#define BT_FUNC BIT(16) 902#define VENDOR_ID BIT(19) 903#define PAD_HWPD_IDN BIT(22) 904#define TRP_VAUX_EN BIT(23) 905#define TRP_BT_EN BIT(24) 906#define BD_PKG_SEL BIT(25) 907#define BD_HCI_SEL BIT(26) 908#define TYPE_ID BIT(27) 909 910#define CHIP_VER_RTL_MASK 0xF000 911#define CHIP_VER_RTL_SHIFT 12 912 913#define REG_LBMODE (REG_CR + 3) 914 915#define HCI_TXDMA_EN BIT(0) 916#define HCI_RXDMA_EN BIT(1) 917#define TXDMA_EN BIT(2) 918#define RXDMA_EN BIT(3) 919#define PROTOCOL_EN BIT(4) 920#define SCHEDULE_EN BIT(5) 921#define MACTXEN BIT(6) 922#define MACRXEN BIT(7) 923#define ENSWBCN BIT(8) 924#define ENSEC BIT(9) 925 926#define _NETTYPE(x) (((x) & 0x3) << 16) 927#define MASK_NETTYPE 0x30000 928#define NT_NO_LINK 0x0 929#define NT_LINK_AD_HOC 0x1 930#define NT_LINK_AP 0x2 931#define NT_AS_AP 0x3 932 933#define _LBMODE(x) (((x) & 0xF) << 24) 934#define MASK_LBMODE 0xF000000 935#define LOOPBACK_NORMAL 0x0 936#define LOOPBACK_IMMEDIATELY 0xB 937#define LOOPBACK_MAC_DELAY 0x3 938#define LOOPBACK_PHY 0x1 939#define LOOPBACK_DMA 0x7 940 941#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 942#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 943#define _PSRX_MASK 0xF 944#define _PSTX_MASK 0xF0 945#define _PSRX(x) (x) 946#define _PSTX(x) ((x) << 4) 947 948#define PBP_64 0x0 949#define PBP_128 0x1 950#define PBP_256 0x2 951#define PBP_512 0x3 952#define PBP_1024 0x4 953 954#define RXDMA_ARBBW_EN BIT(0) 955#define RXSHFT_EN BIT(1) 956#define RXDMA_AGG_EN BIT(2) 957#define QS_VO_QUEUE BIT(8) 958#define QS_VI_QUEUE BIT(9) 959#define QS_BE_QUEUE BIT(10) 960#define QS_BK_QUEUE BIT(11) 961#define QS_MANAGER_QUEUE BIT(12) 962#define QS_HIGH_QUEUE BIT(13) 963 964#define HQSEL_VOQ BIT(0) 965#define HQSEL_VIQ BIT(1) 966#define HQSEL_BEQ BIT(2) 967#define HQSEL_BKQ BIT(3) 968#define HQSEL_MGTQ BIT(4) 969#define HQSEL_HIQ BIT(5) 970 971#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 972#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 973#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 974#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 975#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 976#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 977 978#define QUEUE_LOW 1 979#define QUEUE_NORMAL 2 980#define QUEUE_HIGH 3 981 982#define _LLT_NO_ACTIVE 0x0 983#define _LLT_WRITE_ACCESS 0x1 984#define _LLT_READ_ACCESS 0x2 985 986#define _LLT_INIT_DATA(x) ((x) & 0xFF) 987#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 988#define _LLT_OP(x) (((x) & 0x3) << 30) 989#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 990 991#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 992#define BB_WRITE_EN BIT(30) 993#define BB_READ_EN BIT(31) 994 995#define _HPQ(x) ((x) & 0xFF) 996#define _LPQ(x) (((x) & 0xFF) << 8) 997#define _PUBQ(x) (((x) & 0xFF) << 16) 998#define _NPQ(x) ((x) & 0xFF) 999 1000#define HPQ_PUBLIC_DIS BIT(24)
1001#define LPQ_PUBLIC_DIS BIT(25) 1002#define LD_RQPN BIT(31) 1003 1004#define BCN_VALID BIT(16) 1005#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1006#define BCN_HEAD_MASK 0xFF00 1007 1008#define BLK_DESC_NUM_SHIFT 4 1009#define BLK_DESC_NUM_MASK 0xF 1010 1011#define DROP_DATA_EN BIT(9) 1012 1013#define EN_AMPDU_RTY_NEW BIT(7) 1014 1015#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1016 1017#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1018#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1019 1020#define RATE_REG_BITMAP_ALL 0xFFFFF 1021 1022#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1023 1024#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1025#define RRSR_RSC_RESERVED 0x0 1026#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1027#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1028#define RRSR_RSC_DUPLICATE_MODE 0x3 1029 1030#define USE_SHORT_G1 BIT(20) 1031 1032#define _AGGLMT_MCS0(x) ((x) & 0xF) 1033#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1034#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1035#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1036#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1037#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1038#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1039#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1040 1041#define RETRY_LIMIT_SHORT_SHIFT 8 1042#define RETRY_LIMIT_LONG_SHIFT 0 1043 1044#define _DARF_RC1(x) ((x) & 0x1F) 1045#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1046#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1047#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1048#define _DARF_RC5(x) ((x) & 0x1F) 1049#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1050#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1051#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1052 1053#define _RARF_RC1(x) ((x) & 0x1F) 1054#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1055#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1056#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1057#define _RARF_RC5(x) ((x) & 0x1F) 1058#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1059#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1060#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1061 1062#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1063#define AC_PARAM_ECW_MAX_OFFSET 12 1064#define AC_PARAM_ECW_MIN_OFFSET 8 1065#define AC_PARAM_AIFS_OFFSET 0 1066 1067#define _AIFS(x) (x) 1068#define _ECW_MAX_MIN(x) ((x) << 8) 1069#define _TXOP_LIMIT(x) ((x) << 16) 1070 1071#define _BCNIFS(x) ((x) & 0xFF) 1072#define _BCNECW(x) ((((x) & 0xF)) << 8) 1073 1074#define _LRL(x) ((x) & 0x3F) 1075#define _SRL(x) (((x) & 0x3F) << 8) 1076 1077#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1078#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1079 1080#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1081#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1082 1083#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1084 1085#define DIS_EDCA_CNT_DWN BIT(11) 1086 1087#define EN_MBSSID BIT(1) 1088#define EN_TXBCN_RPT BIT(2) 1089#define EN_BCN_FUNCTION BIT(3) 1090 1091#define TSFTR_RST BIT(0) 1092#define TSFTR1_RST BIT(1) 1093 1094#define STOP_BCNQ BIT(6) 1095 1096#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1097#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1098 1099#define ACMHW_HWEN BIT(0) 1100#define ACMHW_BEQEN BIT(1) 1101#define ACMHW_VIQEN BIT(2) 1102#define ACMHW_VOQEN BIT(3) 1103#define ACMHW_BEQSTATUS BIT(4) 1104#define ACMHW_VIQSTATUS BIT(5) 1105#define ACMHW_VOQSTATUS BIT(6) 1106 1107#define APSDOFF BIT(6) 1108#define APSDOFF_STATUS BIT(7) 1109 1110#define BW_20MHZ BIT(2) 1111 1112#define RATE_BITMAP_ALL 0xFFFFF 1113 1114#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1115 1116#define TSFRST BIT(0) 1117#define DIS_GCLK BIT(1) 1118#define PAD_SEL BIT(2) 1119#define PWR_ST BIT(6) 1120#define PWRBIT_OW_EN BIT(7) 1121#define ACRC BIT(8) 1122#define CFENDFORM BIT(9) 1123#define ICV BIT(10) 1124 1125#define AAP BIT(0) 1126#define APM BIT(1) 1127#define AM BIT(2) 1128#define AB BIT(3) 1129#define ADD3 BIT(4) 1130#define APWRMGT BIT(5) 1131#define CBSSID BIT(6) 1132#define CBSSID_DATA BIT(6) 1133#define CBSSID_BCN BIT(7) 1134#define ACRC32 BIT(8) 1135#define AICV BIT(9) 1136#define ADF BIT(11) 1137#define ACF BIT(12) 1138#define AMF BIT(13) 1139#define HTC_LOC_CTRL BIT(14) 1140#define UC_DATA_EN BIT(16) 1141#define BM_DATA_EN BIT(17) 1142#define MFBEN BIT(22) 1143#define LSIGEN BIT(23) 1144#define ENMBID BIT(24) 1145#define APP_BASSN BIT(27) 1146#define APP_PHYSTS BIT(28) 1147#define APP_ICV BIT(29) 1148#define APP_MIC BIT(30) 1149#define APP_FCS BIT(31) 1150 1151#define _MIN_SPACE(x) ((x) & 0x7) 1152#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1153 1154#define RXERR_TYPE_OFDM_PPDU 0 1155#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1156#define RXERR_TYPE_OFDM_MPDU_OK 2 1157#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1158#define RXERR_TYPE_CCK_PPDU 4 1159#define RXERR_TYPE_CCK_FALSE_ALARM 5 1160#define RXERR_TYPE_CCK_MPDU_OK 6 1161#define RXERR_TYPE_CCK_MPDU_FAIL 7 1162#define RXERR_TYPE_HT_PPDU 8 1163#define RXERR_TYPE_HT_FALSE_ALARM 9 1164#define RXERR_TYPE_HT_MPDU_TOTAL 10 1165#define RXERR_TYPE_HT_MPDU_OK 11 1166#define RXERR_TYPE_HT_MPDU_FAIL 12 1167#define RXERR_TYPE_RX_FULL_DROP 15 1168 1169#define RXERR_COUNTER_MASK 0xFFFFF 1170#define RXERR_RPT_RST BIT(27) 1171#define _RXERR_RPT_SEL(type) ((type) << 28) 1172 1173#define SCR_TXUSEDK BIT(0) 1174#define SCR_RXUSEDK BIT(1) 1175#define SCR_TXENCENABLE BIT(2) 1176#define SCR_RXDECENABLE BIT(3) 1177#define SCR_SKBYA2 BIT(4) 1178#define SCR_NOSKMC BIT(5) 1179#define SCR_TXBCUSEDK BIT(6) 1180#define SCR_RXBCUSEDK BIT(7) 1181 1182#define USB_IS_HIGH_SPEED 0 1183#define USB_IS_FULL_SPEED 1 1184#define USB_SPEED_MASK BIT(5) 1185 1186#define USB_NORMAL_SIE_EP_MASK 0xF 1187#define USB_NORMAL_SIE_EP_SHIFT 4 1188 1189#define USB_TEST_EP_MASK 0x30 1190#define USB_TEST_EP_SHIFT 4 1191 1192#define USB_AGG_EN BIT(3) 1193 1194#define MAC_ADDR_LEN 6 1195#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1196 1197#define POLLING_LLT_THRESHOLD 20 1198#define POLLING_READY_TIMEOUT_COUNT 1000 1199 1200#define MAX_MSS_DENSITY_2T 0x13 1201#define MAX_MSS_DENSITY_1T 0x0A 1202 1203#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1204#define EPROM_CMD_CONFIG 0x3 1205#define EPROM_CMD_LOAD 1 1206 1207#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1208 1209#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1210 1211#define RPMAC_RESET 0x100 1212#define RPMAC_TXSTART 0x104 1213#define RPMAC_TXLEGACYSIG 0x108 1214#define RPMAC_TXHTSIG1 0x10c 1215#define RPMAC_TXHTSIG2 0x110 1216#define RPMAC_PHYDEBUG 0x114 1217#define RPMAC_TXPACKETNUM 0x118 1218#define RPMAC_TXIDLE 0x11c 1219#define RPMAC_TXMACHEADER0 0x120 1220#define RPMAC_TXMACHEADER1 0x124 1221#define RPMAC_TXMACHEADER2 0x128 1222#define RPMAC_TXMACHEADER3 0x12c 1223#define RPMAC_TXMACHEADER4 0x130 1224#define RPMAC_TXMACHEADER5 0x134 1225#define RPMAC_TXDADATYPE 0x138 1226#define RPMAC_TXRANDOMSEED 0x13c 1227#define RPMAC_CCKPLCPPREAMBLE 0x140 1228#define RPMAC_CCKPLCPHEADER 0x144 1229#define RPMAC_CCKCRC16 0x148 1230#define RPMAC_OFDMRXCRC32OK 0x170 1231#define RPMAC_OFDMRXCRC32ER 0x174 1232#define RPMAC_OFDMRXPARITYER 0x178 1233#define RPMAC_OFDMRXCRC8ER 0x17c 1234#define RPMAC_CCKCRXRC16ER 0x180 1235#define RPMAC_CCKCRXRC32ER 0x184 1236#define RPMAC_CCKCRXRC32OK 0x188 1237#define RPMAC_TXSTATUS 0x18c 1238 1239#define RFPGA0_RFMOD 0x800 1240 1241#define RFPGA0_TXINFO 0x804 1242#define RFPGA0_PSDFUNCTION 0x808 1243 1244#define RFPGA0_TXGAINSTAGE 0x80c 1245 1246#define RFPGA0_RFTIMING1 0x810 1247#define RFPGA0_RFTIMING2 0x814 1248 1249#define RFPGA0_XA_HSSIPARAMETER1 0x820 1250#define RFPGA0_XA_HSSIPARAMETER2 0x824 1251#define RFPGA0_XB_HSSIPARAMETER1 0x828 1252#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1253 1254#define RFPGA0_XA_LSSIPARAMETER 0x840 1255#define RFPGA0_XB_LSSIPARAMETER 0x844 1256 1257#define RFPGA0_RFWAKEUPPARAMETER 0x850 1258#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1259 1260#define RFPGA0_XAB_SWITCHCONTROL 0x858 1261#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1262 1263#define RFPGA0_XA_RFINTERFACEOE 0x860 1264#define RFPGA0_XB_RFINTERFACEOE 0x864 1265 1266#define RFPGA0_XAB_RFINTERFACESW 0x870 1267#define RFPGA0_XCD_RFINTERFACESW 0x874 1268 1269#define RFPGA0_XAB_RFPARAMETER 0x878 1270#define RFPGA0_XCD_RFPARAMETER 0x87c 1271 1272#define RFPGA0_ANALOGPARAMETER1 0x880 1273#define RFPGA0_ANALOGPARAMETER2 0x884 1274#define RFPGA0_ANALOGPARAMETER3 0x888 1275#define RFPGA0_ANALOGPARAMETER4 0x88c 1276 1277#define RFPGA0_XA_LSSIREADBACK 0x8a0 1278#define RFPGA0_XB_LSSIREADBACK 0x8a4 1279#define RFPGA0_XC_LSSIREADBACK 0x8a8 1280#define RFPGA0_XD_LSSIREADBACK 0x8ac 1281 1282#define RFPGA0_PSDREPORT 0x8b4 1283#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1284#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1285#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1286#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1287 1288#define RFPGA1_RFMOD 0x900 1289 1290#define RFPGA1_TXBLOCK 0x904 1291#define RFPGA1_DEBUGSELECT 0x908 1292#define RFPGA1_TXINFO 0x90c 1293 1294#define RCCK0_SYSTEM 0xa00 1295 1296#define RCCK0_AFESETTING 0xa04 1297#define RCCK0_CCA 0xa08 1298 1299#define RCCK0_RXAGC1 0xa0c 1300#define RCCK0_RXAGC2 0xa10 1301 1302#define RCCK0_RXHP 0xa14 1303 1304#define RCCK0_DSPPARAMETER1 0xa18 1305#define RCCK0_DSPPARAMETER2 0xa1c 1306 1307#define RCCK0_TXFILTER1 0xa20 1308#define RCCK0_TXFILTER2 0xa24 1309#define RCCK0_DEBUGPORT 0xa28 1310#define RCCK0_FALSEALARMREPORT 0xa2c 1311#define RCCK0_TRSSIREPORT 0xa50 1312#define RCCK0_RXREPORT 0xa54 1313#define RCCK0_FACOUNTERLOWER 0xa5c 1314#define RCCK0_FACOUNTERUPPER 0xa58 1315 1316#define ROFDM0_LSTF 0xc00 1317 1318#define ROFDM0_TRXPATHENABLE 0xc04 1319#define ROFDM0_TRMUXPAR 0xc08 1320#define ROFDM0_TRSWISOLATION 0xc0c 1321 1322#define ROFDM0_XARXAFE 0xc10 1323#define ROFDM0_XARXIQIMBALANCE 0xc14 1324#define ROFDM0_XBRXAFE 0xc18 1325#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1326#define ROFDM0_XCRXAFE 0xc20 1327#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1328#define ROFDM0_XDRXAFE 0xc28 1329#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1330 1331#define ROFDM0_RXDETECTOR1 0xc30 1332#define ROFDM0_RXDETECTOR2 0xc34 1333#define ROFDM0_RXDETECTOR3 0xc38 1334#define ROFDM0_RXDETECTOR4 0xc3c 1335 1336#define ROFDM0_RXDSP 0xc40 1337#define ROFDM0_CFOANDDAGC 0xc44 1338#define ROFDM0_CCADROPTHRESHOLD 0xc48 1339#define ROFDM0_ECCATHRESHOLD 0xc4c 1340 1341#define ROFDM0_XAAGCCORE1 0xc50 1342#define ROFDM0_XAAGCCORE2 0xc54 1343#define ROFDM0_XBAGCCORE1 0xc58 1344#define ROFDM0_XBAGCCORE2 0xc5c 1345#define ROFDM0_XCAGCCORE1 0xc60 1346#define ROFDM0_XCAGCCORE2 0xc64 1347#define ROFDM0_XDAGCCORE1 0xc68 1348#define ROFDM0_XDAGCCORE2 0xc6c 1349 1350#define ROFDM0_AGCPARAMETER1 0xc70 1351#define ROFDM0_AGCPARAMETER2 0xc74 1352#define ROFDM0_AGCRSSITABLE 0xc78 1353#define ROFDM0_HTSTFAGC 0xc7c 1354 1355#define ROFDM0_XATXIQIMBALANCE 0xc80 1356#define ROFDM0_XATXAFE 0xc84 1357#define ROFDM0_XBTXIQIMBALANCE 0xc88 1358#define ROFDM0_XBTXAFE 0xc8c 1359#define ROFDM0_XCTXIQIMBALANCE 0xc90 1360#define ROFDM0_XCTXAFE 0xc94 1361#define ROFDM0_XDTXIQIMBALANCE 0xc98 1362#define ROFDM0_XDTXAFE 0xc9c 1363 1364#define ROFDM0_RXIQEXTANTA 0xca0 1365 1366#define ROFDM0_RXHPPARAMETER 0xce0 1367#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1368#define ROFDM0_FRAMESYNC 0xcf0 1369#define ROFDM0_DFSREPORT 0xcf4 1370#define ROFDM0_TXCOEFF1 0xca4 1371#define ROFDM0_TXCOEFF2 0xca8 1372#define ROFDM0_TXCOEFF3 0xcac 1373#define ROFDM0_TXCOEFF4 0xcb0 1374#define ROFDM0_TXCOEFF5 0xcb4 1375#define ROFDM0_TXCOEFF6 0xcb8 1376 1377#define ROFDM1_LSTF 0xd00 1378#define ROFDM1_TRXPATHENABLE 0xd04 1379 1380#define ROFDM1_CF0 0xd08 1381#define ROFDM1_CSI1 0xd10 1382#define ROFDM1_SBD 0xd14 1383#define ROFDM1_CSI2 0xd18 1384#define ROFDM1_CFOTRACKING 0xd2c 1385#define ROFDM1_TRXMESAURE1 0xd34 1386#define ROFDM1_INTFDET 0xd3c 1387#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1388#define ROFDM1_PSEUDONOISESTATECD 0xd54 1389#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1390 1391#define ROFDM_PHYCOUNTER1 0xda0 1392#define ROFDM_PHYCOUNTER2 0xda4 1393#define ROFDM_PHYCOUNTER3 0xda8 1394 1395#define ROFDM_SHORTCFOAB 0xdac 1396#define ROFDM_SHORTCFOCD 0xdb0 1397#define ROFDM_LONGCFOAB 0xdb4 1398#define ROFDM_LONGCFOCD 0xdb8 1399#define ROFDM_TAILCF0AB 0xdbc 1400#define ROFDM_TAILCF0CD 0xdc0 1401#define ROFDM_PWMEASURE1 0xdc4 1402#define ROFDM_PWMEASURE2 0xdc8 1403#define ROFDM_BWREPORT 0xdcc 1404#define ROFDM_AGCREPORT 0xdd0 1405#define ROFDM_RXSNR 0xdd4 1406#define ROFDM_RXEVMCSI 0xdd8 1407#define ROFDM_SIGREPORT 0xddc 1408 1409#define RTXAGC_A_RATE18_06 0xe00 1410#define RTXAGC_A_RATE54_24 0xe04 1411#define RTXAGC_A_CCK1_MCS32 0xe08 1412#define RTXAGC_A_MCS03_MCS00 0xe10 1413#define RTXAGC_A_MCS07_MCS04 0xe14 1414#define RTXAGC_A_MCS11_MCS08 0xe18 1415#define RTXAGC_A_MCS15_MCS12 0xe1c 1416 1417#define RTXAGC_B_RATE18_06 0x830 1418#define RTXAGC_B_RATE54_24 0x834 1419#define RTXAGC_B_CCK1_55_MCS32 0x838 1420#define RTXAGC_B_MCS03_MCS00 0x83c 1421#define RTXAGC_B_MCS07_MCS04 0x848 1422#define RTXAGC_B_MCS11_MCS08 0x84c 1423#define RTXAGC_B_MCS15_MCS12 0x868 1424#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1425 1426#define RZEBRA1_HSSIENABLE 0x0 1427#define RZEBRA1_TRXENABLE1 0x1 1428#define RZEBRA1_TRXENABLE2 0x2 1429#define RZEBRA1_AGC 0x4 1430#define RZEBRA1_CHARGEPUMP 0x5 1431#define RZEBRA1_CHANNEL 0x7 1432 1433#define RZEBRA1_TXGAIN 0x8 1434#define RZEBRA1_TXLPF 0x9 1435#define RZEBRA1_RXLPF 0xb 1436#define RZEBRA1_RXHPFCORNER 0xc 1437 1438#define RGLOBALCTRL 0 1439#define RRTL8256_TXLPF 19 1440#define RRTL8256_RXLPF 11 1441#define RRTL8258_TXLPF 0x11 1442#define RRTL8258_RXLPF 0x13 1443#define RRTL8258_RSSILPF 0xa 1444 1445#define RF_AC 0x00 1446 1447#define RF_IQADJ_G1 0x01 1448#define RF_IQADJ_G2 0x02 1449#define RF_POW_TRSW 0x05 1450 1451#define RF_GAIN_RX 0x06 1452#define RF_GAIN_TX 0x07 1453 1454#define RF_TXM_IDAC 0x08 1455#define RF_BS_IQGEN 0x0F 1456 1457#define RF_MODE1 0x10 1458#define RF_MODE2 0x11 1459 1460#define RF_RX_AGC_HP 0x12 1461#define RF_TX_AGC 0x13 1462#define RF_BIAS 0x14 1463#define RF_IPA 0x15 1464#define RF_POW_ABILITY 0x17 1465#define RF_MODE_AG 0x18 1466#define RRFCHANNEL 0x18 1467#define RF_CHNLBW 0x18 1468#define RF_TOP 0x19 1469 1470#define RF_RX_G1 0x1A 1471#define RF_RX_G2 0x1B 1472 1473#define RF_RX_BB2 0x1C 1474#define RF_RX_BB1 0x1D 1475 1476#define RF_RCK1 0x1E 1477#define RF_RCK2 0x1F 1478 1479#define RF_TX_G1 0x20 1480#define RF_TX_G2 0x21 1481#define RF_TX_G3 0x22 1482 1483#define RF_TX_BB1 0x23 1484#define RF_T_METER 0x24 1485 1486#define RF_SYN_G1 0x25 1487#define RF_SYN_G2 0x26 1488#define RF_SYN_G3 0x27 1489#define RF_SYN_G4 0x28 1490#define RF_SYN_G5 0x29 1491#define RF_SYN_G6 0x2A 1492#define RF_SYN_G7 0x2B 1493#define RF_SYN_G8 0x2C 1494 1495#define RF_RCK_OS 0x30 1496#define RF_TXPA_G1 0x31 1497#define RF_TXPA_G2 0x32 1498#define RF_TXPA_G3 0x33 1499 1500#define BBBRESETB 0x100 1501#define BGLOBALRESETB 0x200 1502#define BOFDMTXSTART 0x4 1503#define BCCKTXSTART 0x8 1504#define BCRC32DEBUG 0x100 1505#define BPMACLOOPBACK 0x10 1506#define BTXLSIG 0xffffff 1507#define BOFDMTXRATE 0xf 1508#define BOFDMTXRESERVED 0x10 1509#define BOFDMTXLENGTH 0x1ffe0 1510#define BOFDMTXPARITY 0x20000 1511#define BTXHTSIG1 0xffffff 1512#define BTXHTMCSRATE 0x7f 1513#define BTXHTBW 0x80 1514#define BTXHTLENGTH 0xffff00 1515#define BTXHTSIG2 0xffffff 1516#define BTXHTSMOOTHING 0x1 1517#define BTXHTSOUNDING 0x2 1518#define BTXHTRESERVED 0x4 1519#define BTXHTAGGREATION 0x8 1520#define BTXHTSTBC 0x30 1521#define BTXHTADVANCECODING 0x40 1522#define BTXHTSHORTGI 0x80 1523#define BTXHTNUMBERHT_LTF 0x300 1524#define BTXHTCRC8 0x3fc00 1525#define BCOUNTERRESET 0x10000 1526#define BNUMOFOFDMTX 0xffff 1527#define BNUMOFCCKTX 0xffff0000 1528#define BTXIDLEINTERVAL 0xffff 1529#define BOFDMSERVICE 0xffff0000 1530#define BTXMACHEADER 0xffffffff 1531#define BTXDATAINIT 0xff 1532#define BTXHTMODE 0x100 1533#define BTXDATATYPE 0x30000 1534#define BTXRANDOMSEED 0xffffffff 1535#define BCCKTXPREAMBLE 0x1 1536#define BCCKTXSFD 0xffff0000 1537#define BCCKTXSIG 0xff 1538#define BCCKTXSERVICE 0xff00 1539#define BCCKLENGTHEXT 0x8000 1540#define BCCKTXLENGHT 0xffff0000 1541#define BCCKTXCRC16 0xffff 1542#define BCCKTXSTATUS 0x1 1543#define BOFDMTXSTATUS 0x2 1544#define IS_BB_REG_OFFSET_92S(_offset) \ 1545 ((_offset >= 0x800) && (_offset <= 0xfff)) 1546 1547#define BRFMOD 0x1 1548#define BJAPANMODE 0x2 1549#define BCCKTXSC 0x30 1550#define BCCKEN 0x1000000 1551#define BOFDMEN 0x2000000 1552 1553#define BOFDMRXADCPHASE 0x10000 1554#define BOFDMTXDACPHASE 0x40000 1555#define BXATXAGC 0x3f 1556 1557#define BXBTXAGC 0xf00 1558#define BXCTXAGC 0xf000 1559#define BXDTXAGC 0xf0000 1560 1561#define BPASTART 0xf0000000 1562#define BTRSTART 0x00f00000 1563#define BRFSTART 0x0000f000 1564#define BBBSTART 0x000000f0 1565#define BBBCCKSTART 0x0000000f 1566#define BPAEND 0xf 1567#define BTREND 0x0f000000 1568#define BRFEND 0x000f0000 1569#define BCCAMASK 0x000000f0 1570#define BR2RCCAMASK 0x00000f00 1571#define BHSSI_R2TDELAY 0xf8000000 1572#define BHSSI_T2RDELAY 0xf80000 1573#define BCONTXHSSI 0x400 1574#define BIGFROMCCK 0x200 1575#define BAGCADDRESS 0x3f 1576#define BRXHPTX 0x7000 1577#define BRXHP2RX 0x38000 1578#define BRXHPCCKINI 0xc0000 1579#define BAGCTXCODE 0xc00000 1580#define BAGCRXCODE 0x300000 1581 1582#define B3WIREDATALENGTH 0x800 1583#define B3WIREADDREAALENGTH 0x400 1584 1585#define B3WIRERFPOWERDOWN 0x1 1586#define B5GPAPEPOLARITY 0x40000000 1587#define B2GPAPEPOLARITY 0x80000000 1588#define BRFSW_TXDEFAULTANT 0x3 1589#define BRFSW_TXOPTIONANT 0x30 1590#define BRFSW_RXDEFAULTANT 0x300 1591#define BRFSW_RXOPTIONANT 0x3000 1592#define BRFSI_3WIREDATA 0x1 1593#define BRFSI_3WIRECLOCK 0x2 1594#define BRFSI_3WIRELOAD 0x4 1595#define BRFSI_3WIRERW 0x8 1596#define BRFSI_3WIRE 0xf 1597 1598#define BRFSI_RFENV 0x10 1599 1600#define BRFSI_TRSW 0x20 1601#define BRFSI_TRSWB 0x40 1602#define BRFSI_ANTSW 0x100 1603#define BRFSI_ANTSWB 0x200 1604#define BRFSI_PAPE 0x400 1605#define BRFSI_PAPE5G 0x800 1606#define BBANDSELECT 0x1 1607#define BHTSIG2_GI 0x80 1608#define BHTSIG2_SMOOTHING 0x01 1609#define BHTSIG2_SOUNDING 0x02 1610#define BHTSIG2_AGGREATON 0x08 1611#define BHTSIG2_STBC 0x30 1612#define BHTSIG2_ADVCODING 0x40 1613#define BHTSIG2_NUMOFHTLTF 0x300 1614#define BHTSIG2_CRC8 0x3fc 1615#define BHTSIG1_MCS 0x7f 1616#define BHTSIG1_BANDWIDTH 0x80 1617#define BHTSIG1_HTLENGTH 0xffff 1618#define BLSIG_RATE 0xf 1619#define BLSIG_RESERVED 0x10 1620#define BLSIG_LENGTH 0x1fffe 1621#define BLSIG_PARITY 0x20 1622#define BCCKRXPHASE 0x4 1623 1624#define BLSSIREADADDRESS 0x7f800000 1625#define BLSSIREADEDGE 0x80000000 1626 1627#define BLSSIREADBACKDATA 0xfffff 1628 1629#define BLSSIREADOKFLAG 0x1000 1630#define BCCKSAMPLERATE 0x8 1631#define BREGULATOR0STANDBY 0x1 1632#define BREGULATORPLLSTANDBY 0x2 1633#define BREGULATOR1STANDBY 0x4 1634#define BPLLPOWERUP 0x8 1635#define BDPLLPOWERUP 0x10 1636#define BDA10POWERUP 0x20 1637#define BAD7POWERUP 0x200 1638#define BDA6POWERUP 0x2000 1639#define BXTALPOWERUP 0x4000 1640#define B40MDCLKPOWERUP 0x8000 1641#define BDA6DEBUGMODE 0x20000 1642#define BDA6SWING 0x380000 1643 1644#define BADCLKPHASE 0x4000000 1645#define B80MCLKDELAY 0x18000000 1646#define BAFEWATCHDOGENABLE 0x20000000 1647 1648#define BXTALCAP01 0xc0000000 1649#define BXTALCAP23 0x3 1650#define BXTALCAP92X 0x0f000000 1651#define BXTALCAP 0x0f000000 1652 1653#define BINTDIFCLKENABLE 0x400 1654#define BEXTSIGCLKENABLE 0x800 1655#define BBANDGAP_MBIAS_POWERUP 0x10000 1656#define BAD11SH_GAIN 0xc0000 1657#define BAD11NPUT_RANGE 0x700000 1658#define BAD110P_CURRENT 0x3800000 1659#define BLPATH_LOOPBACK 0x4000000 1660#define BQPATH_LOOPBACK 0x8000000 1661#define BAFE_LOOPBACK 0x10000000 1662#define BDA10_SWING 0x7e0 1663#define BDA10_REVERSE 0x800 1664#define BDA_CLK_SOURCE 0x1000 1665#define BDA7INPUT_RANGE 0x6000 1666#define BDA7_GAIN 0x38000 1667#define BDA7OUTPUT_CM_MODE 0x40000 1668#define BDA7INPUT_CM_MODE 0x380000 1669#define BDA7CURRENT 0xc00000 1670#define BREGULATOR_ADJUST 0x7000000 1671#define BAD11POWERUP_ATTX 0x1 1672#define BDA10PS_ATTX 0x10 1673#define BAD11POWERUP_ATRX 0x100 1674#define BDA10PS_ATRX 0x1000 1675#define BCCKRX_AGC_FORMAT 0x200 1676#define BPSDFFT_SAMPLE_POINT 0xc000 1677#define BPSD_AVERAGE_NUM 0x3000 1678#define BIQPATH_CONTROL 0xc00 1679#define BPSD_FREQ 0x3ff 1680#define BPSD_ANTENNA_PATH 0x30 1681#define BPSD_IQ_SWITCH 0x40 1682#define BPSD_RX_TRIGGER 0x400000 1683#define BPSD_TX_TRIGGER 0x80000000 1684#define BPSD_SINE_TONE_SCALE 0x7f000000 1685#define BPSD_REPORT 0xffff 1686 1687#define BOFDM_TXSC 0x30000000 1688#define BCCK_TXON 0x1 1689#define BOFDM_TXON 0x2 1690#define BDEBUG_PAGE 0xfff 1691#define BDEBUG_ITEM 0xff 1692#define BANTL 0x10 1693#define BANT_NONHT 0x100 1694#define BANT_HT1 0x1000 1695#define BANT_HT2 0x10000 1696#define BANT_HT1S1 0x100000 1697#define BANT_NONHTS1 0x1000000 1698 1699#define BCCK_BBMODE 0x3 1700#define BCCK_TXPOWERSAVING 0x80 1701#define BCCK_RXPOWERSAVING 0x40 1702 1703#define BCCK_SIDEBAND 0x10 1704 1705#define BCCK_SCRAMBLE 0x8 1706#define BCCK_ANTDIVERSITY 0x8000 1707#define BCCK_CARRIER_RECOVERY 0x4000 1708#define BCCK_TXRATE 0x3000 1709#define BCCK_DCCANCEL 0x0800 1710#define BCCK_ISICANCEL 0x0400 1711#define BCCK_MATCH_FILTER 0x0200 1712#define BCCK_EQUALIZER 0x0100 1713#define BCCK_PREAMBLE_DETECT 0x800000 1714#define BCCK_FAST_FALSECCA 0x400000 1715#define BCCK_CH_ESTSTART 0x300000 1716#define BCCK_CCA_COUNT 0x080000 1717#define BCCK_CS_LIM 0x070000 1718#define BCCK_BIST_MODE 0x80000000 1719#define BCCK_CCAMASK 0x40000000 1720#define BCCK_TX_DAC_PHASE 0x4 1721#define BCCK_RX_ADC_PHASE 0x20000000 1722#define BCCKR_CP_MODE 0x0100 1723#define BCCK_TXDC_OFFSET 0xf0 1724#define BCCK_RXDC_OFFSET 0xf 1725#define BCCK_CCA_MODE 0xc000 1726#define BCCK_FALSECS_LIM 0x3f00 1727#define BCCK_CS_RATIO 0xc00000 1728#define BCCK_CORGBIT_SEL 0x300000 1729#define BCCK_PD_LIM 0x0f0000 1730#define BCCK_NEWCCA 0x80000000 1731#define BCCK_RXHP_OF_IG 0x8000 1732#define BCCK_RXIG 0x7f00 1733#define BCCK_LNA_POLARITY 0x800000 1734#define BCCK_RX1ST_BAIN 0x7f0000 1735#define BCCK_RF_EXTEND 0x20000000 1736#define BCCK_RXAGC_SATLEVEL 0x1f000000 1737#define BCCK_RXAGC_SATCOUNT 0xe0 1738#define BCCKRXRFSETTLE 0x1f 1739#define BCCK_FIXED_RXAGC 0x8000 1740#define BCCK_ANTENNA_POLARITY 0x2000 1741#define BCCK_TXFILTER_TYPE 0x0c00 1742#define BCCK_RXAGC_REPORTTYPE 0x0300 1743#define BCCK_RXDAGC_EN 0x80000000 1744#define BCCK_RXDAGC_PERIOD 0x20000000 1745#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1746#define BCCK_TIMING_RECOVERY 0x800000 1747#define BCCK_TXC0 0x3f0000 1748#define BCCK_TXC1 0x3f000000 1749#define BCCK_TXC2 0x3f 1750#define BCCK_TXC3 0x3f00 1751#define BCCK_TXC4 0x3f0000 1752#define BCCK_TXC5 0x3f000000 1753#define BCCK_TXC6 0x3f 1754#define BCCK_TXC7 0x3f00 1755#define BCCK_DEBUGPORT 0xff0000 1756#define BCCK_DAC_DEBUG 0x0f000000 1757#define BCCK_FALSEALARM_ENABLE 0x8000 1758#define BCCK_FALSEALARM_READ 0x4000 1759#define BCCK_TRSSI 0x7f 1760#define BCCK_RXAGC_REPORT 0xfe 1761#define BCCK_RXREPORT_ANTSEL 0x80000000 1762#define BCCK_RXREPORT_MFOFF 0x40000000 1763#define BCCK_RXREPORT_SQLOSS 0x20000000 1764#define BCCK_RXREPORT_PKTLOSS 0x10000000 1765#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1766#define BCCK_RXREPORT_RATEERROR 0x04000000 1767#define BCCK_RXREPORT_RXRATE 0x03000000 1768#define BCCK_RXFA_COUNTER_LOWER 0xff 1769#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1770#define BCCK_RXHPAGC_START 0xe000 1771#define BCCK_RXHPAGC_FINAL 0x1c00 1772#define BCCK_RXFALSEALARM_ENABLE 0x8000 1773#define BCCK_FACOUNTER_FREEZE 0x4000 1774#define BCCK_TXPATH_SEL 0x10000000 1775#define BCCK_DEFAULT_RXPATH 0xc000000 1776#define BCCK_OPTION_RXPATH 0x3000000 1777 1778#define BNUM_OFSTF 0x3 1779#define BSHIFT_L 0xc0 1780#define BGI_TH 0xc 1781#define BRXPATH_A 0x1 1782#define BRXPATH_B 0x2 1783#define BRXPATH_C 0x4 1784#define BRXPATH_D 0x8 1785#define BTXPATH_A 0x1 1786#define BTXPATH_B 0x2 1787#define BTXPATH_C 0x4 1788#define BTXPATH_D 0x8 1789#define BTRSSI_FREQ 0x200 1790#define BADC_BACKOFF 0x3000 1791#define BDFIR_BACKOFF 0xc000 1792#define BTRSSI_LATCH_PHASE 0x10000 1793#define BRX_LDC_OFFSET 0xff 1794#define BRX_QDC_OFFSET 0xff00 1795#define BRX_DFIR_MODE 0x1800000 1796#define BRX_DCNF_TYPE 0xe000000 1797#define BRXIQIMB_A 0x3ff 1798#define BRXIQIMB_B 0xfc00 1799#define BRXIQIMB_C 0x3f0000 1800#define BRXIQIMB_D 0xffc00000 1801#define BDC_DC_NOTCH 0x60000 1802#define BRXNB_NOTCH 0x1f000000 1803#define BPD_TH 0xf 1804#define BPD_TH_OPT2 0xc000 1805#define BPWED_TH 0x700 1806#define BIFMF_WIN_L 0x800 1807#define BPD_OPTION 0x1000 1808#define BMF_WIN_L 0xe000 1809#define BBW_SEARCH_L 0x30000 1810#define BWIN_ENH_L 0xc0000 1811#define BBW_TH 0x700000 1812#define BED_TH2 0x3800000 1813#define BBW_OPTION 0x4000000 1814#define BRADIO_TH 0x18000000 1815#define BWINDOW_L 0xe0000000 1816#define BSBD_OPTION 0x1 1817#define BFRAME_TH 0x1c 1818#define BFS_OPTION 0x60 1819#define BDC_SLOPE_CHECK 0x80 1820#define BFGUARD_COUNTER_DC_L 0xe00 1821#define BFRAME_WEIGHT_SHORT 0x7000 1822#define BSUB_TUNE 0xe00000 1823#define BFRAME_DC_LENGTH 0xe000000 1824#define BSBD_START_OFFSET 0x30000000 1825#define BFRAME_TH_2 0x7 1826#define BFRAME_GI2_TH 0x38 1827#define BGI2_SYNC_EN 0x40 1828#define BSARCH_SHORT_EARLY 0x300 1829#define BSARCH_SHORT_LATE 0xc00 1830#define BSARCH_GI2_LATE 0x70000 1831#define BCFOANTSUM 0x1 1832#define BCFOACC 0x2 1833#define BCFOSTARTOFFSET 0xc 1834#define BCFOLOOPBACK 0x70 1835#define BCFOSUMWEIGHT 0x80 1836#define BDAGCENABLE 0x10000 1837#define BTXIQIMB_A 0x3ff 1838#define BTXIQIMB_b 0xfc00 1839#define BTXIQIMB_C 0x3f0000 1840#define BTXIQIMB_D 0xffc00000 1841#define BTXIDCOFFSET 0xff 1842#define BTXIQDCOFFSET 0xff00 1843#define BTXDFIRMODE 0x10000 1844#define BTXPESUDO_NOISEON 0x4000000 1845#define BTXPESUDO_NOISE_A 0xff 1846#define BTXPESUDO_NOISE_B 0xff00 1847#define BTXPESUDO_NOISE_C 0xff0000 1848#define BTXPESUDO_NOISE_D 0xff000000 1849#define BCCA_DROPOPTION 0x20000 1850#define BCCA_DROPTHRES 0xfff00000 1851#define BEDCCA_H 0xf 1852#define BEDCCA_L 0xf0 1853#define BLAMBDA_ED 0x300 1854#define BRX_INITIALGAIN 0x7f 1855#define BRX_ANTDIV_EN 0x80 1856#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1857#define BRX_HIGHPOWER_FLOW 0x8000 1858#define BRX_AGC_FREEZE_THRES 0xc0000 1859#define BRX_FREEZESTEP_AGC1 0x300000 1860#define BRX_FREEZESTEP_AGC2 0xc00000 1861#define BRX_FREEZESTEP_AGC3 0x3000000 1862#define BRX_FREEZESTEP_AGC0 0xc000000 1863#define BRXRSSI_CMP_EN 0x10000000 1864#define BRXQUICK_AGCEN 0x20000000 1865#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1866#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1867#define BRX_AGCSHIFT 0x7f 1868#define BTRSW_TRI_ONLY 0x80 1869#define BPOWER_THRES 0x300 1870#define BRXAGC_EN 0x1 1871#define BRXAGC_TOGETHER_EN 0x2 1872#define BRXAGC_MIN 0x4 1873#define BRXHP_INI 0x7 1874#define BRXHP_TRLNA 0x70 1875#define BRXHP_RSSI 0x700 1876#define BRXHP_BBP1 0x7000 1877#define BRXHP_BBP2 0x70000 1878#define BRXHP_BBP3 0x700000 1879#define BRSSI_H 0x7f0000 1880#define BRSSI_GEN 0x7f000000 1881#define BRXSETTLE_TRSW 0x7 1882#define BRXSETTLE_LNA 0x38 1883#define BRXSETTLE_RSSI 0x1c0 1884#define BRXSETTLE_BBP 0xe00 1885#define BRXSETTLE_RXHP 0x7000 1886#define BRXSETTLE_ANTSW_RSSI 0x38000 1887#define BRXSETTLE_ANTSW 0xc0000 1888#define BRXPROCESS_TIME_DAGC 0x300000 1889#define BRXSETTLE_HSSI 0x400000 1890#define BRXPROCESS_TIME_BBPPW 0x800000 1891#define BRXANTENNA_POWER_SHIFT 0x3000000 1892#define BRSSI_TABLE_SELECT 0xc000000 1893#define BRXHP_FINAL 0x7000000 1894#define BRXHPSETTLE_BBP 0x7 1895#define BRXHTSETTLE_HSSI 0x8 1896#define BRXHTSETTLE_RXHP 0x70 1897#define BRXHTSETTLE_BBPPW 0x80 1898#define BRXHTSETTLE_IDLE 0x300 1899#define BRXHTSETTLE_RESERVED 0x1c00 1900#define BRXHT_RXHP_EN 0x8000 1901#define BRXAGC_FREEZE_THRES 0x30000 1902#define BRXAGC_TOGETHEREN 0x40000 1903#define BRXHTAGC_MIN 0x80000 1904#define BRXHTAGC_EN 0x100000 1905#define BRXHTDAGC_EN 0x200000 1906#define BRXHT_RXHP_BBP 0x1c00000 1907#define BRXHT_RXHP_FINAL 0xe0000000 1908#define BRXPW_RADIO_TH 0x3 1909#define BRXPW_RADIO_EN 0x4 1910#define BRXMF_HOLD 0x3800 1911#define BRXPD_DELAY_TH1 0x38 1912#define BRXPD_DELAY_TH2 0x1c0 1913#define BRXPD_DC_COUNT_MAX 0x600 1914#define BRXPD_DELAY_TH 0x8000 1915#define BRXPROCESS_DELAY 0xf0000 1916#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1917#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1918#define BRXSGI_GUARD_L 0xc000000 1919#define BRXSGI_SEARCH_L 0x30000000 1920#define BRXSGI_TH 0xc0000000 1921#define BDFSCNT0 0xff 1922#define BDFSCNT1 0xff00 1923#define BDFSFLAG 0xf0000 1924#define BMF_WEIGHT_SUM 0x300000 1925#define BMINIDX_TH 0x7f000000 1926#define BDAFORMAT 0x40000 1927#define BTXCH_EMU_ENABLE 0x01000000 1928#define BTRSW_ISOLATION_A 0x7f 1929#define BTRSW_ISOLATION_B 0x7f00 1930#define BTRSW_ISOLATION_C 0x7f0000 1931#define BTRSW_ISOLATION_D 0x7f000000 1932#define BEXT_LNA_GAIN 0x7c00 1933 1934#define BSTBC_EN 0x4 1935#define BANTENNA_MAPPING 0x10 1936#define BNSS 0x20 1937#define BCFO_ANTSUM_ID 0x200 1938#define BPHY_COUNTER_RESET 0x8000000 1939#define BCFO_REPORT_GET 0x4000000 1940#define BOFDM_CONTINUE_TX 0x10000000 1941#define BOFDM_SINGLE_CARRIER 0x20000000 1942#define BOFDM_SINGLE_TONE 0x40000000 1943#define BHT_DETECT 0x100 1944#define BCFOEN 0x10000 1945#define BCFOVALUE 0xfff00000 1946#define BSIGTONE_RE 0x3f 1947#define BSIGTONE_IM 0x7f00 1948#define BCOUNTER_CCA 0xffff 1949#define BCOUNTER_PARITYFAIL 0xffff0000 1950#define BCOUNTER_RATEILLEGAL 0xffff 1951#define BCOUNTER_CRC8FAIL 0xffff0000 1952#define BCOUNTER_MCSNOSUPPORT 0xffff 1953#define BCOUNTER_FASTSYNC 0xffff 1954#define BSHORTCFO 0xfff 1955#define BSHORTCFOT_LENGTH 12 1956#define BSHORTCFOF_LENGTH 11 1957#define BLONGCFO 0x7ff 1958#define BLONGCFOT_LENGTH 11 1959#define BLONGCFOF_LENGTH 11 1960#define BTAILCFO 0x1fff 1961#define BTAILCFOT_LENGTH 13 1962#define BTAILCFOF_LENGTH 12 1963#define BNOISE_EN_PWDB 0xffff 1964#define BCC_POWER_DB 0xffff0000 1965#define BMOISE_PWDB 0xffff 1966#define BPOWERMEAST_LENGTH 10 1967#define BPOWERMEASF_LENGTH 3 1968#define BRX_HT_BW 0x1 1969#define BRXSC 0x6 1970#define BRX_HT 0x8 1971#define BNB_INTF_DET_ON 0x1 1972#define BINTF_WIN_LEN_CFG 0x30 1973#define BNB_INTF_TH_CFG 0x1c0 1974#define BRFGAIN 0x3f 1975#define BTABLESEL 0x40 1976#define BTRSW 0x80 1977#define BRXSNR_A 0xff 1978#define BRXSNR_B 0xff00 1979#define BRXSNR_C 0xff0000 1980#define BRXSNR_D 0xff000000 1981#define BSNR_EVMT_LENGTH 8 1982#define BSNR_EVMF_LENGTH 1 1983#define BCSI1ST 0xff 1984#define BCSI2ND 0xff00 1985#define BRXEVM1ST 0xff0000 1986#define BRXEVM2ND 0xff000000 1987#define BSIGEVM 0xff 1988#define BPWDB 0xff00 1989#define BSGIEN 0x10000 1990 1991#define BSFACTOR_QMA1 0xf 1992#define BSFACTOR_QMA2 0xf0 1993#define BSFACTOR_QMA3 0xf00 1994#define BSFACTOR_QMA4 0xf000 1995#define BSFACTOR_QMA5 0xf0000 1996#define BSFACTOR_QMA6 0xf0000 1997#define BSFACTOR_QMA7 0xf00000 1998#define BSFACTOR_QMA8 0xf000000 1999#define BSFACTOR_QMA9 0xf0000000 2000#define BCSI_SCHEME 0x100000
2001 2002#define BNOISE_LVL_TOP_SET 0x3 2003#define BCHSMOOTH 0x4 2004#define BCHSMOOTH_CFG1 0x38 2005#define BCHSMOOTH_CFG2 0x1c0 2006#define BCHSMOOTH_CFG3 0xe00 2007#define BCHSMOOTH_CFG4 0x7000 2008#define BMRCMODE 0x800000 2009#define BTHEVMCFG 0x7000000 2010 2011#define BLOOP_FIT_TYPE 0x1 2012#define BUPD_CFO 0x40 2013#define BUPD_CFO_OFFDATA 0x80 2014#define BADV_UPD_CFO 0x100 2015#define BADV_TIME_CTRL 0x800 2016#define BUPD_CLKO 0x1000 2017#define BFC 0x6000 2018#define BTRACKING_MODE 0x8000 2019#define BPHCMP_ENABLE 0x10000 2020#define BUPD_CLKO_LTF 0x20000 2021#define BCOM_CH_CFO 0x40000 2022#define BCSI_ESTI_MODE 0x80000 2023#define BADV_UPD_EQZ 0x100000 2024#define BUCHCFG 0x7000000 2025#define BUPDEQZ 0x8000000 2026 2027#define BRX_PESUDO_NOISE_ON 0x20000000 2028#define BRX_PESUDO_NOISE_A 0xff 2029#define BRX_PESUDO_NOISE_B 0xff00 2030#define BRX_PESUDO_NOISE_C 0xff0000 2031#define BRX_PESUDO_NOISE_D 0xff000000 2032#define BRX_PESUDO_NOISESTATE_A 0xffff 2033#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2034#define BRX_PESUDO_NOISESTATE_C 0xffff 2035#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2036 2037#define BZEBRA1_HSSIENABLE 0x8 2038#define BZEBRA1_TRXCONTROL 0xc00 2039#define BZEBRA1_TRXGAINSETTING 0x07f 2040#define BZEBRA1_RXCOUNTER 0xc00 2041#define BZEBRA1_TXCHANGEPUMP 0x38 2042#define BZEBRA1_RXCHANGEPUMP 0x7 2043#define BZEBRA1_CHANNEL_NUM 0xf80 2044#define BZEBRA1_TXLPFBW 0x400 2045#define BZEBRA1_RXLPFBW 0x600 2046 2047#define BRTL8256REG_MODE_CTRL1 0x100 2048#define BRTL8256REG_MODE_CTRL0 0x40 2049#define BRTL8256REG_TXLPFBW 0x18 2050#define BRTL8256REG_RXLPFBW 0x600 2051 2052#define BRTL8258_TXLPFBW 0xc 2053#define BRTL8258_RXLPFBW 0xc00 2054#define BRTL8258_RSSILPFBW 0xc0 2055 2056#define BBYTE0 0x1 2057#define BBYTE1 0x2 2058#define BBYTE2 0x4 2059#define BBYTE3 0x8 2060#define BWORD0 0x3 2061#define BWORD1 0xc 2062#define BWORD 0xf 2063 2064#define MASKBYTE0 0xff 2065#define MASKBYTE1 0xff00 2066#define MASKBYTE2 0xff0000 2067#define MASKBYTE3 0xff000000 2068#define MASKHWORD 0xffff0000 2069#define MASKLWORD 0x0000ffff 2070#define MASKDWORD 0xffffffff 2071#define MASK12BITS 0xfff 2072#define MASKH4BITS 0xf0000000 2073#define MASKOFDM_D 0xffc00000 2074#define MASKCCK 0x3f3f3f3f 2075 2076#define MASK4BITS 0x0f 2077#define MASK20BITS 0xfffff 2078#define RFREG_OFFSET_MASK 0xfffff 2079 2080#define BENABLE 0x1 2081#define BDISABLE 0x0 2082 2083#define LEFT_ANTENNA 0x0 2084#define RIGHT_ANTENNA 0x1 2085 2086#define TCHECK_TXSTATUS 500 2087#define TUPDATE_RXCOUNTER 100 2088 2089/* 2 EFUSE_TEST (For RTL8723 partially) */ 2090#define EFUSE_SEL(x) (((x) & 0x3) << 8) 2091#define EFUSE_SEL_MASK 0x300 2092#define EFUSE_WIFI_SEL_0 0x0 2093/* Enable GPIO[9] as WiFi HW PDn source*/ 2094#define WL_HWPDN_EN BIT(0) 2095/* WiFi HW PDn polarity control*/ 2096#define WL_HWPDN_SL BIT(1) 2097 2098#endif 2099