linux/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
   4 *
   5 * Author: Zheng Yang <zhengyang@rock-chips.com>
   6 *         Heiko Stuebner <heiko@sntech.de>
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/clk-provider.h>
  11#include <linux/delay.h>
  12#include <linux/io.h>
  13#include <linux/interrupt.h>
  14#include <linux/kernel.h>
  15#include <linux/module.h>
  16#include <linux/nvmem-consumer.h>
  17#include <linux/of.h>
  18#include <linux/of_device.h>
  19#include <linux/platform_device.h>
  20#include <linux/regmap.h>
  21#include <linux/phy/phy.h>
  22#include <linux/slab.h>
  23
  24#define UPDATE(x, h, l)         (((x) << (l)) & GENMASK((h), (l)))
  25
  26/* REG: 0x00 */
  27#define RK3228_PRE_PLL_REFCLK_SEL_PCLK                  BIT(0)
  28/* REG: 0x01 */
  29#define RK3228_BYPASS_RXSENSE_EN                        BIT(2)
  30#define RK3228_BYPASS_PWRON_EN                          BIT(1)
  31#define RK3228_BYPASS_PLLPD_EN                          BIT(0)
  32/* REG: 0x02 */
  33#define RK3228_BYPASS_PDATA_EN                          BIT(4)
  34#define RK3228_PDATAEN_DISABLE                          BIT(0)
  35/* REG: 0x03 */
  36#define RK3228_BYPASS_AUTO_TERM_RES_CAL                 BIT(7)
  37#define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x)          UPDATE(x, 6, 0)
  38/* REG: 0x04 */
  39#define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x)           UPDATE(x, 7, 0)
  40/* REG: 0xaa */
  41#define RK3228_POST_PLL_CTRL_MANUAL                     BIT(0)
  42/* REG: 0xe0 */
  43#define RK3228_POST_PLL_POWER_DOWN                      BIT(5)
  44#define RK3228_PRE_PLL_POWER_DOWN                       BIT(4)
  45#define RK3228_RXSENSE_CLK_CH_ENABLE                    BIT(3)
  46#define RK3228_RXSENSE_DATA_CH2_ENABLE                  BIT(2)
  47#define RK3228_RXSENSE_DATA_CH1_ENABLE                  BIT(1)
  48#define RK3228_RXSENSE_DATA_CH0_ENABLE                  BIT(0)
  49/* REG: 0xe1 */
  50#define RK3228_BANDGAP_ENABLE                           BIT(4)
  51#define RK3228_TMDS_DRIVER_ENABLE                       GENMASK(3, 0)
  52/* REG: 0xe2 */
  53#define RK3228_PRE_PLL_FB_DIV_8_MASK                    BIT(7)
  54#define RK3228_PRE_PLL_FB_DIV_8(x)                      UPDATE((x) >> 8, 7, 7)
  55#define RK3228_PCLK_VCO_DIV_5_MASK                      BIT(5)
  56#define RK3228_PCLK_VCO_DIV_5(x)                        UPDATE(x, 5, 5)
  57#define RK3228_PRE_PLL_PRE_DIV_MASK                     GENMASK(4, 0)
  58#define RK3228_PRE_PLL_PRE_DIV(x)                       UPDATE(x, 4, 0)
  59/* REG: 0xe3 */
  60#define RK3228_PRE_PLL_FB_DIV_7_0(x)                    UPDATE(x, 7, 0)
  61/* REG: 0xe4 */
  62#define RK3228_PRE_PLL_PCLK_DIV_B_MASK                  GENMASK(6, 5)
  63#define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT                 5
  64#define RK3228_PRE_PLL_PCLK_DIV_B(x)                    UPDATE(x, 6, 5)
  65#define RK3228_PRE_PLL_PCLK_DIV_A_MASK                  GENMASK(4, 0)
  66#define RK3228_PRE_PLL_PCLK_DIV_A(x)                    UPDATE(x, 4, 0)
  67/* REG: 0xe5 */
  68#define RK3228_PRE_PLL_PCLK_DIV_C_MASK                  GENMASK(6, 5)
  69#define RK3228_PRE_PLL_PCLK_DIV_C(x)                    UPDATE(x, 6, 5)
  70#define RK3228_PRE_PLL_PCLK_DIV_D_MASK                  GENMASK(4, 0)
  71#define RK3228_PRE_PLL_PCLK_DIV_D(x)                    UPDATE(x, 4, 0)
  72/* REG: 0xe6 */
  73#define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK               GENMASK(5, 4)
  74#define RK3228_PRE_PLL_TMDSCLK_DIV_C(x)                 UPDATE(x, 5, 4)
  75#define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK               GENMASK(3, 2)
  76#define RK3228_PRE_PLL_TMDSCLK_DIV_A(x)                 UPDATE(x, 3, 2)
  77#define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK               GENMASK(1, 0)
  78#define RK3228_PRE_PLL_TMDSCLK_DIV_B(x)                 UPDATE(x, 1, 0)
  79/* REG: 0xe8 */
  80#define RK3228_PRE_PLL_LOCK_STATUS                      BIT(0)
  81/* REG: 0xe9 */
  82#define RK3228_POST_PLL_POST_DIV_ENABLE                 UPDATE(3, 7, 6)
  83#define RK3228_POST_PLL_PRE_DIV_MASK                    GENMASK(4, 0)
  84#define RK3228_POST_PLL_PRE_DIV(x)                      UPDATE(x, 4, 0)
  85/* REG: 0xea */
  86#define RK3228_POST_PLL_FB_DIV_7_0(x)                   UPDATE(x, 7, 0)
  87/* REG: 0xeb */
  88#define RK3228_POST_PLL_FB_DIV_8_MASK                   BIT(7)
  89#define RK3228_POST_PLL_FB_DIV_8(x)                     UPDATE((x) >> 8, 7, 7)
  90#define RK3228_POST_PLL_POST_DIV_MASK                   GENMASK(5, 4)
  91#define RK3228_POST_PLL_POST_DIV(x)                     UPDATE(x, 5, 4)
  92#define RK3228_POST_PLL_LOCK_STATUS                     BIT(0)
  93/* REG: 0xee */
  94#define RK3228_TMDS_CH_TA_ENABLE                        GENMASK(7, 4)
  95/* REG: 0xef */
  96#define RK3228_TMDS_CLK_CH_TA(x)                        UPDATE(x, 7, 6)
  97#define RK3228_TMDS_DATA_CH2_TA(x)                      UPDATE(x, 5, 4)
  98#define RK3228_TMDS_DATA_CH1_TA(x)                      UPDATE(x, 3, 2)
  99#define RK3228_TMDS_DATA_CH0_TA(x)                      UPDATE(x, 1, 0)
 100/* REG: 0xf0 */
 101#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK          GENMASK(5, 4)
 102#define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x)            UPDATE(x, 5, 4)
 103#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK          GENMASK(3, 2)
 104#define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x)            UPDATE(x, 3, 2)
 105#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK          GENMASK(1, 0)
 106#define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x)            UPDATE(x, 1, 0)
 107/* REG: 0xf1 */
 108#define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x)              UPDATE(x, 7, 4)
 109#define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x)            UPDATE(x, 3, 0)
 110/* REG: 0xf2 */
 111#define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x)            UPDATE(x, 7, 4)
 112#define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x)            UPDATE(x, 3, 0)
 113
 114/* REG: 0x01 */
 115#define RK3328_BYPASS_RXSENSE_EN                        BIT(2)
 116#define RK3328_BYPASS_POWERON_EN                        BIT(1)
 117#define RK3328_BYPASS_PLLPD_EN                          BIT(0)
 118/* REG: 0x02 */
 119#define RK3328_INT_POL_HIGH                             BIT(7)
 120#define RK3328_BYPASS_PDATA_EN                          BIT(4)
 121#define RK3328_PDATA_EN                                 BIT(0)
 122/* REG:0x05 */
 123#define RK3328_INT_TMDS_CLK(x)                          UPDATE(x, 7, 4)
 124#define RK3328_INT_TMDS_D2(x)                           UPDATE(x, 3, 0)
 125/* REG:0x07 */
 126#define RK3328_INT_TMDS_D1(x)                           UPDATE(x, 7, 4)
 127#define RK3328_INT_TMDS_D0(x)                           UPDATE(x, 3, 0)
 128/* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
 129#define RK3328_INT_AGND_LOW_PULSE_LOCKED                BIT(3)
 130#define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED             BIT(2)
 131#define RK3328_INT_VSS_AGND_ESD_DET                     BIT(1)
 132#define RK3328_INT_AGND_VSS_ESD_DET                     BIT(0)
 133/* REG: 0xa0 */
 134#define RK3328_PCLK_VCO_DIV_5_MASK                      BIT(1)
 135#define RK3328_PCLK_VCO_DIV_5(x)                        UPDATE(x, 1, 1)
 136#define RK3328_PRE_PLL_POWER_DOWN                       BIT(0)
 137/* REG: 0xa1 */
 138#define RK3328_PRE_PLL_PRE_DIV_MASK                     GENMASK(5, 0)
 139#define RK3328_PRE_PLL_PRE_DIV(x)                       UPDATE(x, 5, 0)
 140/* REG: 0xa2 */
 141/* unset means center spread */
 142#define RK3328_SPREAD_SPECTRUM_MOD_DOWN                 BIT(7)
 143#define RK3328_SPREAD_SPECTRUM_MOD_DISABLE              BIT(6)
 144#define RK3328_PRE_PLL_FRAC_DIV_DISABLE                 UPDATE(3, 5, 4)
 145#define RK3328_PRE_PLL_FB_DIV_11_8_MASK                 GENMASK(3, 0)
 146#define RK3328_PRE_PLL_FB_DIV_11_8(x)                   UPDATE((x) >> 8, 3, 0)
 147/* REG: 0xa3 */
 148#define RK3328_PRE_PLL_FB_DIV_7_0(x)                    UPDATE(x, 7, 0)
 149/* REG: 0xa4*/
 150#define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK               GENMASK(1, 0)
 151#define RK3328_PRE_PLL_TMDSCLK_DIV_C(x)                 UPDATE(x, 1, 0)
 152#define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK               GENMASK(3, 2)
 153#define RK3328_PRE_PLL_TMDSCLK_DIV_B(x)                 UPDATE(x, 3, 2)
 154#define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK               GENMASK(5, 4)
 155#define RK3328_PRE_PLL_TMDSCLK_DIV_A(x)                 UPDATE(x, 5, 4)
 156/* REG: 0xa5 */
 157#define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT                 5
 158#define RK3328_PRE_PLL_PCLK_DIV_B_MASK                  GENMASK(6, 5)
 159#define RK3328_PRE_PLL_PCLK_DIV_B(x)                    UPDATE(x, 6, 5)
 160#define RK3328_PRE_PLL_PCLK_DIV_A_MASK                  GENMASK(4, 0)
 161#define RK3328_PRE_PLL_PCLK_DIV_A(x)                    UPDATE(x, 4, 0)
 162/* REG: 0xa6 */
 163#define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT                 5
 164#define RK3328_PRE_PLL_PCLK_DIV_C_MASK                  GENMASK(6, 5)
 165#define RK3328_PRE_PLL_PCLK_DIV_C(x)                    UPDATE(x, 6, 5)
 166#define RK3328_PRE_PLL_PCLK_DIV_D_MASK                  GENMASK(4, 0)
 167#define RK3328_PRE_PLL_PCLK_DIV_D(x)                    UPDATE(x, 4, 0)
 168/* REG: 0xa9 */
 169#define RK3328_PRE_PLL_LOCK_STATUS                      BIT(0)
 170/* REG: 0xaa */
 171#define RK3328_POST_PLL_POST_DIV_ENABLE                 GENMASK(3, 2)
 172#define RK3328_POST_PLL_REFCLK_SEL_TMDS                 BIT(1)
 173#define RK3328_POST_PLL_POWER_DOWN                      BIT(0)
 174/* REG:0xab */
 175#define RK3328_POST_PLL_FB_DIV_8(x)                     UPDATE((x) >> 8, 7, 7)
 176#define RK3328_POST_PLL_PRE_DIV(x)                      UPDATE(x, 4, 0)
 177/* REG: 0xac */
 178#define RK3328_POST_PLL_FB_DIV_7_0(x)                   UPDATE(x, 7, 0)
 179/* REG: 0xad */
 180#define RK3328_POST_PLL_POST_DIV_MASK                   GENMASK(1, 0)
 181#define RK3328_POST_PLL_POST_DIV_2                      0x0
 182#define RK3328_POST_PLL_POST_DIV_4                      0x1
 183#define RK3328_POST_PLL_POST_DIV_8                      0x3
 184/* REG: 0xaf */
 185#define RK3328_POST_PLL_LOCK_STATUS                     BIT(0)
 186/* REG: 0xb0 */
 187#define RK3328_BANDGAP_ENABLE                           BIT(2)
 188/* REG: 0xb2 */
 189#define RK3328_TMDS_CLK_DRIVER_EN                       BIT(3)
 190#define RK3328_TMDS_D2_DRIVER_EN                        BIT(2)
 191#define RK3328_TMDS_D1_DRIVER_EN                        BIT(1)
 192#define RK3328_TMDS_D0_DRIVER_EN                        BIT(0)
 193#define RK3328_TMDS_DRIVER_ENABLE               (RK3328_TMDS_CLK_DRIVER_EN | \
 194                                                RK3328_TMDS_D2_DRIVER_EN | \
 195                                                RK3328_TMDS_D1_DRIVER_EN | \
 196                                                RK3328_TMDS_D0_DRIVER_EN)
 197/* REG:0xc5 */
 198#define RK3328_BYPASS_TERM_RESISTOR_CALIB               BIT(7)
 199#define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x)        UPDATE((x) >> 8, 6, 0)
 200/* REG:0xc6 */
 201#define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x)         UPDATE(x, 7, 0)
 202/* REG:0xc7 */
 203#define RK3328_TERM_RESISTOR_50                         UPDATE(0, 2, 1)
 204#define RK3328_TERM_RESISTOR_62_5                       UPDATE(1, 2, 1)
 205#define RK3328_TERM_RESISTOR_75                         UPDATE(2, 2, 1)
 206#define RK3328_TERM_RESISTOR_100                        UPDATE(3, 2, 1)
 207/* REG 0xc8 - 0xcb */
 208#define RK3328_ESD_DETECT_MASK                          GENMASK(7, 6)
 209#define RK3328_ESD_DETECT_340MV                         (0x0 << 6)
 210#define RK3328_ESD_DETECT_280MV                         (0x1 << 6)
 211#define RK3328_ESD_DETECT_260MV                         (0x2 << 6)
 212#define RK3328_ESD_DETECT_240MV                         (0x3 << 6)
 213/* resistors can be used in parallel */
 214#define RK3328_TMDS_TERM_RESIST_MASK                    GENMASK(5, 0)
 215#define RK3328_TMDS_TERM_RESIST_75                      BIT(5)
 216#define RK3328_TMDS_TERM_RESIST_150                     BIT(4)
 217#define RK3328_TMDS_TERM_RESIST_300                     BIT(3)
 218#define RK3328_TMDS_TERM_RESIST_600                     BIT(2)
 219#define RK3328_TMDS_TERM_RESIST_1000                    BIT(1)
 220#define RK3328_TMDS_TERM_RESIST_2000                    BIT(0)
 221/* REG: 0xd1 */
 222#define RK3328_PRE_PLL_FRAC_DIV_23_16(x)                UPDATE((x) >> 16, 7, 0)
 223/* REG: 0xd2 */
 224#define RK3328_PRE_PLL_FRAC_DIV_15_8(x)                 UPDATE((x) >> 8, 7, 0)
 225/* REG: 0xd3 */
 226#define RK3328_PRE_PLL_FRAC_DIV_7_0(x)                  UPDATE(x, 7, 0)
 227
 228struct inno_hdmi_phy_drv_data;
 229
 230struct inno_hdmi_phy {
 231        struct device *dev;
 232        struct regmap *regmap;
 233        int irq;
 234
 235        struct phy *phy;
 236        struct clk *sysclk;
 237        struct clk *refoclk;
 238        struct clk *refpclk;
 239
 240        /* platform data */
 241        const struct inno_hdmi_phy_drv_data *plat_data;
 242        int chip_version;
 243
 244        /* clk provider */
 245        struct clk_hw hw;
 246        struct clk *phyclk;
 247        unsigned long pixclock;
 248};
 249
 250struct pre_pll_config {
 251        unsigned long pixclock;
 252        unsigned long tmdsclock;
 253        u8 prediv;
 254        u16 fbdiv;
 255        u8 tmds_div_a;
 256        u8 tmds_div_b;
 257        u8 tmds_div_c;
 258        u8 pclk_div_a;
 259        u8 pclk_div_b;
 260        u8 pclk_div_c;
 261        u8 pclk_div_d;
 262        u8 vco_div_5_en;
 263        u32 fracdiv;
 264};
 265
 266struct post_pll_config {
 267        unsigned long tmdsclock;
 268        u8 prediv;
 269        u16 fbdiv;
 270        u8 postdiv;
 271        u8 version;
 272};
 273
 274struct phy_config {
 275        unsigned long   tmdsclock;
 276        u8              regs[14];
 277};
 278
 279struct inno_hdmi_phy_ops {
 280        int (*init)(struct inno_hdmi_phy *inno);
 281        int (*power_on)(struct inno_hdmi_phy *inno,
 282                        const struct post_pll_config *cfg,
 283                        const struct phy_config *phy_cfg);
 284        void (*power_off)(struct inno_hdmi_phy *inno);
 285};
 286
 287struct inno_hdmi_phy_drv_data {
 288        const struct inno_hdmi_phy_ops  *ops;
 289        const struct clk_ops            *clk_ops;
 290        const struct phy_config         *phy_cfg_table;
 291};
 292
 293static const struct pre_pll_config pre_pll_cfg_table[] = {
 294        { 27000000,  27000000, 1,  90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
 295        { 27000000,  33750000, 1,  90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
 296        { 40000000,  40000000, 1,  80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
 297        { 59341000,  59341000, 1,  98, 3, 1, 2,  1, 3, 3, 4, 0, 0xE6AE6B},
 298        { 59400000,  59400000, 1,  99, 3, 1, 1,  1, 3, 3, 4, 0, 0},
 299        { 59341000,  74176250, 1,  98, 0, 3, 3,  1, 3, 3, 4, 0, 0xE6AE6B},
 300        { 59400000,  74250000, 1,  99, 1, 2, 2,  1, 3, 3, 4, 0, 0},
 301        { 74176000,  74176000, 1,  98, 1, 2, 2,  1, 2, 3, 4, 0, 0xE6AE6B},
 302        { 74250000,  74250000, 1,  99, 1, 2, 2,  1, 2, 3, 4, 0, 0},
 303        { 74176000,  92720000, 4, 494, 1, 2, 2,  1, 3, 3, 4, 0, 0x816817},
 304        { 74250000,  92812500, 4, 495, 1, 2, 2,  1, 3, 3, 4, 0, 0},
 305        {148352000, 148352000, 1,  98, 1, 1, 1,  1, 2, 2, 2, 0, 0xE6AE6B},
 306        {148500000, 148500000, 1,  99, 1, 1, 1,  1, 2, 2, 2, 0, 0},
 307        {148352000, 185440000, 4, 494, 0, 2, 2,  1, 3, 2, 2, 0, 0x816817},
 308        {148500000, 185625000, 4, 495, 0, 2, 2,  1, 3, 2, 2, 0, 0},
 309        {296703000, 296703000, 1,  98, 0, 1, 1,  1, 0, 2, 2, 0, 0xE6AE6B},
 310        {297000000, 297000000, 1,  99, 0, 1, 1,  1, 0, 2, 2, 0, 0},
 311        {296703000, 370878750, 4, 494, 1, 2, 0,  1, 3, 1, 1, 0, 0x816817},
 312        {297000000, 371250000, 4, 495, 1, 2, 0,  1, 3, 1, 1, 0, 0},
 313        {593407000, 296703500, 1,  98, 0, 1, 1,  1, 0, 2, 1, 0, 0xE6AE6B},
 314        {594000000, 297000000, 1,  99, 0, 1, 1,  1, 0, 2, 1, 0, 0},
 315        {593407000, 370879375, 4, 494, 1, 2, 0,  1, 3, 1, 1, 1, 0x816817},
 316        {594000000, 371250000, 4, 495, 1, 2, 0,  1, 3, 1, 1, 1, 0},
 317        {593407000, 593407000, 1,  98, 0, 2, 0,  1, 0, 1, 1, 0, 0xE6AE6B},
 318        {594000000, 594000000, 1,  99, 0, 2, 0,  1, 0, 1, 1, 0, 0},
 319        { /* sentinel */ }
 320};
 321
 322static const struct post_pll_config post_pll_cfg_table[] = {
 323        {33750000,  1, 40, 8, 1},
 324        {33750000,  1, 80, 8, 2},
 325        {74250000,  1, 40, 8, 1},
 326        {74250000, 18, 80, 8, 2},
 327        {148500000, 2, 40, 4, 3},
 328        {297000000, 4, 40, 2, 3},
 329        {594000000, 8, 40, 1, 3},
 330        { /* sentinel */ }
 331};
 332
 333/* phy tuning values for an undocumented set of registers */
 334static const struct phy_config rk3228_phy_cfg[] = {
 335        {       165000000, {
 336                        0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
 337                        0x00, 0x00, 0x00, 0x00, 0x00,
 338                },
 339        }, {
 340                340000000, {
 341                        0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
 342                        0x00, 0x00, 0x00, 0x00, 0x00,
 343                },
 344        }, {
 345                594000000, {
 346                        0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
 347                        0x00, 0x00, 0x00, 0x00, 0x00,
 348                },
 349        }, { /* sentinel */ },
 350};
 351
 352/* phy tuning values for an undocumented set of registers */
 353static const struct phy_config rk3328_phy_cfg[] = {
 354        {       165000000, {
 355                        0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
 356                        0x00, 0xac, 0xcc, 0xcc, 0xcc,
 357                },
 358        }, {
 359                340000000, {
 360                        0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
 361                        0x3f, 0xac, 0xcc, 0xcd, 0xdd,
 362                },
 363        }, {
 364                594000000, {
 365                        0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
 366                        0x00, 0xac, 0xcc, 0xcc, 0xcc,
 367                },
 368        }, { /* sentinel */ },
 369};
 370
 371static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
 372{
 373        return container_of(hw, struct inno_hdmi_phy, hw);
 374}
 375
 376/*
 377 * The register description of the IP block does not use any distinct names
 378 * but instead the databook simply numbers the registers in one-increments.
 379 * As the registers are obviously 32bit sized, the inno_* functions
 380 * translate the databook register names to the actual registers addresses.
 381 */
 382static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
 383{
 384        regmap_write(inno->regmap, reg * 4, val);
 385}
 386
 387static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
 388{
 389        u32 val;
 390
 391        regmap_read(inno->regmap, reg * 4, &val);
 392
 393        return val;
 394}
 395
 396static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
 397                                    u8 mask, u8 val)
 398{
 399        regmap_update_bits(inno->regmap, reg * 4, mask, val);
 400}
 401
 402#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
 403        regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
 404                                 sleep_us, timeout_us)
 405
 406static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
 407                                               unsigned long rate)
 408{
 409        int bus_width = phy_get_bus_width(inno->phy);
 410
 411        switch (bus_width) {
 412        case 4:
 413        case 5:
 414        case 6:
 415        case 10:
 416        case 12:
 417        case 16:
 418                return (u64)rate * bus_width / 8;
 419        default:
 420                return rate;
 421        }
 422}
 423
 424static irqreturn_t inno_hdmi_phy_rk3328_hardirq(int irq, void *dev_id)
 425{
 426        struct inno_hdmi_phy *inno = dev_id;
 427        int intr_stat1, intr_stat2, intr_stat3;
 428
 429        intr_stat1 = inno_read(inno, 0x04);
 430        intr_stat2 = inno_read(inno, 0x06);
 431        intr_stat3 = inno_read(inno, 0x08);
 432
 433        if (intr_stat1)
 434                inno_write(inno, 0x04, intr_stat1);
 435        if (intr_stat2)
 436                inno_write(inno, 0x06, intr_stat2);
 437        if (intr_stat3)
 438                inno_write(inno, 0x08, intr_stat3);
 439
 440        if (intr_stat1 || intr_stat2 || intr_stat3)
 441                return IRQ_WAKE_THREAD;
 442
 443        return IRQ_HANDLED;
 444}
 445
 446static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id)
 447{
 448        struct inno_hdmi_phy *inno = dev_id;
 449
 450        inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
 451        usleep_range(10, 20);
 452        inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
 453
 454        return IRQ_HANDLED;
 455}
 456
 457static int inno_hdmi_phy_power_on(struct phy *phy)
 458{
 459        struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
 460        const struct post_pll_config *cfg = post_pll_cfg_table;
 461        const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
 462        unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno,
 463                                                            inno->pixclock);
 464        int ret;
 465
 466        if (!tmdsclock) {
 467                dev_err(inno->dev, "TMDS clock is zero!\n");
 468                return -EINVAL;
 469        }
 470
 471        if (!inno->plat_data->ops->power_on)
 472                return -EINVAL;
 473
 474        for (; cfg->tmdsclock != 0; cfg++)
 475                if (tmdsclock <= cfg->tmdsclock &&
 476                    cfg->version & inno->chip_version)
 477                        break;
 478
 479        for (; phy_cfg->tmdsclock != 0; phy_cfg++)
 480                if (tmdsclock <= phy_cfg->tmdsclock)
 481                        break;
 482
 483        if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0)
 484                return -EINVAL;
 485
 486        dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
 487
 488        ret = clk_prepare_enable(inno->phyclk);
 489        if (ret)
 490                return ret;
 491
 492        ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
 493        if (ret) {
 494                clk_disable_unprepare(inno->phyclk);
 495                return ret;
 496        }
 497
 498        return 0;
 499}
 500
 501static int inno_hdmi_phy_power_off(struct phy *phy)
 502{
 503        struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
 504
 505        if (!inno->plat_data->ops->power_off)
 506                return -EINVAL;
 507
 508        inno->plat_data->ops->power_off(inno);
 509
 510        clk_disable_unprepare(inno->phyclk);
 511
 512        dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
 513
 514        return 0;
 515}
 516
 517static const struct phy_ops inno_hdmi_phy_ops = {
 518        .owner = THIS_MODULE,
 519        .power_on = inno_hdmi_phy_power_on,
 520        .power_off = inno_hdmi_phy_power_off,
 521};
 522
 523static const
 524struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno,
 525                                                     unsigned long rate)
 526{
 527        const struct pre_pll_config *cfg = pre_pll_cfg_table;
 528        unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
 529
 530        for (; cfg->pixclock != 0; cfg++)
 531                if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
 532                        break;
 533
 534        if (cfg->pixclock == 0)
 535                return ERR_PTR(-EINVAL);
 536
 537        return cfg;
 538}
 539
 540static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw)
 541{
 542        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 543        u8 status;
 544
 545        status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN;
 546        return status ? 0 : 1;
 547}
 548
 549static int inno_hdmi_phy_rk3228_clk_prepare(struct clk_hw *hw)
 550{
 551        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 552
 553        inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
 554        return 0;
 555}
 556
 557static void inno_hdmi_phy_rk3228_clk_unprepare(struct clk_hw *hw)
 558{
 559        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 560
 561        inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
 562                         RK3228_PRE_PLL_POWER_DOWN);
 563}
 564
 565static
 566unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(struct clk_hw *hw,
 567                                                   unsigned long parent_rate)
 568{
 569        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 570        u8 nd, no_a, no_b, no_d;
 571        u64 vco;
 572        u16 nf;
 573
 574        nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK;
 575        nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1;
 576        nf |= inno_read(inno, 0xe3);
 577        vco = parent_rate * nf;
 578
 579        if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) {
 580                do_div(vco, nd * 5);
 581        } else {
 582                no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK;
 583                if (!no_a)
 584                        no_a = 1;
 585                no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK;
 586                no_b >>= RK3228_PRE_PLL_PCLK_DIV_B_SHIFT;
 587                no_b += 2;
 588                no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK;
 589
 590                do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
 591        }
 592
 593        inno->pixclock = vco;
 594
 595        dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
 596
 597        return vco;
 598}
 599
 600static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw,
 601                                                unsigned long rate,
 602                                                unsigned long *parent_rate)
 603{
 604        const struct pre_pll_config *cfg = pre_pll_cfg_table;
 605
 606        for (; cfg->pixclock != 0; cfg++)
 607                if (cfg->pixclock == rate && !cfg->fracdiv)
 608                        break;
 609
 610        if (cfg->pixclock == 0)
 611                return -EINVAL;
 612
 613        return cfg->pixclock;
 614}
 615
 616static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
 617                                             unsigned long rate,
 618                                             unsigned long parent_rate)
 619{
 620        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 621        const struct pre_pll_config *cfg = pre_pll_cfg_table;
 622        unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
 623        u32 v;
 624        int ret;
 625
 626        dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
 627                __func__, rate, tmdsclock);
 628
 629        cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
 630        if (IS_ERR(cfg))
 631                return PTR_ERR(cfg);
 632
 633        /* Power down PRE-PLL */
 634        inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
 635                         RK3228_PRE_PLL_POWER_DOWN);
 636
 637        inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
 638                         RK3228_PCLK_VCO_DIV_5_MASK |
 639                         RK3228_PRE_PLL_PRE_DIV_MASK,
 640                         RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) |
 641                         RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) |
 642                         RK3228_PRE_PLL_PRE_DIV(cfg->prediv));
 643        inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
 644        inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
 645                         RK3228_PRE_PLL_PCLK_DIV_A_MASK,
 646                         RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |
 647                         RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a));
 648        inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
 649                         RK3228_PRE_PLL_PCLK_DIV_D_MASK,
 650                         RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
 651                         RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
 652        inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
 653                         RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK |
 654                         RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK,
 655                         RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
 656                         RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
 657                         RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
 658
 659        /* Power up PRE-PLL */
 660        inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
 661
 662        /* Wait for Pre-PLL lock */
 663        ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
 664                        100, 100000);
 665        if (ret) {
 666                dev_err(inno->dev, "Pre-PLL locking failed\n");
 667                return ret;
 668        }
 669
 670        inno->pixclock = rate;
 671
 672        return 0;
 673}
 674
 675static const struct clk_ops inno_hdmi_phy_rk3228_clk_ops = {
 676        .prepare = inno_hdmi_phy_rk3228_clk_prepare,
 677        .unprepare = inno_hdmi_phy_rk3228_clk_unprepare,
 678        .is_prepared = inno_hdmi_phy_rk3228_clk_is_prepared,
 679        .recalc_rate = inno_hdmi_phy_rk3228_clk_recalc_rate,
 680        .round_rate = inno_hdmi_phy_rk3228_clk_round_rate,
 681        .set_rate = inno_hdmi_phy_rk3228_clk_set_rate,
 682};
 683
 684static int inno_hdmi_phy_rk3328_clk_is_prepared(struct clk_hw *hw)
 685{
 686        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 687        u8 status;
 688
 689        status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN;
 690        return status ? 0 : 1;
 691}
 692
 693static int inno_hdmi_phy_rk3328_clk_prepare(struct clk_hw *hw)
 694{
 695        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 696
 697        inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
 698        return 0;
 699}
 700
 701static void inno_hdmi_phy_rk3328_clk_unprepare(struct clk_hw *hw)
 702{
 703        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 704
 705        inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
 706                         RK3328_PRE_PLL_POWER_DOWN);
 707}
 708
 709static
 710unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
 711                                                   unsigned long parent_rate)
 712{
 713        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 714        unsigned long frac;
 715        u8 nd, no_a, no_b, no_c, no_d;
 716        u64 vco;
 717        u16 nf;
 718
 719        nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK;
 720        nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8);
 721        nf |= inno_read(inno, 0xa3);
 722        vco = parent_rate * nf;
 723
 724        if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) {
 725                frac = inno_read(inno, 0xd3) |
 726                       (inno_read(inno, 0xd2) << 8) |
 727                       (inno_read(inno, 0xd1) << 16);
 728                vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
 729        }
 730
 731        if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) {
 732                do_div(vco, nd * 5);
 733        } else {
 734                no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK;
 735                no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
 736                no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
 737                no_b += 2;
 738                no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
 739                no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
 740                no_c = 1 << no_c;
 741                no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
 742
 743                do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
 744        }
 745
 746        inno->pixclock = vco;
 747        dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
 748
 749        return vco;
 750}
 751
 752static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
 753                                                unsigned long rate,
 754                                                unsigned long *parent_rate)
 755{
 756        const struct pre_pll_config *cfg = pre_pll_cfg_table;
 757
 758        for (; cfg->pixclock != 0; cfg++)
 759                if (cfg->pixclock == rate)
 760                        break;
 761
 762        if (cfg->pixclock == 0)
 763                return -EINVAL;
 764
 765        return cfg->pixclock;
 766}
 767
 768static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
 769                                             unsigned long rate,
 770                                             unsigned long parent_rate)
 771{
 772        struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 773        const struct pre_pll_config *cfg = pre_pll_cfg_table;
 774        unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
 775        u32 val;
 776        int ret;
 777
 778        dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
 779                __func__, rate, tmdsclock);
 780
 781        cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
 782        if (IS_ERR(cfg))
 783                return PTR_ERR(cfg);
 784
 785        inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
 786                         RK3328_PRE_PLL_POWER_DOWN);
 787
 788        /* Configure pre-pll */
 789        inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK,
 790                         RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
 791        inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
 792
 793        val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
 794        if (!cfg->fracdiv)
 795                val |= RK3328_PRE_PLL_FRAC_DIV_DISABLE;
 796        inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
 797        inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
 798        inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |
 799                   RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b));
 800        inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
 801                   RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
 802        inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
 803                   RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
 804                   RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
 805        inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
 806        inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
 807        inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
 808
 809        inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
 810
 811        /* Wait for Pre-PLL lock */
 812        ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
 813                        1000, 10000);
 814        if (ret) {
 815                dev_err(inno->dev, "Pre-PLL locking failed\n");
 816                return ret;
 817        }
 818
 819        inno->pixclock = rate;
 820
 821        return 0;
 822}
 823
 824static const struct clk_ops inno_hdmi_phy_rk3328_clk_ops = {
 825        .prepare = inno_hdmi_phy_rk3328_clk_prepare,
 826        .unprepare = inno_hdmi_phy_rk3328_clk_unprepare,
 827        .is_prepared = inno_hdmi_phy_rk3328_clk_is_prepared,
 828        .recalc_rate = inno_hdmi_phy_rk3328_clk_recalc_rate,
 829        .round_rate = inno_hdmi_phy_rk3328_clk_round_rate,
 830        .set_rate = inno_hdmi_phy_rk3328_clk_set_rate,
 831};
 832
 833static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
 834{
 835        struct device *dev = inno->dev;
 836        struct device_node *np = dev->of_node;
 837        struct clk_init_data init;
 838        const char *parent_name;
 839        int ret;
 840
 841        parent_name = __clk_get_name(inno->refoclk);
 842
 843        init.parent_names = &parent_name;
 844        init.num_parents = 1;
 845        init.flags = 0;
 846        init.name = "pin_hd20_pclk";
 847        init.ops = inno->plat_data->clk_ops;
 848
 849        /* optional override of the clock name */
 850        of_property_read_string(np, "clock-output-names", &init.name);
 851
 852        inno->hw.init = &init;
 853
 854        inno->phyclk = devm_clk_register(dev, &inno->hw);
 855        if (IS_ERR(inno->phyclk)) {
 856                ret = PTR_ERR(inno->phyclk);
 857                dev_err(dev, "failed to register clock: %d\n", ret);
 858                return ret;
 859        }
 860
 861        ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);
 862        if (ret) {
 863                dev_err(dev, "failed to register clock provider: %d\n", ret);
 864                return ret;
 865        }
 866
 867        return 0;
 868}
 869
 870static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
 871{
 872        /*
 873         * Use phy internal register control
 874         * rxsense/poweron/pllpd/pdataen signal.
 875         */
 876        inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |
 877                   RK3228_BYPASS_PWRON_EN |
 878                   RK3228_BYPASS_PLLPD_EN);
 879        inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
 880                         RK3228_BYPASS_PDATA_EN);
 881
 882        /* manual power down post-PLL */
 883        inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
 884                         RK3228_POST_PLL_CTRL_MANUAL);
 885
 886        inno->chip_version = 1;
 887
 888        return 0;
 889}
 890
 891static int
 892inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
 893                              const struct post_pll_config *cfg,
 894                              const struct phy_config *phy_cfg)
 895{
 896        int ret;
 897        u32 v;
 898
 899        inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
 900                         RK3228_PDATAEN_DISABLE);
 901        inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
 902                         RK3228_POST_PLL_POWER_DOWN,
 903                         RK3228_PRE_PLL_POWER_DOWN |
 904                         RK3228_POST_PLL_POWER_DOWN);
 905
 906        /* Post-PLL update */
 907        inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
 908                         RK3228_POST_PLL_PRE_DIV(cfg->prediv));
 909        inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
 910                         RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv));
 911        inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
 912
 913        if (cfg->postdiv == 1) {
 914                inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
 915                                 0);
 916        } else {
 917                int div = cfg->postdiv / 2 - 1;
 918
 919                inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
 920                                 RK3228_POST_PLL_POST_DIV_ENABLE);
 921                inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
 922                                 RK3228_POST_PLL_POST_DIV(div));
 923        }
 924
 925        for (v = 0; v < 4; v++)
 926                inno_write(inno, 0xef + v, phy_cfg->regs[v]);
 927
 928        inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
 929                         RK3228_POST_PLL_POWER_DOWN, 0);
 930        inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
 931                         RK3228_BANDGAP_ENABLE);
 932        inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
 933                         RK3228_TMDS_DRIVER_ENABLE);
 934
 935        /* Wait for post PLL lock */
 936        ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
 937                        100, 100000);
 938        if (ret) {
 939                dev_err(inno->dev, "Post-PLL locking failed\n");
 940                return ret;
 941        }
 942
 943        if (cfg->tmdsclock > 340000000)
 944                msleep(100);
 945
 946        inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
 947        return 0;
 948}
 949
 950static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
 951{
 952        inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
 953        inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
 954        inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
 955                         RK3228_POST_PLL_POWER_DOWN);
 956}
 957
 958static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
 959        .init = inno_hdmi_phy_rk3228_init,
 960        .power_on = inno_hdmi_phy_rk3228_power_on,
 961        .power_off = inno_hdmi_phy_rk3228_power_off,
 962};
 963
 964static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
 965{
 966        struct nvmem_cell *cell;
 967        unsigned char *efuse_buf;
 968        size_t len;
 969
 970        /*
 971         * Use phy internal register control
 972         * rxsense/poweron/pllpd/pdataen signal.
 973         */
 974        inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |
 975                   RK3328_BYPASS_POWERON_EN |
 976                   RK3328_BYPASS_PLLPD_EN);
 977        inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |
 978                   RK3328_PDATA_EN);
 979
 980        /* Disable phy irq */
 981        inno_write(inno, 0x05, 0);
 982        inno_write(inno, 0x07, 0);
 983
 984        /* try to read the chip-version */
 985        inno->chip_version = 1;
 986        cell = nvmem_cell_get(inno->dev, "cpu-version");
 987        if (IS_ERR(cell)) {
 988                if (PTR_ERR(cell) == -EPROBE_DEFER)
 989                        return -EPROBE_DEFER;
 990
 991                return 0;
 992        }
 993
 994        efuse_buf = nvmem_cell_read(cell, &len);
 995        nvmem_cell_put(cell);
 996
 997        if (IS_ERR(efuse_buf))
 998                return 0;
 999        if (len == 1)
1000                inno->chip_version = efuse_buf[0] + 1;
1001        kfree(efuse_buf);
1002
1003        return 0;
1004}
1005
1006static int
1007inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
1008                              const struct post_pll_config *cfg,
1009                              const struct phy_config *phy_cfg)
1010{
1011        int ret;
1012        u32 v;
1013
1014        inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1015        inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1016                         RK3328_POST_PLL_POWER_DOWN);
1017
1018        inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1019        if (cfg->postdiv == 1) {
1020                inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
1021                inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1022                           RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1023        } else {
1024                v = (cfg->postdiv / 2) - 1;
1025                v &= RK3328_POST_PLL_POST_DIV_MASK;
1026                inno_write(inno, 0xad, v);
1027                inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1028                           RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1029                inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
1030                           RK3328_POST_PLL_REFCLK_SEL_TMDS);
1031        }
1032
1033        for (v = 0; v < 14; v++)
1034                inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
1035
1036        /* set ESD detection threshold for TMDS CLK, D2, D1 and D0 */
1037        for (v = 0; v < 4; v++)
1038                inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1039                                 RK3328_ESD_DETECT_340MV);
1040
1041        if (phy_cfg->tmdsclock > 340000000) {
1042                /* Set termination resistor to 100ohm */
1043                v = clk_get_rate(inno->sysclk) / 100000;
1044                inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
1045                           | RK3328_BYPASS_TERM_RESISTOR_CALIB);
1046                inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
1047                inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);
1048                inno_update_bits(inno, 0xc5,
1049                                 RK3328_BYPASS_TERM_RESISTOR_CALIB, 0);
1050        } else {
1051                inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);
1052
1053                /* clk termination resistor is 50ohm (parallel resistors) */
1054                if (phy_cfg->tmdsclock > 165000000)
1055                        inno_update_bits(inno, 0xc8,
1056                                         RK3328_TMDS_TERM_RESIST_MASK,
1057                                         RK3328_TMDS_TERM_RESIST_75 |
1058                                         RK3328_TMDS_TERM_RESIST_150);
1059
1060                /* data termination resistor for D2, D1 and D0 is 150ohm */
1061                for (v = 0; v < 3; v++)
1062                        inno_update_bits(inno, 0xc9 + v,
1063                                         RK3328_TMDS_TERM_RESIST_MASK,
1064                                         RK3328_TMDS_TERM_RESIST_150);
1065        }
1066
1067        inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1068        inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1069                         RK3328_BANDGAP_ENABLE);
1070        inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1071                         RK3328_TMDS_DRIVER_ENABLE);
1072
1073        /* Wait for post PLL lock */
1074        ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1075                        1000, 10000);
1076        if (ret) {
1077                dev_err(inno->dev, "Post-PLL locking failed\n");
1078                return ret;
1079        }
1080
1081        if (phy_cfg->tmdsclock > 340000000)
1082                msleep(100);
1083
1084        inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1085
1086        /* Enable PHY IRQ */
1087        inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)
1088                   | RK3328_INT_TMDS_D2(RK3328_INT_VSS_AGND_ESD_DET));
1089        inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)
1090                   | RK3328_INT_TMDS_D0(RK3328_INT_VSS_AGND_ESD_DET));
1091        return 0;
1092}
1093
1094static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1095{
1096        inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1097        inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1098        inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1099                         RK3328_POST_PLL_POWER_DOWN);
1100
1101        /* Disable PHY IRQ */
1102        inno_write(inno, 0x05, 0);
1103        inno_write(inno, 0x07, 0);
1104}
1105
1106static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1107        .init = inno_hdmi_phy_rk3328_init,
1108        .power_on = inno_hdmi_phy_rk3328_power_on,
1109        .power_off = inno_hdmi_phy_rk3328_power_off,
1110};
1111
1112static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1113        .ops = &rk3228_hdmi_phy_ops,
1114        .clk_ops = &inno_hdmi_phy_rk3228_clk_ops,
1115        .phy_cfg_table = rk3228_phy_cfg,
1116};
1117
1118static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1119        .ops = &rk3328_hdmi_phy_ops,
1120        .clk_ops = &inno_hdmi_phy_rk3328_clk_ops,
1121        .phy_cfg_table = rk3328_phy_cfg,
1122};
1123
1124static const struct regmap_config inno_hdmi_phy_regmap_config = {
1125        .reg_bits = 32,
1126        .val_bits = 32,
1127        .reg_stride = 4,
1128        .max_register = 0x400,
1129};
1130
1131static void inno_hdmi_phy_action(void *data)
1132{
1133        struct inno_hdmi_phy *inno = data;
1134
1135        clk_disable_unprepare(inno->refpclk);
1136        clk_disable_unprepare(inno->sysclk);
1137}
1138
1139static int inno_hdmi_phy_probe(struct platform_device *pdev)
1140{
1141        struct inno_hdmi_phy *inno;
1142        struct phy_provider *phy_provider;
1143        struct resource *res;
1144        void __iomem *regs;
1145        int ret;
1146
1147        inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);
1148        if (!inno)
1149                return -ENOMEM;
1150
1151        inno->dev = &pdev->dev;
1152
1153        inno->plat_data = of_device_get_match_data(inno->dev);
1154        if (!inno->plat_data || !inno->plat_data->ops)
1155                return -EINVAL;
1156
1157        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1158        regs = devm_ioremap_resource(inno->dev, res);
1159        if (IS_ERR(regs))
1160                return PTR_ERR(regs);
1161
1162        inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1163        if (IS_ERR(inno->sysclk)) {
1164                ret = PTR_ERR(inno->sysclk);
1165                dev_err(inno->dev, "failed to get sysclk: %d\n", ret);
1166                return ret;
1167        }
1168
1169        inno->refpclk = devm_clk_get(inno->dev, "refpclk");
1170        if (IS_ERR(inno->refpclk)) {
1171                ret = PTR_ERR(inno->refpclk);
1172                dev_err(inno->dev, "failed to get ref clock: %d\n", ret);
1173                return ret;
1174        }
1175
1176        inno->refoclk = devm_clk_get(inno->dev, "refoclk");
1177        if (IS_ERR(inno->refoclk)) {
1178                ret = PTR_ERR(inno->refoclk);
1179                dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
1180                        ret);
1181                return ret;
1182        }
1183
1184        ret = clk_prepare_enable(inno->sysclk);
1185        if (ret) {
1186                dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1187                return ret;
1188        }
1189
1190        /*
1191         * Refpclk needs to be on, on at least the rk3328 for still
1192         * unknown reasons.
1193         */
1194        ret = clk_prepare_enable(inno->refpclk);
1195        if (ret) {
1196                dev_err(inno->dev, "failed to enable refpclk\n");
1197                clk_disable_unprepare(inno->sysclk);
1198                return ret;
1199        }
1200
1201        ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,
1202                                       inno);
1203        if (ret)
1204                return ret;
1205
1206        inno->regmap = devm_regmap_init_mmio(inno->dev, regs,
1207                                             &inno_hdmi_phy_regmap_config);
1208        if (IS_ERR(inno->regmap))
1209                return PTR_ERR(inno->regmap);
1210
1211        /* only the newer rk3328 hdmiphy has an interrupt */
1212        inno->irq = platform_get_irq(pdev, 0);
1213        if (inno->irq > 0) {
1214                ret = devm_request_threaded_irq(inno->dev, inno->irq,
1215                                                inno_hdmi_phy_rk3328_hardirq,
1216                                                inno_hdmi_phy_rk3328_irq,
1217                                                IRQF_SHARED,
1218                                                dev_name(inno->dev), inno);
1219                if (ret)
1220                        return ret;
1221        }
1222
1223        inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);
1224        if (IS_ERR(inno->phy)) {
1225                dev_err(inno->dev, "failed to create HDMI PHY\n");
1226                return PTR_ERR(inno->phy);
1227        }
1228
1229        phy_set_drvdata(inno->phy, inno);
1230        phy_set_bus_width(inno->phy, 8);
1231
1232        if (inno->plat_data->ops->init) {
1233                ret = inno->plat_data->ops->init(inno);
1234                if (ret)
1235                        return ret;
1236        }
1237
1238        ret = inno_hdmi_phy_clk_register(inno);
1239        if (ret)
1240                return ret;
1241
1242        phy_provider = devm_of_phy_provider_register(inno->dev,
1243                                                     of_phy_simple_xlate);
1244        return PTR_ERR_OR_ZERO(phy_provider);
1245}
1246
1247static int inno_hdmi_phy_remove(struct platform_device *pdev)
1248{
1249        of_clk_del_provider(pdev->dev.of_node);
1250
1251        return 0;
1252}
1253
1254static const struct of_device_id inno_hdmi_phy_of_match[] = {
1255        {
1256                .compatible = "rockchip,rk3228-hdmi-phy",
1257                .data = &rk3228_hdmi_phy_drv_data
1258        }, {
1259                .compatible = "rockchip,rk3328-hdmi-phy",
1260                .data = &rk3328_hdmi_phy_drv_data
1261        }, { /* sentinel */ }
1262};
1263MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1264
1265static struct platform_driver inno_hdmi_phy_driver = {
1266        .probe  = inno_hdmi_phy_probe,
1267        .remove = inno_hdmi_phy_remove,
1268        .driver = {
1269                .name = "inno-hdmi-phy",
1270                .of_match_table = inno_hdmi_phy_of_match,
1271        },
1272};
1273module_platform_driver(inno_hdmi_phy_driver);
1274
1275MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");
1276MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1277MODULE_LICENSE("GPL v2");
1278