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40#include <linux/async.h>
41#include <linux/devfreq.h>
42#include <linux/nls.h>
43#include <linux/of.h>
44#include <linux/bitfield.h>
45#include "ufshcd.h"
46#include "ufs_quirks.h"
47#include "unipro.h"
48#include "ufs-sysfs.h"
49#include "ufs_bsg.h"
50
51#define CREATE_TRACE_POINTS
52#include <trace/events/ufs.h>
53
54#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
55 UTP_TASK_REQ_COMPL |\
56 UFSHCD_ERROR_MASK)
57
58#define UIC_CMD_TIMEOUT 500
59
60
61#define NOP_OUT_RETRIES 10
62
63#define NOP_OUT_TIMEOUT 30
64
65
66#define QUERY_REQ_RETRIES 3
67
68#define QUERY_REQ_TIMEOUT 1500
69
70
71#define TM_CMD_TIMEOUT 100
72
73
74#define UFS_UIC_COMMAND_RETRIES 3
75
76
77#define DME_LINKSTARTUP_RETRIES 3
78
79
80#define UIC_HIBERN8_ENTER_RETRIES 3
81
82
83#define MAX_HOST_RESET_RETRIES 5
84
85
86#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
87
88
89#define INT_AGGR_DEF_TO 0x02
90
91#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
92 ({ \
93 int _ret; \
94 if (_on) \
95 _ret = ufshcd_enable_vreg(_dev, _vreg); \
96 else \
97 _ret = ufshcd_disable_vreg(_dev, _vreg); \
98 _ret; \
99 })
100
101#define ufshcd_hex_dump(prefix_str, buf, len) do { \
102 size_t __len = (len); \
103 print_hex_dump(KERN_ERR, prefix_str, \
104 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
105 16, 4, buf, __len, false); \
106} while (0)
107
108int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
109 const char *prefix)
110{
111 u32 *regs;
112 size_t pos;
113
114 if (offset % 4 != 0 || len % 4 != 0)
115 return -EINVAL;
116
117 regs = kzalloc(len, GFP_KERNEL);
118 if (!regs)
119 return -ENOMEM;
120
121 for (pos = 0; pos < len; pos += 4)
122 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
123
124 ufshcd_hex_dump(prefix, regs, len);
125 kfree(regs);
126
127 return 0;
128}
129EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
130
131enum {
132 UFSHCD_MAX_CHANNEL = 0,
133 UFSHCD_MAX_ID = 1,
134 UFSHCD_CMD_PER_LUN = 32,
135 UFSHCD_CAN_QUEUE = 32,
136};
137
138
139enum {
140 UFSHCD_STATE_RESET,
141 UFSHCD_STATE_ERROR,
142 UFSHCD_STATE_OPERATIONAL,
143 UFSHCD_STATE_EH_SCHEDULED,
144};
145
146
147enum {
148 UFSHCD_EH_IN_PROGRESS = (1 << 0),
149};
150
151
152enum {
153 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0),
154 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1),
155 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2),
156 UFSHCD_UIC_NL_ERROR = (1 << 3),
157 UFSHCD_UIC_TL_ERROR = (1 << 4),
158 UFSHCD_UIC_DME_ERROR = (1 << 5),
159};
160
161#define ufshcd_set_eh_in_progress(h) \
162 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
163#define ufshcd_eh_in_progress(h) \
164 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
165#define ufshcd_clear_eh_in_progress(h) \
166 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
167
168#define ufshcd_set_ufs_dev_active(h) \
169 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
170#define ufshcd_set_ufs_dev_sleep(h) \
171 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
172#define ufshcd_set_ufs_dev_poweroff(h) \
173 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
174#define ufshcd_is_ufs_dev_active(h) \
175 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
176#define ufshcd_is_ufs_dev_sleep(h) \
177 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
178#define ufshcd_is_ufs_dev_poweroff(h) \
179 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
180
181struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
182 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
183 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
184 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
185 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
186 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
187 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
188};
189
190static inline enum ufs_dev_pwr_mode
191ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
192{
193 return ufs_pm_lvl_states[lvl].dev_state;
194}
195
196static inline enum uic_link_state
197ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
198{
199 return ufs_pm_lvl_states[lvl].link_state;
200}
201
202static inline enum ufs_pm_level
203ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
204 enum uic_link_state link_state)
205{
206 enum ufs_pm_level lvl;
207
208 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
209 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
210 (ufs_pm_lvl_states[lvl].link_state == link_state))
211 return lvl;
212 }
213
214
215 return UFS_PM_LVL_0;
216}
217
218static struct ufs_dev_fix ufs_fixups[] = {
219
220 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
221 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
222 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
223 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
224 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
225 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
226 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
227 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
228 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
229 UFS_DEVICE_QUIRK_PA_TACTIVATE),
230 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
231 UFS_DEVICE_QUIRK_PA_TACTIVATE),
232 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
233 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
234 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" ,
235 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
236
237 END_FIX
238};
239
240static void ufshcd_tmc_handler(struct ufs_hba *hba);
241static void ufshcd_async_scan(void *data, async_cookie_t cookie);
242static int ufshcd_reset_and_restore(struct ufs_hba *hba);
243static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
244static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
245static void ufshcd_hba_exit(struct ufs_hba *hba);
246static int ufshcd_probe_hba(struct ufs_hba *hba);
247static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
248 bool skip_ref_clk);
249static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
250static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
251static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
252static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
253static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
254static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
255static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
256static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
257static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
258static irqreturn_t ufshcd_intr(int irq, void *__hba);
259static int ufshcd_change_power_mode(struct ufs_hba *hba,
260 struct ufs_pa_layer_attr *pwr_mode);
261static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
262{
263 return tag >= 0 && tag < hba->nutrs;
264}
265
266static inline int ufshcd_enable_irq(struct ufs_hba *hba)
267{
268 int ret = 0;
269
270 if (!hba->is_irq_enabled) {
271 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
272 hba);
273 if (ret)
274 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
275 __func__, ret);
276 hba->is_irq_enabled = true;
277 }
278
279 return ret;
280}
281
282static inline void ufshcd_disable_irq(struct ufs_hba *hba)
283{
284 if (hba->is_irq_enabled) {
285 free_irq(hba->irq, hba);
286 hba->is_irq_enabled = false;
287 }
288}
289
290static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
291{
292 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
293 scsi_unblock_requests(hba->host);
294}
295
296static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
297{
298 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
299 scsi_block_requests(hba->host);
300}
301
302static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
303 const char *str)
304{
305 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
306
307 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
308}
309
310static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
311 const char *str)
312{
313 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
314
315 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
316}
317
318static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
319 const char *str)
320{
321 int off = (int)tag - hba->nutrs;
322 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
323
324 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
325 &descp->input_param1);
326}
327
328static void ufshcd_add_command_trace(struct ufs_hba *hba,
329 unsigned int tag, const char *str)
330{
331 sector_t lba = -1;
332 u8 opcode = 0;
333 u32 intr, doorbell;
334 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
335 int transfer_len = -1;
336
337 if (!trace_ufshcd_command_enabled()) {
338
339 if (lrbp->cmd)
340 ufshcd_add_cmd_upiu_trace(hba, tag, str);
341 return;
342 }
343
344 if (lrbp->cmd) {
345
346 ufshcd_add_cmd_upiu_trace(hba, tag, str);
347 opcode = (u8)(*lrbp->cmd->cmnd);
348 if ((opcode == READ_10) || (opcode == WRITE_10)) {
349
350
351
352
353 if (lrbp->cmd->request && lrbp->cmd->request->bio)
354 lba =
355 lrbp->cmd->request->bio->bi_iter.bi_sector;
356 transfer_len = be32_to_cpu(
357 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
358 }
359 }
360
361 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
362 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
363 trace_ufshcd_command(dev_name(hba->dev), str, tag,
364 doorbell, transfer_len, intr, lba, opcode);
365}
366
367static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
368{
369 struct ufs_clk_info *clki;
370 struct list_head *head = &hba->clk_list_head;
371
372 if (list_empty(head))
373 return;
374
375 list_for_each_entry(clki, head, list) {
376 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
377 clki->max_freq)
378 dev_err(hba->dev, "clk: %s, rate: %u\n",
379 clki->name, clki->curr_freq);
380 }
381}
382
383static void ufshcd_print_err_hist(struct ufs_hba *hba,
384 struct ufs_err_reg_hist *err_hist,
385 char *err_name)
386{
387 int i;
388 bool found = false;
389
390 for (i = 0; i < UFS_ERR_REG_HIST_LENGTH; i++) {
391 int p = (i + err_hist->pos) % UFS_ERR_REG_HIST_LENGTH;
392
393 if (err_hist->reg[p] == 0)
394 continue;
395 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
396 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
397 found = true;
398 }
399
400 if (!found)
401 dev_err(hba->dev, "No record of %s errors\n", err_name);
402}
403
404static void ufshcd_print_host_regs(struct ufs_hba *hba)
405{
406 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
407 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
408 hba->ufs_version, hba->capabilities);
409 dev_err(hba->dev,
410 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
411 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
412 dev_err(hba->dev,
413 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
414 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
415 hba->ufs_stats.hibern8_exit_cnt);
416
417 ufshcd_print_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
418 ufshcd_print_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
419 ufshcd_print_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
420 ufshcd_print_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
421 ufshcd_print_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
422 ufshcd_print_err_hist(hba, &hba->ufs_stats.auto_hibern8_err,
423 "auto_hibern8_err");
424 ufshcd_print_err_hist(hba, &hba->ufs_stats.fatal_err, "fatal_err");
425 ufshcd_print_err_hist(hba, &hba->ufs_stats.link_startup_err,
426 "link_startup_fail");
427 ufshcd_print_err_hist(hba, &hba->ufs_stats.resume_err, "resume_fail");
428 ufshcd_print_err_hist(hba, &hba->ufs_stats.suspend_err,
429 "suspend_fail");
430 ufshcd_print_err_hist(hba, &hba->ufs_stats.dev_reset, "dev_reset");
431 ufshcd_print_err_hist(hba, &hba->ufs_stats.host_reset, "host_reset");
432 ufshcd_print_err_hist(hba, &hba->ufs_stats.task_abort, "task_abort");
433
434 ufshcd_print_clk_freqs(hba);
435
436 if (hba->vops && hba->vops->dbg_register_dump)
437 hba->vops->dbg_register_dump(hba);
438}
439
440static
441void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
442{
443 struct ufshcd_lrb *lrbp;
444 int prdt_length;
445 int tag;
446
447 for_each_set_bit(tag, &bitmap, hba->nutrs) {
448 lrbp = &hba->lrb[tag];
449
450 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
451 tag, ktime_to_us(lrbp->issue_time_stamp));
452 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
453 tag, ktime_to_us(lrbp->compl_time_stamp));
454 dev_err(hba->dev,
455 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
456 tag, (u64)lrbp->utrd_dma_addr);
457
458 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
459 sizeof(struct utp_transfer_req_desc));
460 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
461 (u64)lrbp->ucd_req_dma_addr);
462 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
463 sizeof(struct utp_upiu_req));
464 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
465 (u64)lrbp->ucd_rsp_dma_addr);
466 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
467 sizeof(struct utp_upiu_rsp));
468
469 prdt_length = le16_to_cpu(
470 lrbp->utr_descriptor_ptr->prd_table_length);
471 dev_err(hba->dev,
472 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
473 tag, prdt_length,
474 (u64)lrbp->ucd_prdt_dma_addr);
475
476 if (pr_prdt)
477 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
478 sizeof(struct ufshcd_sg_entry) * prdt_length);
479 }
480}
481
482static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
483{
484 int tag;
485
486 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
487 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
488
489 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
490 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
491 }
492}
493
494static void ufshcd_print_host_state(struct ufs_hba *hba)
495{
496 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
497 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
498 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
499 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
500 hba->saved_err, hba->saved_uic_err);
501 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
502 hba->curr_dev_pwr_mode, hba->uic_link_state);
503 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
504 hba->pm_op_in_progress, hba->is_sys_suspended);
505 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
506 hba->auto_bkops_enabled, hba->host->host_self_blocked);
507 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
508 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
509 hba->eh_flags, hba->req_abort_count);
510 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
511 hba->capabilities, hba->caps);
512 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
513 hba->dev_quirks);
514}
515
516
517
518
519
520
521static void ufshcd_print_pwr_info(struct ufs_hba *hba)
522{
523 static const char * const names[] = {
524 "INVALID MODE",
525 "FAST MODE",
526 "SLOW_MODE",
527 "INVALID MODE",
528 "FASTAUTO_MODE",
529 "SLOWAUTO_MODE",
530 "INVALID MODE",
531 };
532
533 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
534 __func__,
535 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
536 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
537 names[hba->pwr_info.pwr_rx],
538 names[hba->pwr_info.pwr_tx],
539 hba->pwr_info.hs_rate);
540}
541
542
543
544
545
546
547
548
549
550
551
552
553
554int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
555 u32 val, unsigned long interval_us,
556 unsigned long timeout_ms, bool can_sleep)
557{
558 int err = 0;
559 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
560
561
562 val = val & mask;
563
564 while ((ufshcd_readl(hba, reg) & mask) != val) {
565 if (can_sleep)
566 usleep_range(interval_us, interval_us + 50);
567 else
568 udelay(interval_us);
569 if (time_after(jiffies, timeout)) {
570 if ((ufshcd_readl(hba, reg) & mask) != val)
571 err = -ETIMEDOUT;
572 break;
573 }
574 }
575
576 return err;
577}
578
579
580
581
582
583
584
585static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
586{
587 u32 intr_mask = 0;
588
589 switch (hba->ufs_version) {
590 case UFSHCI_VERSION_10:
591 intr_mask = INTERRUPT_MASK_ALL_VER_10;
592 break;
593 case UFSHCI_VERSION_11:
594 case UFSHCI_VERSION_20:
595 intr_mask = INTERRUPT_MASK_ALL_VER_11;
596 break;
597 case UFSHCI_VERSION_21:
598 default:
599 intr_mask = INTERRUPT_MASK_ALL_VER_21;
600 break;
601 }
602
603 return intr_mask;
604}
605
606
607
608
609
610
611
612static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
613{
614 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
615 return ufshcd_vops_get_ufs_hci_version(hba);
616
617 return ufshcd_readl(hba, REG_UFS_VERSION);
618}
619
620
621
622
623
624
625
626
627static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
628{
629 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
630 DEVICE_PRESENT) ? true : false;
631}
632
633
634
635
636
637
638
639
640static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
641{
642 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
643}
644
645
646
647
648
649
650
651
652
653
654static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
655{
656 int tag;
657 bool ret = false;
658
659 if (!free_slot)
660 goto out;
661
662 do {
663 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
664 if (tag >= hba->nutmrs)
665 goto out;
666 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
667
668 *free_slot = tag;
669 ret = true;
670out:
671 return ret;
672}
673
674static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
675{
676 clear_bit_unlock(slot, &hba->tm_slots_in_use);
677}
678
679
680
681
682
683
684static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
685{
686 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
687 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
688 else
689 ufshcd_writel(hba, ~(1 << pos),
690 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
691}
692
693
694
695
696
697
698static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
699{
700 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
701 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
702 else
703 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
704}
705
706
707
708
709
710
711static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
712{
713 __clear_bit(tag, &hba->outstanding_reqs);
714}
715
716
717
718
719
720
721
722static inline int ufshcd_get_lists_status(u32 reg)
723{
724 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
725}
726
727
728
729
730
731
732
733
734static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
735{
736 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
737 MASK_UIC_COMMAND_RESULT;
738}
739
740
741
742
743
744
745
746
747static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
748{
749 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
750}
751
752
753
754
755
756static inline int
757ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
758{
759 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
760}
761
762
763
764
765
766
767
768
769static inline int
770ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
771{
772 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
773}
774
775
776
777
778
779
780
781
782static inline unsigned int
783ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
784{
785 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
786 MASK_RSP_UPIU_DATA_SEG_LEN;
787}
788
789
790
791
792
793
794
795
796
797
798static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
799{
800 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
801 MASK_RSP_EXCEPTION_EVENT ? true : false;
802}
803
804
805
806
807
808static inline void
809ufshcd_reset_intr_aggr(struct ufs_hba *hba)
810{
811 ufshcd_writel(hba, INT_AGGR_ENABLE |
812 INT_AGGR_COUNTER_AND_TIMER_RESET,
813 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
814}
815
816
817
818
819
820
821
822static inline void
823ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
824{
825 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
826 INT_AGGR_COUNTER_THLD_VAL(cnt) |
827 INT_AGGR_TIMEOUT_VAL(tmout),
828 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
829}
830
831
832
833
834
835static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
836{
837 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
838}
839
840
841
842
843
844
845
846static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
847{
848 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
849 REG_UTP_TASK_REQ_LIST_RUN_STOP);
850 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
851 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
852}
853
854
855
856
857
858static inline void ufshcd_hba_start(struct ufs_hba *hba)
859{
860 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
861}
862
863
864
865
866
867
868
869static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
870{
871 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
872 ? false : true;
873}
874
875u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
876{
877
878 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
879 (hba->ufs_version == UFSHCI_VERSION_11))
880 return UFS_UNIPRO_VER_1_41;
881 else
882 return UFS_UNIPRO_VER_1_6;
883}
884EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
885
886static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
887{
888
889
890
891
892
893
894
895
896
897 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
898 return true;
899 else
900 return false;
901}
902
903static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
904{
905 int ret = 0;
906 struct ufs_clk_info *clki;
907 struct list_head *head = &hba->clk_list_head;
908 ktime_t start = ktime_get();
909 bool clk_state_changed = false;
910
911 if (list_empty(head))
912 goto out;
913
914 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
915 if (ret)
916 return ret;
917
918 list_for_each_entry(clki, head, list) {
919 if (!IS_ERR_OR_NULL(clki->clk)) {
920 if (scale_up && clki->max_freq) {
921 if (clki->curr_freq == clki->max_freq)
922 continue;
923
924 clk_state_changed = true;
925 ret = clk_set_rate(clki->clk, clki->max_freq);
926 if (ret) {
927 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
928 __func__, clki->name,
929 clki->max_freq, ret);
930 break;
931 }
932 trace_ufshcd_clk_scaling(dev_name(hba->dev),
933 "scaled up", clki->name,
934 clki->curr_freq,
935 clki->max_freq);
936
937 clki->curr_freq = clki->max_freq;
938
939 } else if (!scale_up && clki->min_freq) {
940 if (clki->curr_freq == clki->min_freq)
941 continue;
942
943 clk_state_changed = true;
944 ret = clk_set_rate(clki->clk, clki->min_freq);
945 if (ret) {
946 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
947 __func__, clki->name,
948 clki->min_freq, ret);
949 break;
950 }
951 trace_ufshcd_clk_scaling(dev_name(hba->dev),
952 "scaled down", clki->name,
953 clki->curr_freq,
954 clki->min_freq);
955 clki->curr_freq = clki->min_freq;
956 }
957 }
958 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
959 clki->name, clk_get_rate(clki->clk));
960 }
961
962 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
963
964out:
965 if (clk_state_changed)
966 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
967 (scale_up ? "up" : "down"),
968 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
969 return ret;
970}
971
972
973
974
975
976
977
978
979static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
980 bool scale_up)
981{
982 struct ufs_clk_info *clki;
983 struct list_head *head = &hba->clk_list_head;
984
985 if (list_empty(head))
986 return false;
987
988 list_for_each_entry(clki, head, list) {
989 if (!IS_ERR_OR_NULL(clki->clk)) {
990 if (scale_up && clki->max_freq) {
991 if (clki->curr_freq == clki->max_freq)
992 continue;
993 return true;
994 } else if (!scale_up && clki->min_freq) {
995 if (clki->curr_freq == clki->min_freq)
996 continue;
997 return true;
998 }
999 }
1000 }
1001
1002 return false;
1003}
1004
1005static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1006 u64 wait_timeout_us)
1007{
1008 unsigned long flags;
1009 int ret = 0;
1010 u32 tm_doorbell;
1011 u32 tr_doorbell;
1012 bool timeout = false, do_last_check = false;
1013 ktime_t start;
1014
1015 ufshcd_hold(hba, false);
1016 spin_lock_irqsave(hba->host->host_lock, flags);
1017
1018
1019
1020
1021 start = ktime_get();
1022 do {
1023 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1024 ret = -EBUSY;
1025 goto out;
1026 }
1027
1028 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1029 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1030 if (!tm_doorbell && !tr_doorbell) {
1031 timeout = false;
1032 break;
1033 } else if (do_last_check) {
1034 break;
1035 }
1036
1037 spin_unlock_irqrestore(hba->host->host_lock, flags);
1038 schedule();
1039 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1040 wait_timeout_us) {
1041 timeout = true;
1042
1043
1044
1045
1046
1047 do_last_check = true;
1048 }
1049 spin_lock_irqsave(hba->host->host_lock, flags);
1050 } while (tm_doorbell || tr_doorbell);
1051
1052 if (timeout) {
1053 dev_err(hba->dev,
1054 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1055 __func__, tm_doorbell, tr_doorbell);
1056 ret = -EBUSY;
1057 }
1058out:
1059 spin_unlock_irqrestore(hba->host->host_lock, flags);
1060 ufshcd_release(hba);
1061 return ret;
1062}
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1074{
1075 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1076 int ret = 0;
1077 struct ufs_pa_layer_attr new_pwr_info;
1078
1079 if (scale_up) {
1080 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1081 sizeof(struct ufs_pa_layer_attr));
1082 } else {
1083 memcpy(&new_pwr_info, &hba->pwr_info,
1084 sizeof(struct ufs_pa_layer_attr));
1085
1086 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1087 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1088
1089 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1090 &hba->pwr_info,
1091 sizeof(struct ufs_pa_layer_attr));
1092
1093
1094 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1095 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1096 }
1097 }
1098
1099
1100 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1101
1102 if (ret)
1103 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1104 __func__, ret,
1105 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1106 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1107
1108 return ret;
1109}
1110
1111static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1112{
1113 #define DOORBELL_CLR_TOUT_US (1000 * 1000)
1114 int ret = 0;
1115
1116
1117
1118
1119 ufshcd_scsi_block_requests(hba);
1120 down_write(&hba->clk_scaling_lock);
1121 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1122 ret = -EBUSY;
1123 up_write(&hba->clk_scaling_lock);
1124 ufshcd_scsi_unblock_requests(hba);
1125 }
1126
1127 return ret;
1128}
1129
1130static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1131{
1132 up_write(&hba->clk_scaling_lock);
1133 ufshcd_scsi_unblock_requests(hba);
1134}
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1146{
1147 int ret = 0;
1148
1149
1150 ufshcd_hold(hba, false);
1151
1152 ret = ufshcd_clock_scaling_prepare(hba);
1153 if (ret)
1154 return ret;
1155
1156
1157 if (!scale_up) {
1158 ret = ufshcd_scale_gear(hba, false);
1159 if (ret)
1160 goto out;
1161 }
1162
1163 ret = ufshcd_scale_clks(hba, scale_up);
1164 if (ret) {
1165 if (!scale_up)
1166 ufshcd_scale_gear(hba, true);
1167 goto out;
1168 }
1169
1170
1171 if (scale_up) {
1172 ret = ufshcd_scale_gear(hba, true);
1173 if (ret) {
1174 ufshcd_scale_clks(hba, false);
1175 goto out;
1176 }
1177 }
1178
1179 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1180
1181out:
1182 ufshcd_clock_scaling_unprepare(hba);
1183 ufshcd_release(hba);
1184 return ret;
1185}
1186
1187static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1188{
1189 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1190 clk_scaling.suspend_work);
1191 unsigned long irq_flags;
1192
1193 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1194 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1195 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1196 return;
1197 }
1198 hba->clk_scaling.is_suspended = true;
1199 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1200
1201 __ufshcd_suspend_clkscaling(hba);
1202}
1203
1204static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1205{
1206 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1207 clk_scaling.resume_work);
1208 unsigned long irq_flags;
1209
1210 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1211 if (!hba->clk_scaling.is_suspended) {
1212 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1213 return;
1214 }
1215 hba->clk_scaling.is_suspended = false;
1216 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1217
1218 devfreq_resume_device(hba->devfreq);
1219}
1220
1221static int ufshcd_devfreq_target(struct device *dev,
1222 unsigned long *freq, u32 flags)
1223{
1224 int ret = 0;
1225 struct ufs_hba *hba = dev_get_drvdata(dev);
1226 ktime_t start;
1227 bool scale_up, sched_clk_scaling_suspend_work = false;
1228 struct list_head *clk_list = &hba->clk_list_head;
1229 struct ufs_clk_info *clki;
1230 unsigned long irq_flags;
1231
1232 if (!ufshcd_is_clkscaling_supported(hba))
1233 return -EINVAL;
1234
1235 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1236 if (ufshcd_eh_in_progress(hba)) {
1237 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1238 return 0;
1239 }
1240
1241 if (!hba->clk_scaling.active_reqs)
1242 sched_clk_scaling_suspend_work = true;
1243
1244 if (list_empty(clk_list)) {
1245 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1246 goto out;
1247 }
1248
1249 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1250 scale_up = (*freq == clki->max_freq) ? true : false;
1251 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1252 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1253 ret = 0;
1254 goto out;
1255 }
1256 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1257
1258 start = ktime_get();
1259 ret = ufshcd_devfreq_scale(hba, scale_up);
1260
1261 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1262 (scale_up ? "up" : "down"),
1263 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1264
1265out:
1266 if (sched_clk_scaling_suspend_work)
1267 queue_work(hba->clk_scaling.workq,
1268 &hba->clk_scaling.suspend_work);
1269
1270 return ret;
1271}
1272
1273
1274static int ufshcd_devfreq_get_dev_status(struct device *dev,
1275 struct devfreq_dev_status *stat)
1276{
1277 struct ufs_hba *hba = dev_get_drvdata(dev);
1278 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1279 unsigned long flags;
1280
1281 if (!ufshcd_is_clkscaling_supported(hba))
1282 return -EINVAL;
1283
1284 memset(stat, 0, sizeof(*stat));
1285
1286 spin_lock_irqsave(hba->host->host_lock, flags);
1287 if (!scaling->window_start_t)
1288 goto start_window;
1289
1290 if (scaling->is_busy_started)
1291 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1292 scaling->busy_start_t));
1293
1294 stat->total_time = jiffies_to_usecs((long)jiffies -
1295 (long)scaling->window_start_t);
1296 stat->busy_time = scaling->tot_busy_t;
1297start_window:
1298 scaling->window_start_t = jiffies;
1299 scaling->tot_busy_t = 0;
1300
1301 if (hba->outstanding_reqs) {
1302 scaling->busy_start_t = ktime_get();
1303 scaling->is_busy_started = true;
1304 } else {
1305 scaling->busy_start_t = 0;
1306 scaling->is_busy_started = false;
1307 }
1308 spin_unlock_irqrestore(hba->host->host_lock, flags);
1309 return 0;
1310}
1311
1312static struct devfreq_dev_profile ufs_devfreq_profile = {
1313 .polling_ms = 100,
1314 .target = ufshcd_devfreq_target,
1315 .get_dev_status = ufshcd_devfreq_get_dev_status,
1316};
1317
1318static int ufshcd_devfreq_init(struct ufs_hba *hba)
1319{
1320 struct list_head *clk_list = &hba->clk_list_head;
1321 struct ufs_clk_info *clki;
1322 struct devfreq *devfreq;
1323 int ret;
1324
1325
1326 if (list_empty(clk_list))
1327 return 0;
1328
1329 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1330 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1331 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1332
1333 devfreq = devfreq_add_device(hba->dev,
1334 &ufs_devfreq_profile,
1335 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1336 NULL);
1337 if (IS_ERR(devfreq)) {
1338 ret = PTR_ERR(devfreq);
1339 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1340
1341 dev_pm_opp_remove(hba->dev, clki->min_freq);
1342 dev_pm_opp_remove(hba->dev, clki->max_freq);
1343 return ret;
1344 }
1345
1346 hba->devfreq = devfreq;
1347
1348 return 0;
1349}
1350
1351static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1352{
1353 struct list_head *clk_list = &hba->clk_list_head;
1354 struct ufs_clk_info *clki;
1355
1356 if (!hba->devfreq)
1357 return;
1358
1359 devfreq_remove_device(hba->devfreq);
1360 hba->devfreq = NULL;
1361
1362 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1363 dev_pm_opp_remove(hba->dev, clki->min_freq);
1364 dev_pm_opp_remove(hba->dev, clki->max_freq);
1365}
1366
1367static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1368{
1369 unsigned long flags;
1370
1371 devfreq_suspend_device(hba->devfreq);
1372 spin_lock_irqsave(hba->host->host_lock, flags);
1373 hba->clk_scaling.window_start_t = 0;
1374 spin_unlock_irqrestore(hba->host->host_lock, flags);
1375}
1376
1377static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1378{
1379 unsigned long flags;
1380 bool suspend = false;
1381
1382 if (!ufshcd_is_clkscaling_supported(hba))
1383 return;
1384
1385 spin_lock_irqsave(hba->host->host_lock, flags);
1386 if (!hba->clk_scaling.is_suspended) {
1387 suspend = true;
1388 hba->clk_scaling.is_suspended = true;
1389 }
1390 spin_unlock_irqrestore(hba->host->host_lock, flags);
1391
1392 if (suspend)
1393 __ufshcd_suspend_clkscaling(hba);
1394}
1395
1396static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1397{
1398 unsigned long flags;
1399 bool resume = false;
1400
1401 if (!ufshcd_is_clkscaling_supported(hba))
1402 return;
1403
1404 spin_lock_irqsave(hba->host->host_lock, flags);
1405 if (hba->clk_scaling.is_suspended) {
1406 resume = true;
1407 hba->clk_scaling.is_suspended = false;
1408 }
1409 spin_unlock_irqrestore(hba->host->host_lock, flags);
1410
1411 if (resume)
1412 devfreq_resume_device(hba->devfreq);
1413}
1414
1415static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1416 struct device_attribute *attr, char *buf)
1417{
1418 struct ufs_hba *hba = dev_get_drvdata(dev);
1419
1420 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1421}
1422
1423static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1424 struct device_attribute *attr, const char *buf, size_t count)
1425{
1426 struct ufs_hba *hba = dev_get_drvdata(dev);
1427 u32 value;
1428 int err;
1429
1430 if (kstrtou32(buf, 0, &value))
1431 return -EINVAL;
1432
1433 value = !!value;
1434 if (value == hba->clk_scaling.is_allowed)
1435 goto out;
1436
1437 pm_runtime_get_sync(hba->dev);
1438 ufshcd_hold(hba, false);
1439
1440 cancel_work_sync(&hba->clk_scaling.suspend_work);
1441 cancel_work_sync(&hba->clk_scaling.resume_work);
1442
1443 hba->clk_scaling.is_allowed = value;
1444
1445 if (value) {
1446 ufshcd_resume_clkscaling(hba);
1447 } else {
1448 ufshcd_suspend_clkscaling(hba);
1449 err = ufshcd_devfreq_scale(hba, true);
1450 if (err)
1451 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1452 __func__, err);
1453 }
1454
1455 ufshcd_release(hba);
1456 pm_runtime_put_sync(hba->dev);
1457out:
1458 return count;
1459}
1460
1461static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1462{
1463 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1464 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1465 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1466 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1467 hba->clk_scaling.enable_attr.attr.mode = 0644;
1468 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1469 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1470}
1471
1472static void ufshcd_ungate_work(struct work_struct *work)
1473{
1474 int ret;
1475 unsigned long flags;
1476 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1477 clk_gating.ungate_work);
1478
1479 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1480
1481 spin_lock_irqsave(hba->host->host_lock, flags);
1482 if (hba->clk_gating.state == CLKS_ON) {
1483 spin_unlock_irqrestore(hba->host->host_lock, flags);
1484 goto unblock_reqs;
1485 }
1486
1487 spin_unlock_irqrestore(hba->host->host_lock, flags);
1488 ufshcd_setup_clocks(hba, true);
1489
1490
1491 if (ufshcd_can_hibern8_during_gating(hba)) {
1492
1493 hba->clk_gating.is_suspended = true;
1494 if (ufshcd_is_link_hibern8(hba)) {
1495 ret = ufshcd_uic_hibern8_exit(hba);
1496 if (ret)
1497 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1498 __func__, ret);
1499 else
1500 ufshcd_set_link_active(hba);
1501 }
1502 hba->clk_gating.is_suspended = false;
1503 }
1504unblock_reqs:
1505 ufshcd_scsi_unblock_requests(hba);
1506}
1507
1508
1509
1510
1511
1512
1513
1514int ufshcd_hold(struct ufs_hba *hba, bool async)
1515{
1516 int rc = 0;
1517 unsigned long flags;
1518
1519 if (!ufshcd_is_clkgating_allowed(hba))
1520 goto out;
1521 spin_lock_irqsave(hba->host->host_lock, flags);
1522 hba->clk_gating.active_reqs++;
1523
1524 if (ufshcd_eh_in_progress(hba)) {
1525 spin_unlock_irqrestore(hba->host->host_lock, flags);
1526 return 0;
1527 }
1528
1529start:
1530 switch (hba->clk_gating.state) {
1531 case CLKS_ON:
1532
1533
1534
1535
1536
1537
1538
1539
1540 if (ufshcd_can_hibern8_during_gating(hba) &&
1541 ufshcd_is_link_hibern8(hba)) {
1542 spin_unlock_irqrestore(hba->host->host_lock, flags);
1543 flush_work(&hba->clk_gating.ungate_work);
1544 spin_lock_irqsave(hba->host->host_lock, flags);
1545 goto start;
1546 }
1547 break;
1548 case REQ_CLKS_OFF:
1549 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1550 hba->clk_gating.state = CLKS_ON;
1551 trace_ufshcd_clk_gating(dev_name(hba->dev),
1552 hba->clk_gating.state);
1553 break;
1554 }
1555
1556
1557
1558
1559
1560
1561 case CLKS_OFF:
1562 ufshcd_scsi_block_requests(hba);
1563 hba->clk_gating.state = REQ_CLKS_ON;
1564 trace_ufshcd_clk_gating(dev_name(hba->dev),
1565 hba->clk_gating.state);
1566 queue_work(hba->clk_gating.clk_gating_workq,
1567 &hba->clk_gating.ungate_work);
1568
1569
1570
1571
1572
1573 case REQ_CLKS_ON:
1574 if (async) {
1575 rc = -EAGAIN;
1576 hba->clk_gating.active_reqs--;
1577 break;
1578 }
1579
1580 spin_unlock_irqrestore(hba->host->host_lock, flags);
1581 flush_work(&hba->clk_gating.ungate_work);
1582
1583 spin_lock_irqsave(hba->host->host_lock, flags);
1584 goto start;
1585 default:
1586 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1587 __func__, hba->clk_gating.state);
1588 break;
1589 }
1590 spin_unlock_irqrestore(hba->host->host_lock, flags);
1591out:
1592 return rc;
1593}
1594EXPORT_SYMBOL_GPL(ufshcd_hold);
1595
1596static void ufshcd_gate_work(struct work_struct *work)
1597{
1598 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1599 clk_gating.gate_work.work);
1600 unsigned long flags;
1601
1602 spin_lock_irqsave(hba->host->host_lock, flags);
1603
1604
1605
1606
1607
1608
1609 if (hba->clk_gating.is_suspended ||
1610 (hba->clk_gating.state == REQ_CLKS_ON)) {
1611 hba->clk_gating.state = CLKS_ON;
1612 trace_ufshcd_clk_gating(dev_name(hba->dev),
1613 hba->clk_gating.state);
1614 goto rel_lock;
1615 }
1616
1617 if (hba->clk_gating.active_reqs
1618 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1619 || hba->lrb_in_use || hba->outstanding_tasks
1620 || hba->active_uic_cmd || hba->uic_async_done)
1621 goto rel_lock;
1622
1623 spin_unlock_irqrestore(hba->host->host_lock, flags);
1624
1625
1626 if (ufshcd_can_hibern8_during_gating(hba)) {
1627 if (ufshcd_uic_hibern8_enter(hba)) {
1628 hba->clk_gating.state = CLKS_ON;
1629 trace_ufshcd_clk_gating(dev_name(hba->dev),
1630 hba->clk_gating.state);
1631 goto out;
1632 }
1633 ufshcd_set_link_hibern8(hba);
1634 }
1635
1636 if (!ufshcd_is_link_active(hba))
1637 ufshcd_setup_clocks(hba, false);
1638 else
1639
1640 __ufshcd_setup_clocks(hba, false, true);
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651 spin_lock_irqsave(hba->host->host_lock, flags);
1652 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1653 hba->clk_gating.state = CLKS_OFF;
1654 trace_ufshcd_clk_gating(dev_name(hba->dev),
1655 hba->clk_gating.state);
1656 }
1657rel_lock:
1658 spin_unlock_irqrestore(hba->host->host_lock, flags);
1659out:
1660 return;
1661}
1662
1663
1664static void __ufshcd_release(struct ufs_hba *hba)
1665{
1666 if (!ufshcd_is_clkgating_allowed(hba))
1667 return;
1668
1669 hba->clk_gating.active_reqs--;
1670
1671 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1672 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1673 || hba->lrb_in_use || hba->outstanding_tasks
1674 || hba->active_uic_cmd || hba->uic_async_done
1675 || ufshcd_eh_in_progress(hba))
1676 return;
1677
1678 hba->clk_gating.state = REQ_CLKS_OFF;
1679 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1680 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1681 &hba->clk_gating.gate_work,
1682 msecs_to_jiffies(hba->clk_gating.delay_ms));
1683}
1684
1685void ufshcd_release(struct ufs_hba *hba)
1686{
1687 unsigned long flags;
1688
1689 spin_lock_irqsave(hba->host->host_lock, flags);
1690 __ufshcd_release(hba);
1691 spin_unlock_irqrestore(hba->host->host_lock, flags);
1692}
1693EXPORT_SYMBOL_GPL(ufshcd_release);
1694
1695static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1696 struct device_attribute *attr, char *buf)
1697{
1698 struct ufs_hba *hba = dev_get_drvdata(dev);
1699
1700 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1701}
1702
1703static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1704 struct device_attribute *attr, const char *buf, size_t count)
1705{
1706 struct ufs_hba *hba = dev_get_drvdata(dev);
1707 unsigned long flags, value;
1708
1709 if (kstrtoul(buf, 0, &value))
1710 return -EINVAL;
1711
1712 spin_lock_irqsave(hba->host->host_lock, flags);
1713 hba->clk_gating.delay_ms = value;
1714 spin_unlock_irqrestore(hba->host->host_lock, flags);
1715 return count;
1716}
1717
1718static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1719 struct device_attribute *attr, char *buf)
1720{
1721 struct ufs_hba *hba = dev_get_drvdata(dev);
1722
1723 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1724}
1725
1726static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1727 struct device_attribute *attr, const char *buf, size_t count)
1728{
1729 struct ufs_hba *hba = dev_get_drvdata(dev);
1730 unsigned long flags;
1731 u32 value;
1732
1733 if (kstrtou32(buf, 0, &value))
1734 return -EINVAL;
1735
1736 value = !!value;
1737 if (value == hba->clk_gating.is_enabled)
1738 goto out;
1739
1740 if (value) {
1741 ufshcd_release(hba);
1742 } else {
1743 spin_lock_irqsave(hba->host->host_lock, flags);
1744 hba->clk_gating.active_reqs++;
1745 spin_unlock_irqrestore(hba->host->host_lock, flags);
1746 }
1747
1748 hba->clk_gating.is_enabled = value;
1749out:
1750 return count;
1751}
1752
1753static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1754{
1755 char wq_name[sizeof("ufs_clkscaling_00")];
1756
1757 if (!ufshcd_is_clkscaling_supported(hba))
1758 return;
1759
1760 INIT_WORK(&hba->clk_scaling.suspend_work,
1761 ufshcd_clk_scaling_suspend_work);
1762 INIT_WORK(&hba->clk_scaling.resume_work,
1763 ufshcd_clk_scaling_resume_work);
1764
1765 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1766 hba->host->host_no);
1767 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1768
1769 ufshcd_clkscaling_init_sysfs(hba);
1770}
1771
1772static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1773{
1774 if (!ufshcd_is_clkscaling_supported(hba))
1775 return;
1776
1777 destroy_workqueue(hba->clk_scaling.workq);
1778 ufshcd_devfreq_remove(hba);
1779}
1780
1781static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1782{
1783 char wq_name[sizeof("ufs_clk_gating_00")];
1784
1785 if (!ufshcd_is_clkgating_allowed(hba))
1786 return;
1787
1788 hba->clk_gating.delay_ms = 150;
1789 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1790 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1791
1792 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1793 hba->host->host_no);
1794 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1795 WQ_MEM_RECLAIM);
1796
1797 hba->clk_gating.is_enabled = true;
1798
1799 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1800 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1801 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1802 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1803 hba->clk_gating.delay_attr.attr.mode = 0644;
1804 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1805 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1806
1807 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1808 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1809 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1810 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1811 hba->clk_gating.enable_attr.attr.mode = 0644;
1812 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1813 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1814}
1815
1816static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1817{
1818 if (!ufshcd_is_clkgating_allowed(hba))
1819 return;
1820 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1821 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1822 cancel_work_sync(&hba->clk_gating.ungate_work);
1823 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1824 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1825}
1826
1827
1828static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1829{
1830 bool queue_resume_work = false;
1831
1832 if (!ufshcd_is_clkscaling_supported(hba))
1833 return;
1834
1835 if (!hba->clk_scaling.active_reqs++)
1836 queue_resume_work = true;
1837
1838 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1839 return;
1840
1841 if (queue_resume_work)
1842 queue_work(hba->clk_scaling.workq,
1843 &hba->clk_scaling.resume_work);
1844
1845 if (!hba->clk_scaling.window_start_t) {
1846 hba->clk_scaling.window_start_t = jiffies;
1847 hba->clk_scaling.tot_busy_t = 0;
1848 hba->clk_scaling.is_busy_started = false;
1849 }
1850
1851 if (!hba->clk_scaling.is_busy_started) {
1852 hba->clk_scaling.busy_start_t = ktime_get();
1853 hba->clk_scaling.is_busy_started = true;
1854 }
1855}
1856
1857static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1858{
1859 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1860
1861 if (!ufshcd_is_clkscaling_supported(hba))
1862 return;
1863
1864 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1865 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1866 scaling->busy_start_t));
1867 scaling->busy_start_t = 0;
1868 scaling->is_busy_started = false;
1869 }
1870}
1871
1872
1873
1874
1875
1876static inline
1877void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1878{
1879 hba->lrb[task_tag].issue_time_stamp = ktime_get();
1880 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
1881 ufshcd_clk_scaling_start_busy(hba);
1882 __set_bit(task_tag, &hba->outstanding_reqs);
1883 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1884
1885 wmb();
1886 ufshcd_add_command_trace(hba, task_tag, "send");
1887}
1888
1889
1890
1891
1892
1893static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1894{
1895 int len;
1896 if (lrbp->sense_buffer &&
1897 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
1898 int len_to_copy;
1899
1900 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
1901 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
1902
1903 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1904 len_to_copy);
1905 }
1906}
1907
1908
1909
1910
1911
1912
1913
1914static
1915int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1916{
1917 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1918
1919 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
1920
1921
1922 if (hba->dev_cmd.query.descriptor &&
1923 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
1924 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
1925 GENERAL_UPIU_REQUEST_SIZE;
1926 u16 resp_len;
1927 u16 buf_len;
1928
1929
1930 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
1931 MASK_QUERY_DATA_SEG_LEN;
1932 buf_len = be16_to_cpu(
1933 hba->dev_cmd.query.request.upiu_req.length);
1934 if (likely(buf_len >= resp_len)) {
1935 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1936 } else {
1937 dev_warn(hba->dev,
1938 "%s: Response size is bigger than buffer",
1939 __func__);
1940 return -EINVAL;
1941 }
1942 }
1943
1944 return 0;
1945}
1946
1947
1948
1949
1950
1951static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1952{
1953 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
1954
1955
1956 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1957 hba->nutmrs =
1958 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1959}
1960
1961
1962
1963
1964
1965
1966
1967static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1968{
1969 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1970 return true;
1971 else
1972 return false;
1973}
1974
1975
1976
1977
1978
1979
1980
1981
1982static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1983{
1984 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1985}
1986
1987
1988
1989
1990
1991
1992
1993
1994static inline void
1995ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1996{
1997 WARN_ON(hba->active_uic_cmd);
1998
1999 hba->active_uic_cmd = uic_cmd;
2000
2001
2002 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2003 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2004 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2005
2006
2007 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2008 REG_UIC_COMMAND);
2009}
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019static int
2020ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2021{
2022 int ret;
2023 unsigned long flags;
2024
2025 if (wait_for_completion_timeout(&uic_cmd->done,
2026 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2027 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2028 else
2029 ret = -ETIMEDOUT;
2030
2031 spin_lock_irqsave(hba->host->host_lock, flags);
2032 hba->active_uic_cmd = NULL;
2033 spin_unlock_irqrestore(hba->host->host_lock, flags);
2034
2035 return ret;
2036}
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048static int
2049__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2050 bool completion)
2051{
2052 if (!ufshcd_ready_for_uic_cmd(hba)) {
2053 dev_err(hba->dev,
2054 "Controller not ready to accept UIC commands\n");
2055 return -EIO;
2056 }
2057
2058 if (completion)
2059 init_completion(&uic_cmd->done);
2060
2061 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2062
2063 return 0;
2064}
2065
2066
2067
2068
2069
2070
2071
2072
2073int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2074{
2075 int ret;
2076 unsigned long flags;
2077
2078 ufshcd_hold(hba, false);
2079 mutex_lock(&hba->uic_cmd_mutex);
2080 ufshcd_add_delay_before_dme_cmd(hba);
2081
2082 spin_lock_irqsave(hba->host->host_lock, flags);
2083 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2084 spin_unlock_irqrestore(hba->host->host_lock, flags);
2085 if (!ret)
2086 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2087
2088 mutex_unlock(&hba->uic_cmd_mutex);
2089
2090 ufshcd_release(hba);
2091 return ret;
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2102{
2103 struct ufshcd_sg_entry *prd_table;
2104 struct scatterlist *sg;
2105 struct scsi_cmnd *cmd;
2106 int sg_segments;
2107 int i;
2108
2109 cmd = lrbp->cmd;
2110 sg_segments = scsi_dma_map(cmd);
2111 if (sg_segments < 0)
2112 return sg_segments;
2113
2114 if (sg_segments) {
2115 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2116 lrbp->utr_descriptor_ptr->prd_table_length =
2117 cpu_to_le16((u16)(sg_segments *
2118 sizeof(struct ufshcd_sg_entry)));
2119 else
2120 lrbp->utr_descriptor_ptr->prd_table_length =
2121 cpu_to_le16((u16) (sg_segments));
2122
2123 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2124
2125 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2126 prd_table[i].size =
2127 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2128 prd_table[i].base_addr =
2129 cpu_to_le32(lower_32_bits(sg->dma_address));
2130 prd_table[i].upper_addr =
2131 cpu_to_le32(upper_32_bits(sg->dma_address));
2132 prd_table[i].reserved = 0;
2133 }
2134 } else {
2135 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2136 }
2137
2138 return 0;
2139}
2140
2141
2142
2143
2144
2145
2146static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2147{
2148 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2149
2150 if (hba->ufs_version == UFSHCI_VERSION_10) {
2151 u32 rw;
2152 rw = set & INTERRUPT_MASK_RW_VER_10;
2153 set = rw | ((set ^ intrs) & intrs);
2154 } else {
2155 set |= intrs;
2156 }
2157
2158 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2159}
2160
2161
2162
2163
2164
2165
2166static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2167{
2168 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2169
2170 if (hba->ufs_version == UFSHCI_VERSION_10) {
2171 u32 rw;
2172 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2173 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2174 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2175
2176 } else {
2177 set &= ~intrs;
2178 }
2179
2180 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2181}
2182
2183
2184
2185
2186
2187
2188
2189
2190static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2191 u32 *upiu_flags, enum dma_data_direction cmd_dir)
2192{
2193 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2194 u32 data_direction;
2195 u32 dword_0;
2196
2197 if (cmd_dir == DMA_FROM_DEVICE) {
2198 data_direction = UTP_DEVICE_TO_HOST;
2199 *upiu_flags = UPIU_CMD_FLAGS_READ;
2200 } else if (cmd_dir == DMA_TO_DEVICE) {
2201 data_direction = UTP_HOST_TO_DEVICE;
2202 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2203 } else {
2204 data_direction = UTP_NO_DATA_TRANSFER;
2205 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2206 }
2207
2208 dword_0 = data_direction | (lrbp->command_type
2209 << UPIU_COMMAND_TYPE_OFFSET);
2210 if (lrbp->intr_cmd)
2211 dword_0 |= UTP_REQ_DESC_INT_CMD;
2212
2213
2214 req_desc->header.dword_0 = cpu_to_le32(dword_0);
2215
2216 req_desc->header.dword_1 = 0;
2217
2218
2219
2220
2221
2222 req_desc->header.dword_2 =
2223 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2224
2225 req_desc->header.dword_3 = 0;
2226
2227 req_desc->prd_table_length = 0;
2228}
2229
2230
2231
2232
2233
2234
2235
2236static
2237void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2238{
2239 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2240 unsigned short cdb_len;
2241
2242
2243 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2244 UPIU_TRANSACTION_COMMAND, upiu_flags,
2245 lrbp->lun, lrbp->task_tag);
2246 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2247 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2248
2249
2250 ucd_req_ptr->header.dword_2 = 0;
2251
2252 ucd_req_ptr->sc.exp_data_transfer_len =
2253 cpu_to_be32(lrbp->cmd->sdb.length);
2254
2255 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, UFS_CDB_SIZE);
2256 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2257 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2258
2259 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2260}
2261
2262
2263
2264
2265
2266
2267
2268
2269static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2270 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2271{
2272 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2273 struct ufs_query *query = &hba->dev_cmd.query;
2274 u16 len = be16_to_cpu(query->request.upiu_req.length);
2275
2276
2277 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2278 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2279 lrbp->lun, lrbp->task_tag);
2280 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2281 0, query->request.query_func, 0, 0);
2282
2283
2284 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2285 ucd_req_ptr->header.dword_2 =
2286 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2287 else
2288 ucd_req_ptr->header.dword_2 = 0;
2289
2290
2291 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2292 QUERY_OSF_SIZE);
2293
2294
2295 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2296 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2297
2298 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2299}
2300
2301static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2302{
2303 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2304
2305 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2306
2307
2308 ucd_req_ptr->header.dword_0 =
2309 UPIU_HEADER_DWORD(
2310 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2311
2312 ucd_req_ptr->header.dword_1 = 0;
2313 ucd_req_ptr->header.dword_2 = 0;
2314
2315 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2316}
2317
2318
2319
2320
2321
2322
2323
2324static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2325{
2326 u32 upiu_flags;
2327 int ret = 0;
2328
2329 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2330 (hba->ufs_version == UFSHCI_VERSION_11))
2331 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2332 else
2333 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2334
2335 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2336 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2337 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2338 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2339 ufshcd_prepare_utp_nop_upiu(lrbp);
2340 else
2341 ret = -EINVAL;
2342
2343 return ret;
2344}
2345
2346
2347
2348
2349
2350
2351
2352static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2353{
2354 u32 upiu_flags;
2355 int ret = 0;
2356
2357 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2358 (hba->ufs_version == UFSHCI_VERSION_11))
2359 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2360 else
2361 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2362
2363 if (likely(lrbp->cmd)) {
2364 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2365 lrbp->cmd->sc_data_direction);
2366 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2367 } else {
2368 ret = -EINVAL;
2369 }
2370
2371 return ret;
2372}
2373
2374
2375
2376
2377
2378
2379
2380static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2381{
2382 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2383}
2384
2385
2386
2387
2388
2389
2390
2391
2392static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2393{
2394 struct ufshcd_lrb *lrbp;
2395 struct ufs_hba *hba;
2396 unsigned long flags;
2397 int tag;
2398 int err = 0;
2399
2400 hba = shost_priv(host);
2401
2402 tag = cmd->request->tag;
2403 if (!ufshcd_valid_tag(hba, tag)) {
2404 dev_err(hba->dev,
2405 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2406 __func__, tag, cmd, cmd->request);
2407 BUG();
2408 }
2409
2410 if (!down_read_trylock(&hba->clk_scaling_lock))
2411 return SCSI_MLQUEUE_HOST_BUSY;
2412
2413 spin_lock_irqsave(hba->host->host_lock, flags);
2414 switch (hba->ufshcd_state) {
2415 case UFSHCD_STATE_OPERATIONAL:
2416 break;
2417 case UFSHCD_STATE_EH_SCHEDULED:
2418 case UFSHCD_STATE_RESET:
2419 err = SCSI_MLQUEUE_HOST_BUSY;
2420 goto out_unlock;
2421 case UFSHCD_STATE_ERROR:
2422 set_host_byte(cmd, DID_ERROR);
2423 cmd->scsi_done(cmd);
2424 goto out_unlock;
2425 default:
2426 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2427 __func__, hba->ufshcd_state);
2428 set_host_byte(cmd, DID_BAD_TARGET);
2429 cmd->scsi_done(cmd);
2430 goto out_unlock;
2431 }
2432
2433
2434 if (ufshcd_eh_in_progress(hba)) {
2435 set_host_byte(cmd, DID_ERROR);
2436 cmd->scsi_done(cmd);
2437 goto out_unlock;
2438 }
2439 spin_unlock_irqrestore(hba->host->host_lock, flags);
2440
2441 hba->req_abort_count = 0;
2442
2443
2444 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2445
2446
2447
2448
2449
2450
2451 err = SCSI_MLQUEUE_HOST_BUSY;
2452 goto out;
2453 }
2454
2455 err = ufshcd_hold(hba, true);
2456 if (err) {
2457 err = SCSI_MLQUEUE_HOST_BUSY;
2458 clear_bit_unlock(tag, &hba->lrb_in_use);
2459 goto out;
2460 }
2461 WARN_ON(hba->clk_gating.state != CLKS_ON);
2462
2463 lrbp = &hba->lrb[tag];
2464
2465 WARN_ON(lrbp->cmd);
2466 lrbp->cmd = cmd;
2467 lrbp->sense_bufflen = UFS_SENSE_SIZE;
2468 lrbp->sense_buffer = cmd->sense_buffer;
2469 lrbp->task_tag = tag;
2470 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2471 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2472 lrbp->req_abort_skip = false;
2473
2474 ufshcd_comp_scsi_upiu(hba, lrbp);
2475
2476 err = ufshcd_map_sg(hba, lrbp);
2477 if (err) {
2478 lrbp->cmd = NULL;
2479 clear_bit_unlock(tag, &hba->lrb_in_use);
2480 goto out;
2481 }
2482
2483 wmb();
2484
2485
2486 spin_lock_irqsave(hba->host->host_lock, flags);
2487 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
2488 ufshcd_send_command(hba, tag);
2489out_unlock:
2490 spin_unlock_irqrestore(hba->host->host_lock, flags);
2491out:
2492 up_read(&hba->clk_scaling_lock);
2493 return err;
2494}
2495
2496static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2497 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2498{
2499 lrbp->cmd = NULL;
2500 lrbp->sense_bufflen = 0;
2501 lrbp->sense_buffer = NULL;
2502 lrbp->task_tag = tag;
2503 lrbp->lun = 0;
2504 lrbp->intr_cmd = true;
2505 hba->dev_cmd.type = cmd_type;
2506
2507 return ufshcd_comp_devman_upiu(hba, lrbp);
2508}
2509
2510static int
2511ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2512{
2513 int err = 0;
2514 unsigned long flags;
2515 u32 mask = 1 << tag;
2516
2517
2518 spin_lock_irqsave(hba->host->host_lock, flags);
2519 ufshcd_utrl_clear(hba, tag);
2520 spin_unlock_irqrestore(hba->host->host_lock, flags);
2521
2522
2523
2524
2525
2526 err = ufshcd_wait_for_register(hba,
2527 REG_UTP_TRANSFER_REQ_DOOR_BELL,
2528 mask, ~mask, 1000, 1000, true);
2529
2530 return err;
2531}
2532
2533static int
2534ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2535{
2536 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2537
2538
2539 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2540 UPIU_RSP_CODE_OFFSET;
2541 return query_res->response;
2542}
2543
2544
2545
2546
2547
2548
2549static int
2550ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2551{
2552 int resp;
2553 int err = 0;
2554
2555 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2556 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2557
2558 switch (resp) {
2559 case UPIU_TRANSACTION_NOP_IN:
2560 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2561 err = -EINVAL;
2562 dev_err(hba->dev, "%s: unexpected response %x\n",
2563 __func__, resp);
2564 }
2565 break;
2566 case UPIU_TRANSACTION_QUERY_RSP:
2567 err = ufshcd_check_query_response(hba, lrbp);
2568 if (!err)
2569 err = ufshcd_copy_query_response(hba, lrbp);
2570 break;
2571 case UPIU_TRANSACTION_REJECT_UPIU:
2572
2573 err = -EPERM;
2574 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2575 __func__);
2576 break;
2577 default:
2578 err = -EINVAL;
2579 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2580 __func__, resp);
2581 break;
2582 }
2583
2584 return err;
2585}
2586
2587static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2588 struct ufshcd_lrb *lrbp, int max_timeout)
2589{
2590 int err = 0;
2591 unsigned long time_left;
2592 unsigned long flags;
2593
2594 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2595 msecs_to_jiffies(max_timeout));
2596
2597
2598 wmb();
2599 spin_lock_irqsave(hba->host->host_lock, flags);
2600 hba->dev_cmd.complete = NULL;
2601 if (likely(time_left)) {
2602 err = ufshcd_get_tr_ocs(lrbp);
2603 if (!err)
2604 err = ufshcd_dev_cmd_completion(hba, lrbp);
2605 }
2606 spin_unlock_irqrestore(hba->host->host_lock, flags);
2607
2608 if (!time_left) {
2609 err = -ETIMEDOUT;
2610 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2611 __func__, lrbp->task_tag);
2612 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2613
2614 err = -EAGAIN;
2615
2616
2617
2618
2619
2620 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
2621 }
2622
2623 return err;
2624}
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2638{
2639 int tag;
2640 bool ret = false;
2641 unsigned long tmp;
2642
2643 if (!tag_out)
2644 goto out;
2645
2646 do {
2647 tmp = ~hba->lrb_in_use;
2648 tag = find_last_bit(&tmp, hba->nutrs);
2649 if (tag >= hba->nutrs)
2650 goto out;
2651 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2652
2653 *tag_out = tag;
2654 ret = true;
2655out:
2656 return ret;
2657}
2658
2659static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2660{
2661 clear_bit_unlock(tag, &hba->lrb_in_use);
2662}
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2674 enum dev_cmd_type cmd_type, int timeout)
2675{
2676 struct ufshcd_lrb *lrbp;
2677 int err;
2678 int tag;
2679 struct completion wait;
2680 unsigned long flags;
2681
2682 down_read(&hba->clk_scaling_lock);
2683
2684
2685
2686
2687
2688
2689 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2690
2691 init_completion(&wait);
2692 lrbp = &hba->lrb[tag];
2693 WARN_ON(lrbp->cmd);
2694 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2695 if (unlikely(err))
2696 goto out_put_tag;
2697
2698 hba->dev_cmd.complete = &wait;
2699
2700 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
2701
2702 wmb();
2703 spin_lock_irqsave(hba->host->host_lock, flags);
2704 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
2705 ufshcd_send_command(hba, tag);
2706 spin_unlock_irqrestore(hba->host->host_lock, flags);
2707
2708 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2709
2710 ufshcd_add_query_upiu_trace(hba, tag,
2711 err ? "query_complete_err" : "query_complete");
2712
2713out_put_tag:
2714 ufshcd_put_dev_cmd_tag(hba, tag);
2715 wake_up(&hba->dev_cmd.tag_wq);
2716 up_read(&hba->clk_scaling_lock);
2717 return err;
2718}
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730static inline void ufshcd_init_query(struct ufs_hba *hba,
2731 struct ufs_query_req **request, struct ufs_query_res **response,
2732 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2733{
2734 *request = &hba->dev_cmd.query.request;
2735 *response = &hba->dev_cmd.query.response;
2736 memset(*request, 0, sizeof(struct ufs_query_req));
2737 memset(*response, 0, sizeof(struct ufs_query_res));
2738 (*request)->upiu_req.opcode = opcode;
2739 (*request)->upiu_req.idn = idn;
2740 (*request)->upiu_req.index = index;
2741 (*request)->upiu_req.selector = selector;
2742}
2743
2744static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2745 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2746{
2747 int ret;
2748 int retries;
2749
2750 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2751 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2752 if (ret)
2753 dev_dbg(hba->dev,
2754 "%s: failed with error %d, retries %d\n",
2755 __func__, ret, retries);
2756 else
2757 break;
2758 }
2759
2760 if (ret)
2761 dev_err(hba->dev,
2762 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2763 __func__, opcode, idn, ret, retries);
2764 return ret;
2765}
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
2777 enum flag_idn idn, bool *flag_res)
2778{
2779 struct ufs_query_req *request = NULL;
2780 struct ufs_query_res *response = NULL;
2781 int err, index = 0, selector = 0;
2782 int timeout = QUERY_REQ_TIMEOUT;
2783
2784 BUG_ON(!hba);
2785
2786 ufshcd_hold(hba, false);
2787 mutex_lock(&hba->dev_cmd.lock);
2788 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2789 selector);
2790
2791 switch (opcode) {
2792 case UPIU_QUERY_OPCODE_SET_FLAG:
2793 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2794 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2795 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2796 break;
2797 case UPIU_QUERY_OPCODE_READ_FLAG:
2798 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2799 if (!flag_res) {
2800
2801 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2802 __func__);
2803 err = -EINVAL;
2804 goto out_unlock;
2805 }
2806 break;
2807 default:
2808 dev_err(hba->dev,
2809 "%s: Expected query flag opcode but got = %d\n",
2810 __func__, opcode);
2811 err = -EINVAL;
2812 goto out_unlock;
2813 }
2814
2815 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
2816
2817 if (err) {
2818 dev_err(hba->dev,
2819 "%s: Sending flag query for idn %d failed, err = %d\n",
2820 __func__, idn, err);
2821 goto out_unlock;
2822 }
2823
2824 if (flag_res)
2825 *flag_res = (be32_to_cpu(response->upiu_res.value) &
2826 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2827
2828out_unlock:
2829 mutex_unlock(&hba->dev_cmd.lock);
2830 ufshcd_release(hba);
2831 return err;
2832}
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2846 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2847{
2848 struct ufs_query_req *request = NULL;
2849 struct ufs_query_res *response = NULL;
2850 int err;
2851
2852 BUG_ON(!hba);
2853
2854 ufshcd_hold(hba, false);
2855 if (!attr_val) {
2856 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2857 __func__, opcode);
2858 err = -EINVAL;
2859 goto out;
2860 }
2861
2862 mutex_lock(&hba->dev_cmd.lock);
2863 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2864 selector);
2865
2866 switch (opcode) {
2867 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2868 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2869 request->upiu_req.value = cpu_to_be32(*attr_val);
2870 break;
2871 case UPIU_QUERY_OPCODE_READ_ATTR:
2872 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2873 break;
2874 default:
2875 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2876 __func__, opcode);
2877 err = -EINVAL;
2878 goto out_unlock;
2879 }
2880
2881 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2882
2883 if (err) {
2884 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2885 __func__, opcode, idn, index, err);
2886 goto out_unlock;
2887 }
2888
2889 *attr_val = be32_to_cpu(response->upiu_res.value);
2890
2891out_unlock:
2892 mutex_unlock(&hba->dev_cmd.lock);
2893out:
2894 ufshcd_release(hba);
2895 return err;
2896}
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2912 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2913 u32 *attr_val)
2914{
2915 int ret = 0;
2916 u32 retries;
2917
2918 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2919 ret = ufshcd_query_attr(hba, opcode, idn, index,
2920 selector, attr_val);
2921 if (ret)
2922 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2923 __func__, ret, retries);
2924 else
2925 break;
2926 }
2927
2928 if (ret)
2929 dev_err(hba->dev,
2930 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2931 __func__, idn, ret, QUERY_REQ_RETRIES);
2932 return ret;
2933}
2934
2935static int __ufshcd_query_descriptor(struct ufs_hba *hba,
2936 enum query_opcode opcode, enum desc_idn idn, u8 index,
2937 u8 selector, u8 *desc_buf, int *buf_len)
2938{
2939 struct ufs_query_req *request = NULL;
2940 struct ufs_query_res *response = NULL;
2941 int err;
2942
2943 BUG_ON(!hba);
2944
2945 ufshcd_hold(hba, false);
2946 if (!desc_buf) {
2947 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2948 __func__, opcode);
2949 err = -EINVAL;
2950 goto out;
2951 }
2952
2953 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
2954 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2955 __func__, *buf_len);
2956 err = -EINVAL;
2957 goto out;
2958 }
2959
2960 mutex_lock(&hba->dev_cmd.lock);
2961 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2962 selector);
2963 hba->dev_cmd.query.descriptor = desc_buf;
2964 request->upiu_req.length = cpu_to_be16(*buf_len);
2965
2966 switch (opcode) {
2967 case UPIU_QUERY_OPCODE_WRITE_DESC:
2968 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2969 break;
2970 case UPIU_QUERY_OPCODE_READ_DESC:
2971 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2972 break;
2973 default:
2974 dev_err(hba->dev,
2975 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2976 __func__, opcode);
2977 err = -EINVAL;
2978 goto out_unlock;
2979 }
2980
2981 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2982
2983 if (err) {
2984 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2985 __func__, opcode, idn, index, err);
2986 goto out_unlock;
2987 }
2988
2989 hba->dev_cmd.query.descriptor = NULL;
2990 *buf_len = be16_to_cpu(response->upiu_res.length);
2991
2992out_unlock:
2993 mutex_unlock(&hba->dev_cmd.lock);
2994out:
2995 ufshcd_release(hba);
2996 return err;
2997}
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3014 enum query_opcode opcode,
3015 enum desc_idn idn, u8 index,
3016 u8 selector,
3017 u8 *desc_buf, int *buf_len)
3018{
3019 int err;
3020 int retries;
3021
3022 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3023 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3024 selector, desc_buf, buf_len);
3025 if (!err || err == -EINVAL)
3026 break;
3027 }
3028
3029 return err;
3030}
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041static int ufshcd_read_desc_length(struct ufs_hba *hba,
3042 enum desc_idn desc_id,
3043 int desc_index,
3044 int *desc_length)
3045{
3046 int ret;
3047 u8 header[QUERY_DESC_HDR_SIZE];
3048 int header_len = QUERY_DESC_HDR_SIZE;
3049
3050 if (desc_id >= QUERY_DESC_IDN_MAX)
3051 return -EINVAL;
3052
3053 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3054 desc_id, desc_index, 0, header,
3055 &header_len);
3056
3057 if (ret) {
3058 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3059 __func__, desc_id);
3060 return ret;
3061 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3062 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3063 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3064 desc_id);
3065 ret = -EINVAL;
3066 }
3067
3068 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3069 return ret;
3070
3071}
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3082 enum desc_idn desc_id, int *desc_len)
3083{
3084 switch (desc_id) {
3085 case QUERY_DESC_IDN_DEVICE:
3086 *desc_len = hba->desc_size.dev_desc;
3087 break;
3088 case QUERY_DESC_IDN_POWER:
3089 *desc_len = hba->desc_size.pwr_desc;
3090 break;
3091 case QUERY_DESC_IDN_GEOMETRY:
3092 *desc_len = hba->desc_size.geom_desc;
3093 break;
3094 case QUERY_DESC_IDN_CONFIGURATION:
3095 *desc_len = hba->desc_size.conf_desc;
3096 break;
3097 case QUERY_DESC_IDN_UNIT:
3098 *desc_len = hba->desc_size.unit_desc;
3099 break;
3100 case QUERY_DESC_IDN_INTERCONNECT:
3101 *desc_len = hba->desc_size.interc_desc;
3102 break;
3103 case QUERY_DESC_IDN_STRING:
3104 *desc_len = QUERY_DESC_MAX_SIZE;
3105 break;
3106 case QUERY_DESC_IDN_HEALTH:
3107 *desc_len = hba->desc_size.hlth_desc;
3108 break;
3109 case QUERY_DESC_IDN_RFU_0:
3110 case QUERY_DESC_IDN_RFU_1:
3111 *desc_len = 0;
3112 break;
3113 default:
3114 *desc_len = 0;
3115 return -EINVAL;
3116 }
3117 return 0;
3118}
3119EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132int ufshcd_read_desc_param(struct ufs_hba *hba,
3133 enum desc_idn desc_id,
3134 int desc_index,
3135 u8 param_offset,
3136 u8 *param_read_buf,
3137 u8 param_size)
3138{
3139 int ret;
3140 u8 *desc_buf;
3141 int buff_len;
3142 bool is_kmalloc = true;
3143
3144
3145 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3146 return -EINVAL;
3147
3148
3149
3150
3151 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3152
3153
3154 if (ret || !buff_len) {
3155 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3156 __func__);
3157 return ret;
3158 }
3159
3160
3161 if (param_offset != 0 || param_size < buff_len) {
3162 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3163 if (!desc_buf)
3164 return -ENOMEM;
3165 } else {
3166 desc_buf = param_read_buf;
3167 is_kmalloc = false;
3168 }
3169
3170
3171 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3172 desc_id, desc_index, 0,
3173 desc_buf, &buff_len);
3174
3175 if (ret) {
3176 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3177 __func__, desc_id, desc_index, param_offset, ret);
3178 goto out;
3179 }
3180
3181
3182 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3183 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3184 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3185 ret = -EINVAL;
3186 goto out;
3187 }
3188
3189
3190 if (is_kmalloc && param_size > buff_len)
3191 param_size = buff_len;
3192
3193 if (is_kmalloc)
3194 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3195out:
3196 if (is_kmalloc)
3197 kfree(desc_buf);
3198 return ret;
3199}
3200
3201static inline int ufshcd_read_desc(struct ufs_hba *hba,
3202 enum desc_idn desc_id,
3203 int desc_index,
3204 void *buf,
3205 u32 size)
3206{
3207 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3208}
3209
3210static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3211 u8 *buf,
3212 u32 size)
3213{
3214 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
3215}
3216
3217static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
3218{
3219 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3220}
3221
3222
3223
3224
3225
3226
3227
3228
3229struct uc_string_id {
3230 u8 len;
3231 u8 type;
3232 wchar_t uc[0];
3233} __packed;
3234
3235
3236static inline char ufshcd_remove_non_printable(u8 ch)
3237{
3238 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3239}
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3256 u8 **buf, bool ascii)
3257{
3258 struct uc_string_id *uc_str;
3259 u8 *str;
3260 int ret;
3261
3262 if (!buf)
3263 return -EINVAL;
3264
3265 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3266 if (!uc_str)
3267 return -ENOMEM;
3268
3269 ret = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING,
3270 desc_index, uc_str,
3271 QUERY_DESC_MAX_SIZE);
3272 if (ret < 0) {
3273 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3274 QUERY_REQ_RETRIES, ret);
3275 str = NULL;
3276 goto out;
3277 }
3278
3279 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3280 dev_dbg(hba->dev, "String Desc is of zero length\n");
3281 str = NULL;
3282 ret = 0;
3283 goto out;
3284 }
3285
3286 if (ascii) {
3287 ssize_t ascii_len;
3288 int i;
3289
3290 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3291 str = kzalloc(ascii_len, GFP_KERNEL);
3292 if (!str) {
3293 ret = -ENOMEM;
3294 goto out;
3295 }
3296
3297
3298
3299
3300
3301 ret = utf16s_to_utf8s(uc_str->uc,
3302 uc_str->len - QUERY_DESC_HDR_SIZE,
3303 UTF16_BIG_ENDIAN, str, ascii_len);
3304
3305
3306 for (i = 0; i < ret; i++)
3307 str[i] = ufshcd_remove_non_printable(str[i]);
3308
3309 str[ret++] = '\0';
3310
3311 } else {
3312 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3313 if (!str) {
3314 ret = -ENOMEM;
3315 goto out;
3316 }
3317 ret = uc_str->len;
3318 }
3319out:
3320 *buf = str;
3321 kfree(uc_str);
3322 return ret;
3323}
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3336 int lun,
3337 enum unit_desc_param param_offset,
3338 u8 *param_read_buf,
3339 u32 param_size)
3340{
3341
3342
3343
3344
3345 if (!ufs_is_valid_unit_desc_lun(lun))
3346 return -EOPNOTSUPP;
3347
3348 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3349 param_offset, param_read_buf, param_size);
3350}
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365static int ufshcd_memory_alloc(struct ufs_hba *hba)
3366{
3367 size_t utmrdl_size, utrdl_size, ucdl_size;
3368
3369
3370 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3371 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3372 ucdl_size,
3373 &hba->ucdl_dma_addr,
3374 GFP_KERNEL);
3375
3376
3377
3378
3379
3380
3381
3382 if (!hba->ucdl_base_addr ||
3383 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3384 dev_err(hba->dev,
3385 "Command Descriptor Memory allocation failed\n");
3386 goto out;
3387 }
3388
3389
3390
3391
3392
3393 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3394 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3395 utrdl_size,
3396 &hba->utrdl_dma_addr,
3397 GFP_KERNEL);
3398 if (!hba->utrdl_base_addr ||
3399 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3400 dev_err(hba->dev,
3401 "Transfer Descriptor Memory allocation failed\n");
3402 goto out;
3403 }
3404
3405
3406
3407
3408
3409 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3410 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3411 utmrdl_size,
3412 &hba->utmrdl_dma_addr,
3413 GFP_KERNEL);
3414 if (!hba->utmrdl_base_addr ||
3415 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3416 dev_err(hba->dev,
3417 "Task Management Descriptor Memory allocation failed\n");
3418 goto out;
3419 }
3420
3421
3422 hba->lrb = devm_kcalloc(hba->dev,
3423 hba->nutrs, sizeof(struct ufshcd_lrb),
3424 GFP_KERNEL);
3425 if (!hba->lrb) {
3426 dev_err(hba->dev, "LRB Memory allocation failed\n");
3427 goto out;
3428 }
3429 return 0;
3430out:
3431 return -ENOMEM;
3432}
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3448{
3449 struct utp_transfer_cmd_desc *cmd_descp;
3450 struct utp_transfer_req_desc *utrdlp;
3451 dma_addr_t cmd_desc_dma_addr;
3452 dma_addr_t cmd_desc_element_addr;
3453 u16 response_offset;
3454 u16 prdt_offset;
3455 int cmd_desc_size;
3456 int i;
3457
3458 utrdlp = hba->utrdl_base_addr;
3459 cmd_descp = hba->ucdl_base_addr;
3460
3461 response_offset =
3462 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3463 prdt_offset =
3464 offsetof(struct utp_transfer_cmd_desc, prd_table);
3465
3466 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3467 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3468
3469 for (i = 0; i < hba->nutrs; i++) {
3470
3471 cmd_desc_element_addr =
3472 (cmd_desc_dma_addr + (cmd_desc_size * i));
3473 utrdlp[i].command_desc_base_addr_lo =
3474 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3475 utrdlp[i].command_desc_base_addr_hi =
3476 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3477
3478
3479 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3480 utrdlp[i].response_upiu_offset =
3481 cpu_to_le16(response_offset);
3482 utrdlp[i].prd_table_offset =
3483 cpu_to_le16(prdt_offset);
3484 utrdlp[i].response_upiu_length =
3485 cpu_to_le16(ALIGNED_UPIU_SIZE);
3486 } else {
3487 utrdlp[i].response_upiu_offset =
3488 cpu_to_le16((response_offset >> 2));
3489 utrdlp[i].prd_table_offset =
3490 cpu_to_le16((prdt_offset >> 2));
3491 utrdlp[i].response_upiu_length =
3492 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3493 }
3494
3495 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
3496 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3497 (i * sizeof(struct utp_transfer_req_desc));
3498 hba->lrb[i].ucd_req_ptr =
3499 (struct utp_upiu_req *)(cmd_descp + i);
3500 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
3501 hba->lrb[i].ucd_rsp_ptr =
3502 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
3503 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3504 response_offset;
3505 hba->lrb[i].ucd_prdt_ptr =
3506 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
3507 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3508 prdt_offset;
3509 }
3510}
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3524{
3525 struct uic_command uic_cmd = {0};
3526 int ret;
3527
3528 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3529
3530 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3531 if (ret)
3532 dev_dbg(hba->dev,
3533 "dme-link-startup: error code %d\n", ret);
3534 return ret;
3535}
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545static int ufshcd_dme_reset(struct ufs_hba *hba)
3546{
3547 struct uic_command uic_cmd = {0};
3548 int ret;
3549
3550 uic_cmd.command = UIC_CMD_DME_RESET;
3551
3552 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3553 if (ret)
3554 dev_err(hba->dev,
3555 "dme-reset: error code %d\n", ret);
3556
3557 return ret;
3558}
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568static int ufshcd_dme_enable(struct ufs_hba *hba)
3569{
3570 struct uic_command uic_cmd = {0};
3571 int ret;
3572
3573 uic_cmd.command = UIC_CMD_DME_ENABLE;
3574
3575 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3576 if (ret)
3577 dev_err(hba->dev,
3578 "dme-reset: error code %d\n", ret);
3579
3580 return ret;
3581}
3582
3583static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3584{
3585 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3586 unsigned long min_sleep_time_us;
3587
3588 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3589 return;
3590
3591
3592
3593
3594
3595 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3596 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3597 } else {
3598 unsigned long delta =
3599 (unsigned long) ktime_to_us(
3600 ktime_sub(ktime_get(),
3601 hba->last_dme_cmd_tstamp));
3602
3603 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3604 min_sleep_time_us =
3605 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3606 else
3607 return;
3608 }
3609
3610
3611 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3612}
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3625 u8 attr_set, u32 mib_val, u8 peer)
3626{
3627 struct uic_command uic_cmd = {0};
3628 static const char *const action[] = {
3629 "dme-set",
3630 "dme-peer-set"
3631 };
3632 const char *set = action[!!peer];
3633 int ret;
3634 int retries = UFS_UIC_COMMAND_RETRIES;
3635
3636 uic_cmd.command = peer ?
3637 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3638 uic_cmd.argument1 = attr_sel;
3639 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3640 uic_cmd.argument3 = mib_val;
3641
3642 do {
3643
3644 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3645 if (ret)
3646 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3647 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3648 } while (ret && peer && --retries);
3649
3650 if (ret)
3651 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3652 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3653 UFS_UIC_COMMAND_RETRIES - retries);
3654
3655 return ret;
3656}
3657EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3669 u32 *mib_val, u8 peer)
3670{
3671 struct uic_command uic_cmd = {0};
3672 static const char *const action[] = {
3673 "dme-get",
3674 "dme-peer-get"
3675 };
3676 const char *get = action[!!peer];
3677 int ret;
3678 int retries = UFS_UIC_COMMAND_RETRIES;
3679 struct ufs_pa_layer_attr orig_pwr_info;
3680 struct ufs_pa_layer_attr temp_pwr_info;
3681 bool pwr_mode_change = false;
3682
3683 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3684 orig_pwr_info = hba->pwr_info;
3685 temp_pwr_info = orig_pwr_info;
3686
3687 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3688 orig_pwr_info.pwr_rx == FAST_MODE) {
3689 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3690 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3691 pwr_mode_change = true;
3692 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3693 orig_pwr_info.pwr_rx == SLOW_MODE) {
3694 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3695 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3696 pwr_mode_change = true;
3697 }
3698 if (pwr_mode_change) {
3699 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3700 if (ret)
3701 goto out;
3702 }
3703 }
3704
3705 uic_cmd.command = peer ?
3706 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3707 uic_cmd.argument1 = attr_sel;
3708
3709 do {
3710
3711 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3712 if (ret)
3713 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3714 get, UIC_GET_ATTR_ID(attr_sel), ret);
3715 } while (ret && peer && --retries);
3716
3717 if (ret)
3718 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3719 get, UIC_GET_ATTR_ID(attr_sel),
3720 UFS_UIC_COMMAND_RETRIES - retries);
3721
3722 if (mib_val && !ret)
3723 *mib_val = uic_cmd.argument3;
3724
3725 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3726 && pwr_mode_change)
3727 ufshcd_change_power_mode(hba, &orig_pwr_info);
3728out:
3729 return ret;
3730}
3731EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3750{
3751 struct completion uic_async_done;
3752 unsigned long flags;
3753 u8 status;
3754 int ret;
3755 bool reenable_intr = false;
3756
3757 mutex_lock(&hba->uic_cmd_mutex);
3758 init_completion(&uic_async_done);
3759 ufshcd_add_delay_before_dme_cmd(hba);
3760
3761 spin_lock_irqsave(hba->host->host_lock, flags);
3762 hba->uic_async_done = &uic_async_done;
3763 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3764 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3765
3766
3767
3768
3769 wmb();
3770 reenable_intr = true;
3771 }
3772 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3773 spin_unlock_irqrestore(hba->host->host_lock, flags);
3774 if (ret) {
3775 dev_err(hba->dev,
3776 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3777 cmd->command, cmd->argument3, ret);
3778 goto out;
3779 }
3780
3781 if (!wait_for_completion_timeout(hba->uic_async_done,
3782 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3783 dev_err(hba->dev,
3784 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3785 cmd->command, cmd->argument3);
3786 ret = -ETIMEDOUT;
3787 goto out;
3788 }
3789
3790 status = ufshcd_get_upmcrs(hba);
3791 if (status != PWR_LOCAL) {
3792 dev_err(hba->dev,
3793 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
3794 cmd->command, status);
3795 ret = (status != PWR_OK) ? status : -1;
3796 }
3797out:
3798 if (ret) {
3799 ufshcd_print_host_state(hba);
3800 ufshcd_print_pwr_info(hba);
3801 ufshcd_print_host_regs(hba);
3802 }
3803
3804 spin_lock_irqsave(hba->host->host_lock, flags);
3805 hba->active_uic_cmd = NULL;
3806 hba->uic_async_done = NULL;
3807 if (reenable_intr)
3808 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
3809 spin_unlock_irqrestore(hba->host->host_lock, flags);
3810 mutex_unlock(&hba->uic_cmd_mutex);
3811
3812 return ret;
3813}
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3824{
3825 struct uic_command uic_cmd = {0};
3826 int ret;
3827
3828 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3829 ret = ufshcd_dme_set(hba,
3830 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3831 if (ret) {
3832 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3833 __func__, ret);
3834 goto out;
3835 }
3836 }
3837
3838 uic_cmd.command = UIC_CMD_DME_SET;
3839 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3840 uic_cmd.argument3 = mode;
3841 ufshcd_hold(hba, false);
3842 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3843 ufshcd_release(hba);
3844
3845out:
3846 return ret;
3847}
3848
3849static int ufshcd_link_recovery(struct ufs_hba *hba)
3850{
3851 int ret;
3852 unsigned long flags;
3853
3854 spin_lock_irqsave(hba->host->host_lock, flags);
3855 hba->ufshcd_state = UFSHCD_STATE_RESET;
3856 ufshcd_set_eh_in_progress(hba);
3857 spin_unlock_irqrestore(hba->host->host_lock, flags);
3858
3859 ret = ufshcd_host_reset_and_restore(hba);
3860
3861 spin_lock_irqsave(hba->host->host_lock, flags);
3862 if (ret)
3863 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3864 ufshcd_clear_eh_in_progress(hba);
3865 spin_unlock_irqrestore(hba->host->host_lock, flags);
3866
3867 if (ret)
3868 dev_err(hba->dev, "%s: link recovery failed, err %d",
3869 __func__, ret);
3870
3871 return ret;
3872}
3873
3874static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3875{
3876 int ret;
3877 struct uic_command uic_cmd = {0};
3878 ktime_t start = ktime_get();
3879
3880 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3881
3882 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
3883 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3884 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3885 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3886
3887 if (ret) {
3888 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3889 __func__, ret);
3890
3891
3892
3893
3894
3895 if (ufshcd_link_recovery(hba))
3896 ret = -ENOLINK;
3897 } else
3898 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3899 POST_CHANGE);
3900
3901 return ret;
3902}
3903
3904static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3905{
3906 int ret = 0, retries;
3907
3908 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3909 ret = __ufshcd_uic_hibern8_enter(hba);
3910 if (!ret || ret == -ENOLINK)
3911 goto out;
3912 }
3913out:
3914 return ret;
3915}
3916
3917static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3918{
3919 struct uic_command uic_cmd = {0};
3920 int ret;
3921 ktime_t start = ktime_get();
3922
3923 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3924
3925 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3926 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3927 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3928 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3929
3930 if (ret) {
3931 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3932 __func__, ret);
3933 ret = ufshcd_link_recovery(hba);
3934 } else {
3935 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3936 POST_CHANGE);
3937 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3938 hba->ufs_stats.hibern8_exit_cnt++;
3939 }
3940
3941 return ret;
3942}
3943
3944static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
3945{
3946 unsigned long flags;
3947
3948 if (!ufshcd_is_auto_hibern8_supported(hba) || !hba->ahit)
3949 return;
3950
3951 spin_lock_irqsave(hba->host->host_lock, flags);
3952 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3953 spin_unlock_irqrestore(hba->host->host_lock, flags);
3954}
3955
3956
3957
3958
3959
3960
3961static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3962{
3963 hba->pwr_info.gear_rx = UFS_PWM_G1;
3964 hba->pwr_info.gear_tx = UFS_PWM_G1;
3965 hba->pwr_info.lane_rx = 1;
3966 hba->pwr_info.lane_tx = 1;
3967 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3968 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3969 hba->pwr_info.hs_rate = 0;
3970}
3971
3972
3973
3974
3975
3976static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
3977{
3978 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3979
3980 if (hba->max_pwr_info.is_valid)
3981 return 0;
3982
3983 pwr_info->pwr_tx = FAST_MODE;
3984 pwr_info->pwr_rx = FAST_MODE;
3985 pwr_info->hs_rate = PA_HS_MODE_B;
3986
3987
3988 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3989 &pwr_info->lane_rx);
3990 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3991 &pwr_info->lane_tx);
3992
3993 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3994 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3995 __func__,
3996 pwr_info->lane_rx,
3997 pwr_info->lane_tx);
3998 return -EINVAL;
3999 }
4000
4001
4002
4003
4004
4005
4006 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4007 if (!pwr_info->gear_rx) {
4008 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4009 &pwr_info->gear_rx);
4010 if (!pwr_info->gear_rx) {
4011 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4012 __func__, pwr_info->gear_rx);
4013 return -EINVAL;
4014 }
4015 pwr_info->pwr_rx = SLOW_MODE;
4016 }
4017
4018 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4019 &pwr_info->gear_tx);
4020 if (!pwr_info->gear_tx) {
4021 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4022 &pwr_info->gear_tx);
4023 if (!pwr_info->gear_tx) {
4024 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4025 __func__, pwr_info->gear_tx);
4026 return -EINVAL;
4027 }
4028 pwr_info->pwr_tx = SLOW_MODE;
4029 }
4030
4031 hba->max_pwr_info.is_valid = true;
4032 return 0;
4033}
4034
4035static int ufshcd_change_power_mode(struct ufs_hba *hba,
4036 struct ufs_pa_layer_attr *pwr_mode)
4037{
4038 int ret;
4039
4040
4041 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4042 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4043 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4044 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4045 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4046 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4047 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4048 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4049 return 0;
4050 }
4051
4052
4053
4054
4055
4056
4057
4058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4059 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4060 pwr_mode->lane_rx);
4061 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4062 pwr_mode->pwr_rx == FAST_MODE)
4063 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4064 else
4065 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4066
4067 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4068 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4069 pwr_mode->lane_tx);
4070 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4071 pwr_mode->pwr_tx == FAST_MODE)
4072 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4073 else
4074 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4075
4076 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4077 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4078 pwr_mode->pwr_rx == FAST_MODE ||
4079 pwr_mode->pwr_tx == FAST_MODE)
4080 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4081 pwr_mode->hs_rate);
4082
4083 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4084 | pwr_mode->pwr_tx);
4085
4086 if (ret) {
4087 dev_err(hba->dev,
4088 "%s: power mode change failed %d\n", __func__, ret);
4089 } else {
4090 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4091 pwr_mode);
4092
4093 memcpy(&hba->pwr_info, pwr_mode,
4094 sizeof(struct ufs_pa_layer_attr));
4095 }
4096
4097 return ret;
4098}
4099
4100
4101
4102
4103
4104
4105int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4106 struct ufs_pa_layer_attr *desired_pwr_mode)
4107{
4108 struct ufs_pa_layer_attr final_params = { 0 };
4109 int ret;
4110
4111 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4112 desired_pwr_mode, &final_params);
4113
4114 if (ret)
4115 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4116
4117 ret = ufshcd_change_power_mode(hba, &final_params);
4118 if (!ret)
4119 ufshcd_print_pwr_info(hba);
4120
4121 return ret;
4122}
4123EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4124
4125
4126
4127
4128
4129
4130
4131static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4132{
4133 int i;
4134 int err;
4135 bool flag_res = 1;
4136
4137 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4138 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
4139 if (err) {
4140 dev_err(hba->dev,
4141 "%s setting fDeviceInit flag failed with error %d\n",
4142 __func__, err);
4143 goto out;
4144 }
4145
4146
4147 for (i = 0; i < 1000 && !err && flag_res; i++)
4148 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4149 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4150
4151 if (err)
4152 dev_err(hba->dev,
4153 "%s reading fDeviceInit flag failed with error %d\n",
4154 __func__, err);
4155 else if (flag_res)
4156 dev_err(hba->dev,
4157 "%s fDeviceInit was not cleared by the device\n",
4158 __func__);
4159
4160out:
4161 return err;
4162}
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4177{
4178 int err = 0;
4179 u32 reg;
4180
4181
4182 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4183
4184
4185 if (ufshcd_is_intr_aggr_allowed(hba))
4186 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4187 else
4188 ufshcd_disable_intr_aggr(hba);
4189
4190
4191 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4192 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4193 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4194 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4195 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4196 REG_UTP_TASK_REQ_LIST_BASE_L);
4197 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4198 REG_UTP_TASK_REQ_LIST_BASE_H);
4199
4200
4201
4202
4203
4204 wmb();
4205
4206
4207
4208
4209 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4210 if (!(ufshcd_get_lists_status(reg))) {
4211 ufshcd_enable_run_stop_reg(hba);
4212 } else {
4213 dev_err(hba->dev,
4214 "Host controller not ready to process requests");
4215 err = -EIO;
4216 goto out;
4217 }
4218
4219out:
4220 return err;
4221}
4222
4223
4224
4225
4226
4227
4228static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4229{
4230 int err;
4231
4232 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4233 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4234 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4235 10, 1, can_sleep);
4236 if (err)
4237 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4238}
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4251{
4252 int retry;
4253
4254 if (!ufshcd_is_hba_active(hba))
4255
4256 ufshcd_hba_stop(hba, true);
4257
4258
4259 ufshcd_set_link_off(hba);
4260
4261 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4262
4263
4264 ufshcd_hba_start(hba);
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276 usleep_range(1000, 1100);
4277
4278
4279 retry = 10;
4280 while (ufshcd_is_hba_active(hba)) {
4281 if (retry) {
4282 retry--;
4283 } else {
4284 dev_err(hba->dev,
4285 "Controller enable failed\n");
4286 return -EIO;
4287 }
4288 usleep_range(5000, 5100);
4289 }
4290
4291
4292 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4293
4294 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4295
4296 return 0;
4297}
4298
4299static int ufshcd_hba_enable(struct ufs_hba *hba)
4300{
4301 int ret;
4302
4303 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4304 ufshcd_set_link_off(hba);
4305 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4306
4307
4308 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4309 ret = ufshcd_dme_reset(hba);
4310 if (!ret) {
4311 ret = ufshcd_dme_enable(hba);
4312 if (!ret)
4313 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4314 if (ret)
4315 dev_err(hba->dev,
4316 "Host controller enable failed with non-hce\n");
4317 }
4318 } else {
4319 ret = ufshcd_hba_execute_hce(hba);
4320 }
4321
4322 return ret;
4323}
4324static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4325{
4326 int tx_lanes, i, err = 0;
4327
4328 if (!peer)
4329 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4330 &tx_lanes);
4331 else
4332 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4333 &tx_lanes);
4334 for (i = 0; i < tx_lanes; i++) {
4335 if (!peer)
4336 err = ufshcd_dme_set(hba,
4337 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4338 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4339 0);
4340 else
4341 err = ufshcd_dme_peer_set(hba,
4342 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4343 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4344 0);
4345 if (err) {
4346 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4347 __func__, peer, i, err);
4348 break;
4349 }
4350 }
4351
4352 return err;
4353}
4354
4355static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4356{
4357 return ufshcd_disable_tx_lcc(hba, true);
4358}
4359
4360static void ufshcd_update_reg_hist(struct ufs_err_reg_hist *reg_hist,
4361 u32 reg)
4362{
4363 reg_hist->reg[reg_hist->pos] = reg;
4364 reg_hist->tstamp[reg_hist->pos] = ktime_get();
4365 reg_hist->pos = (reg_hist->pos + 1) % UFS_ERR_REG_HIST_LENGTH;
4366}
4367
4368
4369
4370
4371
4372
4373
4374static int ufshcd_link_startup(struct ufs_hba *hba)
4375{
4376 int ret;
4377 int retries = DME_LINKSTARTUP_RETRIES;
4378 bool link_startup_again = false;
4379
4380
4381
4382
4383
4384 if (!ufshcd_is_ufs_dev_active(hba))
4385 link_startup_again = true;
4386
4387link_startup:
4388 do {
4389 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4390
4391 ret = ufshcd_dme_link_startup(hba);
4392
4393
4394 if (!ret && !ufshcd_is_device_present(hba)) {
4395 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4396 0);
4397 dev_err(hba->dev, "%s: Device not present\n", __func__);
4398 ret = -ENXIO;
4399 goto out;
4400 }
4401
4402
4403
4404
4405
4406
4407 if (ret && ufshcd_hba_enable(hba)) {
4408 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4409 (u32)ret);
4410 goto out;
4411 }
4412 } while (ret && retries--);
4413
4414 if (ret) {
4415
4416 ufshcd_update_reg_hist(&hba->ufs_stats.link_startup_err,
4417 (u32)ret);
4418 goto out;
4419 }
4420
4421 if (link_startup_again) {
4422 link_startup_again = false;
4423 retries = DME_LINKSTARTUP_RETRIES;
4424 goto link_startup;
4425 }
4426
4427
4428 ufshcd_init_pwr_info(hba);
4429 ufshcd_print_pwr_info(hba);
4430
4431 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4432 ret = ufshcd_disable_device_tx_lcc(hba);
4433 if (ret)
4434 goto out;
4435 }
4436
4437
4438 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4439 if (ret)
4440 goto out;
4441
4442 ret = ufshcd_make_hba_operational(hba);
4443out:
4444 if (ret) {
4445 dev_err(hba->dev, "link startup failed %d\n", ret);
4446 ufshcd_print_host_state(hba);
4447 ufshcd_print_pwr_info(hba);
4448 ufshcd_print_host_regs(hba);
4449 }
4450 return ret;
4451}
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4464{
4465 int err = 0;
4466 int retries;
4467
4468 ufshcd_hold(hba, false);
4469 mutex_lock(&hba->dev_cmd.lock);
4470 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4471 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4472 NOP_OUT_TIMEOUT);
4473
4474 if (!err || err == -ETIMEDOUT)
4475 break;
4476
4477 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4478 }
4479 mutex_unlock(&hba->dev_cmd.lock);
4480 ufshcd_release(hba);
4481
4482 if (err)
4483 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4484 return err;
4485}
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4497{
4498 int ret = 0;
4499 u8 lun_qdepth;
4500 struct ufs_hba *hba;
4501
4502 hba = shost_priv(sdev->host);
4503
4504 lun_qdepth = hba->nutrs;
4505 ret = ufshcd_read_unit_desc_param(hba,
4506 ufshcd_scsi_to_upiu_lun(sdev->lun),
4507 UNIT_DESC_PARAM_LU_Q_DEPTH,
4508 &lun_qdepth,
4509 sizeof(lun_qdepth));
4510
4511
4512 if (ret == -EOPNOTSUPP)
4513 lun_qdepth = 1;
4514 else if (!lun_qdepth)
4515
4516 lun_qdepth = hba->nutrs;
4517 else
4518 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4519
4520 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4521 __func__, lun_qdepth);
4522 scsi_change_queue_depth(sdev, lun_qdepth);
4523}
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4537 u8 lun,
4538 u8 *b_lu_write_protect)
4539{
4540 int ret;
4541
4542 if (!b_lu_write_protect)
4543 ret = -EINVAL;
4544
4545
4546
4547
4548
4549 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4550 ret = -ENOTSUPP;
4551 else
4552 ret = ufshcd_read_unit_desc_param(hba,
4553 lun,
4554 UNIT_DESC_PARAM_LU_WR_PROTECT,
4555 b_lu_write_protect,
4556 sizeof(*b_lu_write_protect));
4557 return ret;
4558}
4559
4560
4561
4562
4563
4564
4565
4566
4567static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4568 struct scsi_device *sdev)
4569{
4570 if (hba->dev_info.f_power_on_wp_en &&
4571 !hba->dev_info.is_lu_power_on_wp) {
4572 u8 b_lu_write_protect;
4573
4574 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4575 &b_lu_write_protect) &&
4576 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4577 hba->dev_info.is_lu_power_on_wp = true;
4578 }
4579}
4580
4581
4582
4583
4584
4585
4586
4587static int ufshcd_slave_alloc(struct scsi_device *sdev)
4588{
4589 struct ufs_hba *hba;
4590
4591 hba = shost_priv(sdev->host);
4592
4593
4594 sdev->use_10_for_ms = 1;
4595
4596
4597 sdev->allow_restart = 1;
4598
4599
4600 sdev->no_report_opcodes = 1;
4601
4602
4603 sdev->no_write_same = 1;
4604
4605 ufshcd_set_queue_depth(sdev);
4606
4607 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4608
4609 return 0;
4610}
4611
4612
4613
4614
4615
4616
4617
4618
4619static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4620{
4621 struct ufs_hba *hba = shost_priv(sdev->host);
4622
4623 if (depth > hba->nutrs)
4624 depth = hba->nutrs;
4625 return scsi_change_queue_depth(sdev, depth);
4626}
4627
4628
4629
4630
4631
4632static int ufshcd_slave_configure(struct scsi_device *sdev)
4633{
4634 struct request_queue *q = sdev->request_queue;
4635
4636 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4637 return 0;
4638}
4639
4640
4641
4642
4643
4644static void ufshcd_slave_destroy(struct scsi_device *sdev)
4645{
4646 struct ufs_hba *hba;
4647
4648 hba = shost_priv(sdev->host);
4649
4650 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4651 unsigned long flags;
4652
4653 spin_lock_irqsave(hba->host->host_lock, flags);
4654 hba->sdev_ufs_device = NULL;
4655 spin_unlock_irqrestore(hba->host->host_lock, flags);
4656 }
4657}
4658
4659
4660
4661
4662
4663
4664
4665
4666static inline int
4667ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4668{
4669 int result = 0;
4670
4671 switch (scsi_status) {
4672 case SAM_STAT_CHECK_CONDITION:
4673 ufshcd_copy_sense_data(lrbp);
4674
4675 case SAM_STAT_GOOD:
4676 result |= DID_OK << 16 |
4677 COMMAND_COMPLETE << 8 |
4678 scsi_status;
4679 break;
4680 case SAM_STAT_TASK_SET_FULL:
4681 case SAM_STAT_BUSY:
4682 case SAM_STAT_TASK_ABORTED:
4683 ufshcd_copy_sense_data(lrbp);
4684 result |= scsi_status;
4685 break;
4686 default:
4687 result |= DID_ERROR << 16;
4688 break;
4689 }
4690
4691 return result;
4692}
4693
4694
4695
4696
4697
4698
4699
4700
4701static inline int
4702ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4703{
4704 int result = 0;
4705 int scsi_status;
4706 int ocs;
4707
4708
4709 ocs = ufshcd_get_tr_ocs(lrbp);
4710
4711 switch (ocs) {
4712 case OCS_SUCCESS:
4713 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
4714 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
4715 switch (result) {
4716 case UPIU_TRANSACTION_RESPONSE:
4717
4718
4719
4720
4721 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4722
4723
4724
4725
4726
4727 scsi_status = result & MASK_SCSI_STATUS;
4728 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742 if (!hba->pm_op_in_progress &&
4743 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
4744 schedule_work(&hba->eeh_work);
4745 break;
4746 case UPIU_TRANSACTION_REJECT_UPIU:
4747
4748 result = DID_ERROR << 16;
4749 dev_err(hba->dev,
4750 "Reject UPIU not fully implemented\n");
4751 break;
4752 default:
4753 dev_err(hba->dev,
4754 "Unexpected request response code = %x\n",
4755 result);
4756 result = DID_ERROR << 16;
4757 break;
4758 }
4759 break;
4760 case OCS_ABORTED:
4761 result |= DID_ABORT << 16;
4762 break;
4763 case OCS_INVALID_COMMAND_STATUS:
4764 result |= DID_REQUEUE << 16;
4765 break;
4766 case OCS_INVALID_CMD_TABLE_ATTR:
4767 case OCS_INVALID_PRDT_ATTR:
4768 case OCS_MISMATCH_DATA_BUF_SIZE:
4769 case OCS_MISMATCH_RESP_UPIU_SIZE:
4770 case OCS_PEER_COMM_FAILURE:
4771 case OCS_FATAL_ERROR:
4772 default:
4773 result |= DID_ERROR << 16;
4774 dev_err(hba->dev,
4775 "OCS error from controller = %x for tag %d\n",
4776 ocs, lrbp->task_tag);
4777 ufshcd_print_host_regs(hba);
4778 ufshcd_print_host_state(hba);
4779 break;
4780 }
4781
4782 if (host_byte(result) != DID_OK)
4783 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
4784 return result;
4785}
4786
4787
4788
4789
4790
4791
4792static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
4793{
4794 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
4795 hba->active_uic_cmd->argument2 |=
4796 ufshcd_get_uic_cmd_result(hba);
4797 hba->active_uic_cmd->argument3 =
4798 ufshcd_get_dme_attr_val(hba);
4799 complete(&hba->active_uic_cmd->done);
4800 }
4801
4802 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4803 complete(hba->uic_async_done);
4804}
4805
4806
4807
4808
4809
4810
4811static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4812 unsigned long completed_reqs)
4813{
4814 struct ufshcd_lrb *lrbp;
4815 struct scsi_cmnd *cmd;
4816 int result;
4817 int index;
4818
4819 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4820 lrbp = &hba->lrb[index];
4821 cmd = lrbp->cmd;
4822 if (cmd) {
4823 ufshcd_add_command_trace(hba, index, "complete");
4824 result = ufshcd_transfer_rsp_status(hba, lrbp);
4825 scsi_dma_unmap(cmd);
4826 cmd->result = result;
4827
4828 lrbp->cmd = NULL;
4829 clear_bit_unlock(index, &hba->lrb_in_use);
4830
4831 cmd->scsi_done(cmd);
4832 __ufshcd_release(hba);
4833 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4834 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
4835 if (hba->dev_cmd.complete) {
4836 ufshcd_add_command_trace(hba, index,
4837 "dev_complete");
4838 complete(hba->dev_cmd.complete);
4839 }
4840 }
4841 if (ufshcd_is_clkscaling_supported(hba))
4842 hba->clk_scaling.active_reqs--;
4843
4844 lrbp->compl_time_stamp = ktime_get();
4845 }
4846
4847
4848 hba->outstanding_reqs ^= completed_reqs;
4849
4850 ufshcd_clk_scaling_update_busy(hba);
4851
4852
4853 wake_up(&hba->dev_cmd.tag_wq);
4854}
4855
4856
4857
4858
4859
4860static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4861{
4862 unsigned long completed_reqs;
4863 u32 tr_doorbell;
4864
4865
4866
4867
4868
4869
4870
4871
4872 if (ufshcd_is_intr_aggr_allowed(hba) &&
4873 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
4874 ufshcd_reset_intr_aggr(hba);
4875
4876 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4877 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4878
4879 __ufshcd_transfer_req_compl(hba, completed_reqs);
4880}
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4893{
4894 int err = 0;
4895 u32 val;
4896
4897 if (!(hba->ee_ctrl_mask & mask))
4898 goto out;
4899
4900 val = hba->ee_ctrl_mask & ~mask;
4901 val &= MASK_EE_STATUS;
4902 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4903 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4904 if (!err)
4905 hba->ee_ctrl_mask &= ~mask;
4906out:
4907 return err;
4908}
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4921{
4922 int err = 0;
4923 u32 val;
4924
4925 if (hba->ee_ctrl_mask & mask)
4926 goto out;
4927
4928 val = hba->ee_ctrl_mask | mask;
4929 val &= MASK_EE_STATUS;
4930 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4931 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4932 if (!err)
4933 hba->ee_ctrl_mask |= mask;
4934out:
4935 return err;
4936}
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4950{
4951 int err = 0;
4952
4953 if (hba->auto_bkops_enabled)
4954 goto out;
4955
4956 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4957 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4958 if (err) {
4959 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4960 __func__, err);
4961 goto out;
4962 }
4963
4964 hba->auto_bkops_enabled = true;
4965 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
4966
4967
4968 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4969 if (err)
4970 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4971 __func__, err);
4972out:
4973 return err;
4974}
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4989{
4990 int err = 0;
4991
4992 if (!hba->auto_bkops_enabled)
4993 goto out;
4994
4995
4996
4997
4998
4999 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5000 if (err) {
5001 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5002 __func__, err);
5003 goto out;
5004 }
5005
5006 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5007 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5008 if (err) {
5009 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5010 __func__, err);
5011 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5012 goto out;
5013 }
5014
5015 hba->auto_bkops_enabled = false;
5016 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5017out:
5018 return err;
5019}
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5031{
5032 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5033 hba->auto_bkops_enabled = false;
5034 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5035 ufshcd_enable_auto_bkops(hba);
5036 } else {
5037 hba->auto_bkops_enabled = true;
5038 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5039 ufshcd_disable_auto_bkops(hba);
5040 }
5041}
5042
5043static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5044{
5045 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5046 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5047}
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062
5063
5064
5065static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5066 enum bkops_status status)
5067{
5068 int err;
5069 u32 curr_status = 0;
5070
5071 err = ufshcd_get_bkops_status(hba, &curr_status);
5072 if (err) {
5073 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5074 __func__, err);
5075 goto out;
5076 } else if (curr_status > BKOPS_STATUS_MAX) {
5077 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5078 __func__, curr_status);
5079 err = -EINVAL;
5080 goto out;
5081 }
5082
5083 if (curr_status >= status)
5084 err = ufshcd_enable_auto_bkops(hba);
5085 else
5086 err = ufshcd_disable_auto_bkops(hba);
5087out:
5088 return err;
5089}
5090
5091
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5102{
5103 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5104}
5105
5106static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5107{
5108 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5109 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5110}
5111
5112static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5113{
5114 int err;
5115 u32 curr_status = 0;
5116
5117 if (hba->is_urgent_bkops_lvl_checked)
5118 goto enable_auto_bkops;
5119
5120 err = ufshcd_get_bkops_status(hba, &curr_status);
5121 if (err) {
5122 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5123 __func__, err);
5124 goto out;
5125 }
5126
5127
5128
5129
5130
5131
5132
5133 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5134 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5135 __func__, curr_status);
5136
5137 hba->urgent_bkops_lvl = curr_status;
5138 hba->is_urgent_bkops_lvl_checked = true;
5139 }
5140
5141enable_auto_bkops:
5142 err = ufshcd_enable_auto_bkops(hba);
5143out:
5144 if (err < 0)
5145 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5146 __func__, err);
5147}
5148
5149
5150
5151
5152
5153
5154
5155
5156static void ufshcd_exception_event_handler(struct work_struct *work)
5157{
5158 struct ufs_hba *hba;
5159 int err;
5160 u32 status = 0;
5161 hba = container_of(work, struct ufs_hba, eeh_work);
5162
5163 pm_runtime_get_sync(hba->dev);
5164 scsi_block_requests(hba->host);
5165 err = ufshcd_get_ee_status(hba, &status);
5166 if (err) {
5167 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5168 __func__, err);
5169 goto out;
5170 }
5171
5172 status &= hba->ee_ctrl_mask;
5173
5174 if (status & MASK_EE_URGENT_BKOPS)
5175 ufshcd_bkops_exception_event_handler(hba);
5176
5177out:
5178 scsi_unblock_requests(hba->host);
5179 pm_runtime_put_sync(hba->dev);
5180 return;
5181}
5182
5183
5184static void ufshcd_complete_requests(struct ufs_hba *hba)
5185{
5186 ufshcd_transfer_req_compl(hba);
5187 ufshcd_tmc_handler(hba);
5188}
5189
5190
5191
5192
5193
5194
5195
5196
5197static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5198{
5199 unsigned long flags;
5200 bool err_handling = true;
5201
5202 spin_lock_irqsave(hba->host->host_lock, flags);
5203
5204
5205
5206
5207 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5208 goto out;
5209
5210 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5211 ((hba->saved_err & UIC_ERROR) &&
5212 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5213 goto out;
5214
5215 if ((hba->saved_err & UIC_ERROR) &&
5216 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5217 int err;
5218
5219
5220
5221 spin_unlock_irqrestore(hba->host->host_lock, flags);
5222 msleep(50);
5223 spin_lock_irqsave(hba->host->host_lock, flags);
5224
5225
5226
5227
5228
5229 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5230 ((hba->saved_err & UIC_ERROR) &&
5231 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5232 goto out;
5233
5234
5235
5236
5237
5238
5239
5240
5241 spin_unlock_irqrestore(hba->host->host_lock, flags);
5242 err = ufshcd_verify_dev_init(hba);
5243 spin_lock_irqsave(hba->host->host_lock, flags);
5244
5245 if (err)
5246 goto out;
5247
5248
5249 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5250 hba->saved_err &= ~UIC_ERROR;
5251
5252 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5253 if (!hba->saved_uic_err) {
5254 err_handling = false;
5255 goto out;
5256 }
5257 }
5258out:
5259 spin_unlock_irqrestore(hba->host->host_lock, flags);
5260 return err_handling;
5261}
5262
5263
5264
5265
5266
5267static void ufshcd_err_handler(struct work_struct *work)
5268{
5269 struct ufs_hba *hba;
5270 unsigned long flags;
5271 u32 err_xfer = 0;
5272 u32 err_tm = 0;
5273 int err = 0;
5274 int tag;
5275 bool needs_reset = false;
5276
5277 hba = container_of(work, struct ufs_hba, eh_work);
5278
5279 pm_runtime_get_sync(hba->dev);
5280 ufshcd_hold(hba, false);
5281
5282 spin_lock_irqsave(hba->host->host_lock, flags);
5283 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
5284 goto out;
5285
5286 hba->ufshcd_state = UFSHCD_STATE_RESET;
5287 ufshcd_set_eh_in_progress(hba);
5288
5289
5290 ufshcd_complete_requests(hba);
5291
5292 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5293 bool ret;
5294
5295 spin_unlock_irqrestore(hba->host->host_lock, flags);
5296
5297 ret = ufshcd_quirk_dl_nac_errors(hba);
5298 spin_lock_irqsave(hba->host->host_lock, flags);
5299 if (!ret)
5300 goto skip_err_handling;
5301 }
5302 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5303 (hba->saved_err & UFSHCD_UIC_HIBERN8_MASK) ||
5304 ((hba->saved_err & UIC_ERROR) &&
5305 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5306 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5307 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5308 needs_reset = true;
5309
5310
5311
5312
5313
5314
5315 if (needs_reset)
5316 goto skip_pending_xfer_clear;
5317
5318
5319 spin_unlock_irqrestore(hba->host->host_lock, flags);
5320
5321 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5322 if (ufshcd_clear_cmd(hba, tag)) {
5323 err_xfer = true;
5324 goto lock_skip_pending_xfer_clear;
5325 }
5326 }
5327
5328
5329 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5330 if (ufshcd_clear_tm_cmd(hba, tag)) {
5331 err_tm = true;
5332 goto lock_skip_pending_xfer_clear;
5333 }
5334 }
5335
5336lock_skip_pending_xfer_clear:
5337 spin_lock_irqsave(hba->host->host_lock, flags);
5338
5339
5340 ufshcd_complete_requests(hba);
5341
5342 if (err_xfer || err_tm)
5343 needs_reset = true;
5344
5345skip_pending_xfer_clear:
5346
5347 if (needs_reset) {
5348 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5349
5350
5351
5352
5353
5354
5355
5356
5357 if (hba->outstanding_reqs == max_doorbells)
5358 __ufshcd_transfer_req_compl(hba,
5359 (1UL << (hba->nutrs - 1)));
5360
5361 spin_unlock_irqrestore(hba->host->host_lock, flags);
5362 err = ufshcd_reset_and_restore(hba);
5363 spin_lock_irqsave(hba->host->host_lock, flags);
5364 if (err) {
5365 dev_err(hba->dev, "%s: reset and restore failed\n",
5366 __func__);
5367 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5368 }
5369
5370
5371
5372
5373 scsi_report_bus_reset(hba->host, 0);
5374 hba->saved_err = 0;
5375 hba->saved_uic_err = 0;
5376 }
5377
5378skip_err_handling:
5379 if (!needs_reset) {
5380 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5381 if (hba->saved_err || hba->saved_uic_err)
5382 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5383 __func__, hba->saved_err, hba->saved_uic_err);
5384 }
5385
5386 ufshcd_clear_eh_in_progress(hba);
5387
5388out:
5389 spin_unlock_irqrestore(hba->host->host_lock, flags);
5390 ufshcd_scsi_unblock_requests(hba);
5391 ufshcd_release(hba);
5392 pm_runtime_put_sync(hba->dev);
5393}
5394
5395
5396
5397
5398
5399static void ufshcd_update_uic_error(struct ufs_hba *hba)
5400{
5401 u32 reg;
5402
5403
5404 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5405
5406 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
5407 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
5408
5409
5410
5411
5412 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
5413 ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg);
5414 }
5415
5416
5417 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
5418 if (reg)
5419 ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg);
5420
5421 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5422 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5423 else if (hba->dev_quirks &
5424 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5425 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5426 hba->uic_error |=
5427 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5428 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5429 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5430 }
5431
5432
5433 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
5434 if (reg) {
5435 ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg);
5436 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
5437 }
5438
5439 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
5440 if (reg) {
5441 ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg);
5442 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
5443 }
5444
5445 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
5446 if (reg) {
5447 ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg);
5448 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
5449 }
5450
5451 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5452 __func__, hba->uic_error);
5453}
5454
5455static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5456 u32 intr_mask)
5457{
5458 if (!ufshcd_is_auto_hibern8_supported(hba))
5459 return false;
5460
5461 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5462 return false;
5463
5464 if (hba->active_uic_cmd &&
5465 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5466 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5467 return false;
5468
5469 return true;
5470}
5471
5472
5473
5474
5475
5476static void ufshcd_check_errors(struct ufs_hba *hba)
5477{
5478 bool queue_eh_work = false;
5479
5480 if (hba->errors & INT_FATAL_ERRORS) {
5481 ufshcd_update_reg_hist(&hba->ufs_stats.fatal_err, hba->errors);
5482 queue_eh_work = true;
5483 }
5484
5485 if (hba->errors & UIC_ERROR) {
5486 hba->uic_error = 0;
5487 ufshcd_update_uic_error(hba);
5488 if (hba->uic_error)
5489 queue_eh_work = true;
5490 }
5491
5492 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
5493 dev_err(hba->dev,
5494 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
5495 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
5496 "Enter" : "Exit",
5497 hba->errors, ufshcd_get_upmcrs(hba));
5498 ufshcd_update_reg_hist(&hba->ufs_stats.auto_hibern8_err,
5499 hba->errors);
5500 queue_eh_work = true;
5501 }
5502
5503 if (queue_eh_work) {
5504
5505
5506
5507
5508 hba->saved_err |= hba->errors;
5509 hba->saved_uic_err |= hba->uic_error;
5510
5511
5512 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5513
5514 ufshcd_scsi_block_requests(hba);
5515
5516 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
5517
5518
5519 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5520 bool pr_prdt = !!(hba->saved_err &
5521 SYSTEM_BUS_FATAL_ERROR);
5522
5523 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5524 __func__, hba->saved_err,
5525 hba->saved_uic_err);
5526
5527 ufshcd_print_host_regs(hba);
5528 ufshcd_print_pwr_info(hba);
5529 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5530 ufshcd_print_trs(hba, hba->outstanding_reqs,
5531 pr_prdt);
5532 }
5533 schedule_work(&hba->eh_work);
5534 }
5535 }
5536
5537
5538
5539
5540
5541
5542}
5543
5544
5545
5546
5547
5548static void ufshcd_tmc_handler(struct ufs_hba *hba)
5549{
5550 u32 tm_doorbell;
5551
5552 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
5553 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
5554 wake_up(&hba->tm_wq);
5555}
5556
5557
5558
5559
5560
5561
5562static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5563{
5564 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5565
5566 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5567 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5568
5569 if (hba->errors)
5570 ufshcd_check_errors(hba);
5571
5572 if (intr_status & UFSHCD_UIC_MASK)
5573 ufshcd_uic_cmd_compl(hba, intr_status);
5574
5575 if (intr_status & UTP_TASK_REQ_COMPL)
5576 ufshcd_tmc_handler(hba);
5577
5578 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5579 ufshcd_transfer_req_compl(hba);
5580}
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590static irqreturn_t ufshcd_intr(int irq, void *__hba)
5591{
5592 u32 intr_status, enabled_intr_status;
5593 irqreturn_t retval = IRQ_NONE;
5594 struct ufs_hba *hba = __hba;
5595 int retries = hba->nutrs;
5596
5597 spin_lock(hba->host->host_lock);
5598 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5599
5600
5601
5602
5603
5604
5605
5606 do {
5607 enabled_intr_status =
5608 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5609 if (intr_status)
5610 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
5611 if (enabled_intr_status) {
5612 ufshcd_sl_intr(hba, enabled_intr_status);
5613 retval = IRQ_HANDLED;
5614 }
5615
5616 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5617 } while (intr_status && --retries);
5618
5619 spin_unlock(hba->host->host_lock);
5620 return retval;
5621}
5622
5623static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5624{
5625 int err = 0;
5626 u32 mask = 1 << tag;
5627 unsigned long flags;
5628
5629 if (!test_bit(tag, &hba->outstanding_tasks))
5630 goto out;
5631
5632 spin_lock_irqsave(hba->host->host_lock, flags);
5633 ufshcd_utmrl_clear(hba, tag);
5634 spin_unlock_irqrestore(hba->host->host_lock, flags);
5635
5636
5637 err = ufshcd_wait_for_register(hba,
5638 REG_UTP_TASK_REQ_DOOR_BELL,
5639 mask, 0, 1000, 1000, true);
5640out:
5641 return err;
5642}
5643
5644static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5645 struct utp_task_req_desc *treq, u8 tm_function)
5646{
5647 struct Scsi_Host *host = hba->host;
5648 unsigned long flags;
5649 int free_slot, task_tag, err;
5650
5651
5652
5653
5654
5655
5656 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
5657 ufshcd_hold(hba, false);
5658
5659 spin_lock_irqsave(host->host_lock, flags);
5660 task_tag = hba->nutrs + free_slot;
5661
5662 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5663
5664 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
5665 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5666
5667
5668 __set_bit(free_slot, &hba->outstanding_tasks);
5669
5670
5671 wmb();
5672
5673 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
5674
5675 wmb();
5676
5677 spin_unlock_irqrestore(host->host_lock, flags);
5678
5679 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5680
5681
5682 err = wait_event_timeout(hba->tm_wq,
5683 test_bit(free_slot, &hba->tm_condition),
5684 msecs_to_jiffies(TM_CMD_TIMEOUT));
5685 if (!err) {
5686 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
5687 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5688 __func__, tm_function);
5689 if (ufshcd_clear_tm_cmd(hba, free_slot))
5690 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5691 __func__, free_slot);
5692 err = -ETIMEDOUT;
5693 } else {
5694 err = 0;
5695 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5696
5697 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
5698 }
5699
5700 spin_lock_irqsave(hba->host->host_lock, flags);
5701 __clear_bit(free_slot, &hba->outstanding_tasks);
5702 spin_unlock_irqrestore(hba->host->host_lock, flags);
5703
5704 clear_bit(free_slot, &hba->tm_condition);
5705 ufshcd_put_tm_slot(hba, free_slot);
5706 wake_up(&hba->tm_tag_wq);
5707
5708 ufshcd_release(hba);
5709 return err;
5710}
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5723 u8 tm_function, u8 *tm_response)
5724{
5725 struct utp_task_req_desc treq = { { 0 }, };
5726 int ocs_value, err;
5727
5728
5729 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5730 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5731
5732
5733 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
5734 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
5735 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
5736
5737
5738
5739
5740
5741 treq.input_param1 = cpu_to_be32(lun_id);
5742 treq.input_param2 = cpu_to_be32(task_id);
5743
5744 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
5745 if (err == -ETIMEDOUT)
5746 return err;
5747
5748 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5749 if (ocs_value != OCS_SUCCESS)
5750 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
5751 __func__, ocs_value);
5752 else if (tm_response)
5753 *tm_response = be32_to_cpu(treq.output_param1) &
5754 MASK_TM_SERVICE_RESP;
5755 return err;
5756}
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
5776 struct utp_upiu_req *req_upiu,
5777 struct utp_upiu_req *rsp_upiu,
5778 u8 *desc_buff, int *buff_len,
5779 int cmd_type,
5780 enum query_opcode desc_op)
5781{
5782 struct ufshcd_lrb *lrbp;
5783 int err = 0;
5784 int tag;
5785 struct completion wait;
5786 unsigned long flags;
5787 u32 upiu_flags;
5788
5789 down_read(&hba->clk_scaling_lock);
5790
5791 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
5792
5793 init_completion(&wait);
5794 lrbp = &hba->lrb[tag];
5795 WARN_ON(lrbp->cmd);
5796
5797 lrbp->cmd = NULL;
5798 lrbp->sense_bufflen = 0;
5799 lrbp->sense_buffer = NULL;
5800 lrbp->task_tag = tag;
5801 lrbp->lun = 0;
5802 lrbp->intr_cmd = true;
5803 hba->dev_cmd.type = cmd_type;
5804
5805 switch (hba->ufs_version) {
5806 case UFSHCI_VERSION_10:
5807 case UFSHCI_VERSION_11:
5808 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
5809 break;
5810 default:
5811 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5812 break;
5813 }
5814
5815
5816 req_upiu->header.dword_0 |= cpu_to_be32(tag);
5817
5818 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
5819
5820
5821 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
5822 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
5823
5824
5825
5826
5827 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
5828 *buff_len = 0;
5829 }
5830
5831 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5832
5833 hba->dev_cmd.complete = &wait;
5834
5835
5836 wmb();
5837 spin_lock_irqsave(hba->host->host_lock, flags);
5838 ufshcd_send_command(hba, tag);
5839 spin_unlock_irqrestore(hba->host->host_lock, flags);
5840
5841
5842
5843
5844
5845
5846 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
5847
5848
5849 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
5850 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
5851 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
5852 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
5853 MASK_QUERY_DATA_SEG_LEN;
5854
5855 if (*buff_len >= resp_len) {
5856 memcpy(desc_buff, descp, resp_len);
5857 *buff_len = resp_len;
5858 } else {
5859 dev_warn(hba->dev, "rsp size is bigger than buffer");
5860 *buff_len = 0;
5861 err = -EINVAL;
5862 }
5863 }
5864
5865 ufshcd_put_dev_cmd_tag(hba, tag);
5866 wake_up(&hba->dev_cmd.tag_wq);
5867 up_read(&hba->clk_scaling_lock);
5868 return err;
5869}
5870
5871
5872
5873
5874
5875
5876
5877
5878
5879
5880
5881
5882
5883
5884
5885
5886int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
5887 struct utp_upiu_req *req_upiu,
5888 struct utp_upiu_req *rsp_upiu,
5889 int msgcode,
5890 u8 *desc_buff, int *buff_len,
5891 enum query_opcode desc_op)
5892{
5893 int err;
5894 int cmd_type = DEV_CMD_TYPE_QUERY;
5895 struct utp_task_req_desc treq = { { 0 }, };
5896 int ocs_value;
5897 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
5898
5899 switch (msgcode) {
5900 case UPIU_TRANSACTION_NOP_OUT:
5901 cmd_type = DEV_CMD_TYPE_NOP;
5902
5903 case UPIU_TRANSACTION_QUERY_REQ:
5904 ufshcd_hold(hba, false);
5905 mutex_lock(&hba->dev_cmd.lock);
5906 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
5907 desc_buff, buff_len,
5908 cmd_type, desc_op);
5909 mutex_unlock(&hba->dev_cmd.lock);
5910 ufshcd_release(hba);
5911
5912 break;
5913 case UPIU_TRANSACTION_TASK_REQ:
5914 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5915 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5916
5917 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
5918
5919 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
5920 if (err == -ETIMEDOUT)
5921 break;
5922
5923 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5924 if (ocs_value != OCS_SUCCESS) {
5925 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
5926 ocs_value);
5927 break;
5928 }
5929
5930 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
5931
5932 break;
5933 default:
5934 err = -EINVAL;
5935
5936 break;
5937 }
5938
5939 return err;
5940}
5941
5942
5943
5944
5945
5946
5947
5948
5949static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
5950{
5951 struct Scsi_Host *host;
5952 struct ufs_hba *hba;
5953 unsigned int tag;
5954 u32 pos;
5955 int err;
5956 u8 resp = 0xF;
5957 struct ufshcd_lrb *lrbp;
5958 unsigned long flags;
5959
5960 host = cmd->device->host;
5961 hba = shost_priv(host);
5962 tag = cmd->request->tag;
5963
5964 lrbp = &hba->lrb[tag];
5965 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5966 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
5967 if (!err)
5968 err = resp;
5969 goto out;
5970 }
5971
5972
5973 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5974 if (hba->lrb[pos].lun == lrbp->lun) {
5975 err = ufshcd_clear_cmd(hba, pos);
5976 if (err)
5977 break;
5978 }
5979 }
5980 spin_lock_irqsave(host->host_lock, flags);
5981 ufshcd_transfer_req_compl(hba);
5982 spin_unlock_irqrestore(host->host_lock, flags);
5983
5984out:
5985 hba->req_abort_count = 0;
5986 ufshcd_update_reg_hist(&hba->ufs_stats.dev_reset, (u32)err);
5987 if (!err) {
5988 err = SUCCESS;
5989 } else {
5990 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5991 err = FAILED;
5992 }
5993 return err;
5994}
5995
5996static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5997{
5998 struct ufshcd_lrb *lrbp;
5999 int tag;
6000
6001 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6002 lrbp = &hba->lrb[tag];
6003 lrbp->req_abort_skip = true;
6004 }
6005}
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019static int ufshcd_abort(struct scsi_cmnd *cmd)
6020{
6021 struct Scsi_Host *host;
6022 struct ufs_hba *hba;
6023 unsigned long flags;
6024 unsigned int tag;
6025 int err = 0;
6026 int poll_cnt;
6027 u8 resp = 0xF;
6028 struct ufshcd_lrb *lrbp;
6029 u32 reg;
6030
6031 host = cmd->device->host;
6032 hba = shost_priv(host);
6033 tag = cmd->request->tag;
6034 lrbp = &hba->lrb[tag];
6035 if (!ufshcd_valid_tag(hba, tag)) {
6036 dev_err(hba->dev,
6037 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
6038 __func__, tag, cmd, cmd->request);
6039 BUG();
6040 }
6041
6042
6043
6044
6045
6046
6047
6048
6049 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
6050 return ufshcd_eh_host_reset_handler(cmd);
6051
6052 ufshcd_hold(hba, false);
6053 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6054
6055 if (!(test_bit(tag, &hba->outstanding_reqs))) {
6056 dev_err(hba->dev,
6057 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6058 __func__, tag, hba->outstanding_reqs, reg);
6059 goto out;
6060 }
6061
6062 if (!(reg & (1 << tag))) {
6063 dev_err(hba->dev,
6064 "%s: cmd was completed, but without a notifying intr, tag = %d",
6065 __func__, tag);
6066 }
6067
6068
6069 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
6070
6071
6072
6073
6074
6075
6076
6077
6078 scsi_print_command(hba->lrb[tag].cmd);
6079 if (!hba->req_abort_count) {
6080 ufshcd_update_reg_hist(&hba->ufs_stats.task_abort, 0);
6081 ufshcd_print_host_regs(hba);
6082 ufshcd_print_host_state(hba);
6083 ufshcd_print_pwr_info(hba);
6084 ufshcd_print_trs(hba, 1 << tag, true);
6085 } else {
6086 ufshcd_print_trs(hba, 1 << tag, false);
6087 }
6088 hba->req_abort_count++;
6089
6090
6091 if (lrbp->req_abort_skip) {
6092 err = -EIO;
6093 goto out;
6094 }
6095
6096 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6097 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6098 UFS_QUERY_TASK, &resp);
6099 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6100
6101 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6102 __func__, tag);
6103 break;
6104 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6105
6106
6107
6108
6109 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6110 __func__, tag);
6111 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6112 if (reg & (1 << tag)) {
6113
6114 usleep_range(100, 200);
6115 continue;
6116 }
6117
6118 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6119 __func__, tag);
6120 goto out;
6121 } else {
6122 dev_err(hba->dev,
6123 "%s: no response from device. tag = %d, err %d\n",
6124 __func__, tag, err);
6125 if (!err)
6126 err = resp;
6127 goto out;
6128 }
6129 }
6130
6131 if (!poll_cnt) {
6132 err = -EBUSY;
6133 goto out;
6134 }
6135
6136 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6137 UFS_ABORT_TASK, &resp);
6138 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6139 if (!err) {
6140 err = resp;
6141 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6142 __func__, tag, err);
6143 }
6144 goto out;
6145 }
6146
6147 err = ufshcd_clear_cmd(hba, tag);
6148 if (err) {
6149 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6150 __func__, tag, err);
6151 goto out;
6152 }
6153
6154 scsi_dma_unmap(cmd);
6155
6156 spin_lock_irqsave(host->host_lock, flags);
6157 ufshcd_outstanding_req_clear(hba, tag);
6158 hba->lrb[tag].cmd = NULL;
6159 spin_unlock_irqrestore(host->host_lock, flags);
6160
6161 clear_bit_unlock(tag, &hba->lrb_in_use);
6162 wake_up(&hba->dev_cmd.tag_wq);
6163
6164out:
6165 if (!err) {
6166 err = SUCCESS;
6167 } else {
6168 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6169 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
6170 err = FAILED;
6171 }
6172
6173
6174
6175
6176
6177 ufshcd_release(hba);
6178 return err;
6179}
6180
6181
6182
6183
6184
6185
6186
6187
6188
6189
6190
6191static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6192{
6193 int err;
6194 unsigned long flags;
6195
6196
6197 spin_lock_irqsave(hba->host->host_lock, flags);
6198 ufshcd_hba_stop(hba, false);
6199 spin_unlock_irqrestore(hba->host->host_lock, flags);
6200
6201
6202 ufshcd_scale_clks(hba, true);
6203
6204 err = ufshcd_hba_enable(hba);
6205 if (err)
6206 goto out;
6207
6208
6209 err = ufshcd_probe_hba(hba);
6210
6211 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
6212 err = -EIO;
6213out:
6214 if (err)
6215 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
6216 ufshcd_update_reg_hist(&hba->ufs_stats.host_reset, (u32)err);
6217 return err;
6218}
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6230{
6231 int err = 0;
6232 unsigned long flags;
6233 int retries = MAX_HOST_RESET_RETRIES;
6234
6235 do {
6236
6237 ufshcd_vops_device_reset(hba);
6238
6239 err = ufshcd_host_reset_and_restore(hba);
6240 } while (err && --retries);
6241
6242
6243
6244
6245
6246 spin_lock_irqsave(hba->host->host_lock, flags);
6247 ufshcd_transfer_req_compl(hba);
6248 ufshcd_tmc_handler(hba);
6249 spin_unlock_irqrestore(hba->host->host_lock, flags);
6250
6251 return err;
6252}
6253
6254
6255
6256
6257
6258
6259
6260static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6261{
6262 int err;
6263 unsigned long flags;
6264 struct ufs_hba *hba;
6265
6266 hba = shost_priv(cmd->device->host);
6267
6268 ufshcd_hold(hba, false);
6269
6270
6271
6272
6273
6274
6275 do {
6276 spin_lock_irqsave(hba->host->host_lock, flags);
6277 if (!(work_pending(&hba->eh_work) ||
6278 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6279 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
6280 break;
6281 spin_unlock_irqrestore(hba->host->host_lock, flags);
6282 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
6283 flush_work(&hba->eh_work);
6284 } while (1);
6285
6286 hba->ufshcd_state = UFSHCD_STATE_RESET;
6287 ufshcd_set_eh_in_progress(hba);
6288 spin_unlock_irqrestore(hba->host->host_lock, flags);
6289
6290 err = ufshcd_reset_and_restore(hba);
6291
6292 spin_lock_irqsave(hba->host->host_lock, flags);
6293 if (!err) {
6294 err = SUCCESS;
6295 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6296 } else {
6297 err = FAILED;
6298 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6299 }
6300 ufshcd_clear_eh_in_progress(hba);
6301 spin_unlock_irqrestore(hba->host->host_lock, flags);
6302
6303 ufshcd_release(hba);
6304 return err;
6305}
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6316{
6317 int i;
6318 int curr_uA;
6319 u16 data;
6320 u16 unit;
6321
6322 for (i = start_scan; i >= 0; i--) {
6323 data = be16_to_cpup((__be16 *)&buff[2 * i]);
6324 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6325 ATTR_ICC_LVL_UNIT_OFFSET;
6326 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6327 switch (unit) {
6328 case UFSHCD_NANO_AMP:
6329 curr_uA = curr_uA / 1000;
6330 break;
6331 case UFSHCD_MILI_AMP:
6332 curr_uA = curr_uA * 1000;
6333 break;
6334 case UFSHCD_AMP:
6335 curr_uA = curr_uA * 1000 * 1000;
6336 break;
6337 case UFSHCD_MICRO_AMP:
6338 default:
6339 break;
6340 }
6341 if (sup_curr_uA >= curr_uA)
6342 break;
6343 }
6344 if (i < 0) {
6345 i = 0;
6346 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6347 }
6348
6349 return (u32)i;
6350}
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6362 u8 *desc_buf, int len)
6363{
6364 u32 icc_level = 0;
6365
6366 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6367 !hba->vreg_info.vccq2) {
6368 dev_err(hba->dev,
6369 "%s: Regulator capability was not set, actvIccLevel=%d",
6370 __func__, icc_level);
6371 goto out;
6372 }
6373
6374 if (hba->vreg_info.vcc && hba->vreg_info.vcc->max_uA)
6375 icc_level = ufshcd_get_max_icc_level(
6376 hba->vreg_info.vcc->max_uA,
6377 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6378 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6379
6380 if (hba->vreg_info.vccq && hba->vreg_info.vccq->max_uA)
6381 icc_level = ufshcd_get_max_icc_level(
6382 hba->vreg_info.vccq->max_uA,
6383 icc_level,
6384 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6385
6386 if (hba->vreg_info.vccq2 && hba->vreg_info.vccq2->max_uA)
6387 icc_level = ufshcd_get_max_icc_level(
6388 hba->vreg_info.vccq2->max_uA,
6389 icc_level,
6390 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6391out:
6392 return icc_level;
6393}
6394
6395static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6396{
6397 int ret;
6398 int buff_len = hba->desc_size.pwr_desc;
6399 u8 *desc_buf;
6400
6401 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6402 if (!desc_buf)
6403 return;
6404
6405 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6406 if (ret) {
6407 dev_err(hba->dev,
6408 "%s: Failed reading power descriptor.len = %d ret = %d",
6409 __func__, buff_len, ret);
6410 goto out;
6411 }
6412
6413 hba->init_prefetch_data.icc_level =
6414 ufshcd_find_max_sup_active_icc_level(hba,
6415 desc_buf, buff_len);
6416 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6417 __func__, hba->init_prefetch_data.icc_level);
6418
6419 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6420 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6421 &hba->init_prefetch_data.icc_level);
6422
6423 if (ret)
6424 dev_err(hba->dev,
6425 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6426 __func__, hba->init_prefetch_data.icc_level , ret);
6427
6428out:
6429 kfree(desc_buf);
6430}
6431
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455
6456
6457
6458static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6459{
6460 int ret = 0;
6461 struct scsi_device *sdev_rpmb;
6462 struct scsi_device *sdev_boot;
6463
6464 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6465 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6466 if (IS_ERR(hba->sdev_ufs_device)) {
6467 ret = PTR_ERR(hba->sdev_ufs_device);
6468 hba->sdev_ufs_device = NULL;
6469 goto out;
6470 }
6471 scsi_device_put(hba->sdev_ufs_device);
6472
6473 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
6474 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
6475 if (IS_ERR(sdev_rpmb)) {
6476 ret = PTR_ERR(sdev_rpmb);
6477 goto remove_sdev_ufs_device;
6478 }
6479 scsi_device_put(sdev_rpmb);
6480
6481 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6482 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6483 if (IS_ERR(sdev_boot))
6484 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6485 else
6486 scsi_device_put(sdev_boot);
6487 goto out;
6488
6489remove_sdev_ufs_device:
6490 scsi_remove_device(hba->sdev_ufs_device);
6491out:
6492 return ret;
6493}
6494
6495static int ufs_get_device_desc(struct ufs_hba *hba,
6496 struct ufs_dev_desc *dev_desc)
6497{
6498 int err;
6499 size_t buff_len;
6500 u8 model_index;
6501 u8 *desc_buf;
6502
6503 if (!dev_desc)
6504 return -EINVAL;
6505
6506 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6507 QUERY_DESC_MAX_SIZE + 1);
6508 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6509 if (!desc_buf) {
6510 err = -ENOMEM;
6511 goto out;
6512 }
6513
6514 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
6515 if (err) {
6516 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6517 __func__, err);
6518 goto out;
6519 }
6520
6521
6522
6523
6524
6525 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
6526 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6527
6528 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6529 err = ufshcd_read_string_desc(hba, model_index,
6530 &dev_desc->model, SD_ASCII_STD);
6531 if (err < 0) {
6532 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6533 __func__, err);
6534 goto out;
6535 }
6536
6537
6538
6539
6540
6541 err = 0;
6542
6543out:
6544 kfree(desc_buf);
6545 return err;
6546}
6547
6548static void ufs_put_device_desc(struct ufs_dev_desc *dev_desc)
6549{
6550 kfree(dev_desc->model);
6551 dev_desc->model = NULL;
6552}
6553
6554static void ufs_fixup_device_setup(struct ufs_hba *hba,
6555 struct ufs_dev_desc *dev_desc)
6556{
6557 struct ufs_dev_fix *f;
6558
6559 for (f = ufs_fixups; f->quirk; f++) {
6560 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6561 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6562 ((dev_desc->model &&
6563 STR_PRFX_EQUAL(f->card.model, dev_desc->model)) ||
6564 !strcmp(f->card.model, UFS_ANY_MODEL)))
6565 hba->dev_quirks |= f->quirk;
6566 }
6567}
6568
6569
6570
6571
6572
6573
6574
6575
6576
6577
6578
6579
6580static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6581{
6582 int ret = 0;
6583 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6584
6585 ret = ufshcd_dme_peer_get(hba,
6586 UIC_ARG_MIB_SEL(
6587 RX_MIN_ACTIVATETIME_CAPABILITY,
6588 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6589 &peer_rx_min_activatetime);
6590 if (ret)
6591 goto out;
6592
6593
6594 tuned_pa_tactivate =
6595 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6596 / PA_TACTIVATE_TIME_UNIT_US);
6597 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6598 tuned_pa_tactivate);
6599
6600out:
6601 return ret;
6602}
6603
6604
6605
6606
6607
6608
6609
6610
6611
6612
6613
6614
6615static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6616{
6617 int ret = 0;
6618 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6619 u32 max_hibern8_time, tuned_pa_hibern8time;
6620
6621 ret = ufshcd_dme_get(hba,
6622 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6623 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6624 &local_tx_hibern8_time_cap);
6625 if (ret)
6626 goto out;
6627
6628 ret = ufshcd_dme_peer_get(hba,
6629 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6630 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6631 &peer_rx_hibern8_time_cap);
6632 if (ret)
6633 goto out;
6634
6635 max_hibern8_time = max(local_tx_hibern8_time_cap,
6636 peer_rx_hibern8_time_cap);
6637
6638 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6639 / PA_HIBERN8_TIME_UNIT_US);
6640 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6641 tuned_pa_hibern8time);
6642out:
6643 return ret;
6644}
6645
6646
6647
6648
6649
6650
6651
6652
6653
6654
6655
6656
6657static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6658{
6659 int ret = 0;
6660 u32 granularity, peer_granularity;
6661 u32 pa_tactivate, peer_pa_tactivate;
6662 u32 pa_tactivate_us, peer_pa_tactivate_us;
6663 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6664
6665 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6666 &granularity);
6667 if (ret)
6668 goto out;
6669
6670 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6671 &peer_granularity);
6672 if (ret)
6673 goto out;
6674
6675 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6676 (granularity > PA_GRANULARITY_MAX_VAL)) {
6677 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6678 __func__, granularity);
6679 return -EINVAL;
6680 }
6681
6682 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6683 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6684 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6685 __func__, peer_granularity);
6686 return -EINVAL;
6687 }
6688
6689 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6690 if (ret)
6691 goto out;
6692
6693 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6694 &peer_pa_tactivate);
6695 if (ret)
6696 goto out;
6697
6698 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6699 peer_pa_tactivate_us = peer_pa_tactivate *
6700 gran_to_us_table[peer_granularity - 1];
6701
6702 if (pa_tactivate_us > peer_pa_tactivate_us) {
6703 u32 new_peer_pa_tactivate;
6704
6705 new_peer_pa_tactivate = pa_tactivate_us /
6706 gran_to_us_table[peer_granularity - 1];
6707 new_peer_pa_tactivate++;
6708 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6709 new_peer_pa_tactivate);
6710 }
6711
6712out:
6713 return ret;
6714}
6715
6716static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6717{
6718 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6719 ufshcd_tune_pa_tactivate(hba);
6720 ufshcd_tune_pa_hibern8time(hba);
6721 }
6722
6723 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6724
6725 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
6726
6727 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6728 ufshcd_quirk_tune_host_pa_tactivate(hba);
6729
6730 ufshcd_vops_apply_dev_quirks(hba);
6731}
6732
6733static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6734{
6735 hba->ufs_stats.hibern8_exit_cnt = 0;
6736 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6737 hba->req_abort_count = 0;
6738}
6739
6740static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6741{
6742 int err;
6743
6744 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6745 &hba->desc_size.dev_desc);
6746 if (err)
6747 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6748
6749 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6750 &hba->desc_size.pwr_desc);
6751 if (err)
6752 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6753
6754 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6755 &hba->desc_size.interc_desc);
6756 if (err)
6757 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6758
6759 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6760 &hba->desc_size.conf_desc);
6761 if (err)
6762 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6763
6764 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6765 &hba->desc_size.unit_desc);
6766 if (err)
6767 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6768
6769 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6770 &hba->desc_size.geom_desc);
6771 if (err)
6772 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6773 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6774 &hba->desc_size.hlth_desc);
6775 if (err)
6776 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
6777}
6778
6779static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6780{
6781 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6782 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6783 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6784 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6785 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6786 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6787 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
6788}
6789
6790static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
6791 {19200000, REF_CLK_FREQ_19_2_MHZ},
6792 {26000000, REF_CLK_FREQ_26_MHZ},
6793 {38400000, REF_CLK_FREQ_38_4_MHZ},
6794 {52000000, REF_CLK_FREQ_52_MHZ},
6795 {0, REF_CLK_FREQ_INVAL},
6796};
6797
6798static enum ufs_ref_clk_freq
6799ufs_get_bref_clk_from_hz(unsigned long freq)
6800{
6801 int i;
6802
6803 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
6804 if (ufs_ref_clk_freqs[i].freq_hz == freq)
6805 return ufs_ref_clk_freqs[i].val;
6806
6807 return REF_CLK_FREQ_INVAL;
6808}
6809
6810void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
6811{
6812 unsigned long freq;
6813
6814 freq = clk_get_rate(refclk);
6815
6816 hba->dev_ref_clk_freq =
6817 ufs_get_bref_clk_from_hz(freq);
6818
6819 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
6820 dev_err(hba->dev,
6821 "invalid ref_clk setting = %ld\n", freq);
6822}
6823
6824static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
6825{
6826 int err;
6827 u32 ref_clk;
6828 u32 freq = hba->dev_ref_clk_freq;
6829
6830 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6831 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
6832
6833 if (err) {
6834 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
6835 err);
6836 goto out;
6837 }
6838
6839 if (ref_clk == freq)
6840 goto out;
6841
6842 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6843 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
6844
6845 if (err) {
6846 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
6847 ufs_ref_clk_freqs[freq].freq_hz);
6848 goto out;
6849 }
6850
6851 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
6852 ufs_ref_clk_freqs[freq].freq_hz);
6853
6854out:
6855 return err;
6856}
6857
6858
6859
6860
6861
6862
6863
6864static int ufshcd_probe_hba(struct ufs_hba *hba)
6865{
6866 struct ufs_dev_desc card = {0};
6867 int ret;
6868 ktime_t start = ktime_get();
6869
6870 ret = ufshcd_link_startup(hba);
6871 if (ret)
6872 goto out;
6873
6874
6875 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6876 hba->is_urgent_bkops_lvl_checked = false;
6877
6878
6879 ufshcd_clear_dbg_ufs_stats(hba);
6880
6881
6882 ufshcd_set_link_active(hba);
6883
6884
6885 ufshcd_auto_hibern8_enable(hba);
6886
6887 ret = ufshcd_verify_dev_init(hba);
6888 if (ret)
6889 goto out;
6890
6891 ret = ufshcd_complete_dev_init(hba);
6892 if (ret)
6893 goto out;
6894
6895
6896 ufshcd_init_desc_sizes(hba);
6897
6898 ret = ufs_get_device_desc(hba, &card);
6899 if (ret) {
6900 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6901 __func__, ret);
6902 goto out;
6903 }
6904
6905 ufs_fixup_device_setup(hba, &card);
6906 ufs_put_device_desc(&card);
6907
6908 ufshcd_tune_unipro_params(hba);
6909
6910
6911 ufshcd_set_ufs_dev_active(hba);
6912 ufshcd_force_reset_auto_bkops(hba);
6913 hba->wlun_dev_clr_ua = true;
6914
6915 if (ufshcd_get_max_pwr_mode(hba)) {
6916 dev_err(hba->dev,
6917 "%s: Failed getting max supported power mode\n",
6918 __func__);
6919 } else {
6920
6921
6922
6923
6924 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
6925 ufshcd_set_dev_ref_clk(hba);
6926 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
6927 if (ret) {
6928 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6929 __func__, ret);
6930 goto out;
6931 }
6932 }
6933
6934
6935 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6936
6937
6938
6939
6940
6941 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6942 bool flag;
6943
6944
6945 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
6946 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6947 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
6948 hba->dev_info.f_power_on_wp_en = flag;
6949
6950 if (!hba->is_init_prefetch)
6951 ufshcd_init_icc_levels(hba);
6952
6953
6954 if (ufshcd_scsi_add_wlus(hba))
6955 goto out;
6956
6957
6958 if (ufshcd_is_clkscaling_supported(hba)) {
6959 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6960 &hba->pwr_info,
6961 sizeof(struct ufs_pa_layer_attr));
6962 hba->clk_scaling.saved_pwr_info.is_valid = true;
6963 if (!hba->devfreq) {
6964 ret = ufshcd_devfreq_init(hba);
6965 if (ret)
6966 goto out;
6967 }
6968 hba->clk_scaling.is_allowed = true;
6969 }
6970
6971 ufs_bsg_probe(hba);
6972
6973 scsi_scan_host(hba->host);
6974 pm_runtime_put_sync(hba->dev);
6975 }
6976
6977 if (!hba->is_init_prefetch)
6978 hba->is_init_prefetch = true;
6979
6980out:
6981
6982
6983
6984
6985 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6986 pm_runtime_put_sync(hba->dev);
6987 ufshcd_exit_clk_scaling(hba);
6988 ufshcd_hba_exit(hba);
6989 }
6990
6991 trace_ufshcd_init(dev_name(hba->dev), ret,
6992 ktime_to_us(ktime_sub(ktime_get(), start)),
6993 hba->curr_dev_pwr_mode, hba->uic_link_state);
6994 return ret;
6995}
6996
6997
6998
6999
7000
7001
7002static void ufshcd_async_scan(void *data, async_cookie_t cookie)
7003{
7004 struct ufs_hba *hba = (struct ufs_hba *)data;
7005
7006 ufshcd_probe_hba(hba);
7007}
7008
7009static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
7010{
7011 unsigned long flags;
7012 struct Scsi_Host *host;
7013 struct ufs_hba *hba;
7014 int index;
7015 bool found = false;
7016
7017 if (!scmd || !scmd->device || !scmd->device->host)
7018 return BLK_EH_DONE;
7019
7020 host = scmd->device->host;
7021 hba = shost_priv(host);
7022 if (!hba)
7023 return BLK_EH_DONE;
7024
7025 spin_lock_irqsave(host->host_lock, flags);
7026
7027 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
7028 if (hba->lrb[index].cmd == scmd) {
7029 found = true;
7030 break;
7031 }
7032 }
7033
7034 spin_unlock_irqrestore(host->host_lock, flags);
7035
7036
7037
7038
7039
7040
7041 return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
7042}
7043
7044static const struct attribute_group *ufshcd_driver_groups[] = {
7045 &ufs_sysfs_unit_descriptor_group,
7046 &ufs_sysfs_lun_attributes_group,
7047 NULL,
7048};
7049
7050static struct scsi_host_template ufshcd_driver_template = {
7051 .module = THIS_MODULE,
7052 .name = UFSHCD,
7053 .proc_name = UFSHCD,
7054 .queuecommand = ufshcd_queuecommand,
7055 .slave_alloc = ufshcd_slave_alloc,
7056 .slave_configure = ufshcd_slave_configure,
7057 .slave_destroy = ufshcd_slave_destroy,
7058 .change_queue_depth = ufshcd_change_queue_depth,
7059 .eh_abort_handler = ufshcd_abort,
7060 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7061 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7062 .eh_timed_out = ufshcd_eh_timed_out,
7063 .this_id = -1,
7064 .sg_tablesize = SG_ALL,
7065 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
7066 .can_queue = UFSHCD_CAN_QUEUE,
7067 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
7068 .max_host_blocked = 1,
7069 .track_queue_depth = 1,
7070 .sdev_groups = ufshcd_driver_groups,
7071 .dma_boundary = PAGE_SIZE - 1,
7072};
7073
7074static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7075 int ua)
7076{
7077 int ret;
7078
7079 if (!vreg)
7080 return 0;
7081
7082
7083
7084
7085
7086
7087
7088 if (!vreg->max_uA)
7089 return 0;
7090
7091 ret = regulator_set_load(vreg->reg, ua);
7092 if (ret < 0) {
7093 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7094 __func__, vreg->name, ua, ret);
7095 }
7096
7097 return ret;
7098}
7099
7100static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7101 struct ufs_vreg *vreg)
7102{
7103 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
7104}
7105
7106static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7107 struct ufs_vreg *vreg)
7108{
7109 if (!vreg)
7110 return 0;
7111
7112 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
7113}
7114
7115static int ufshcd_config_vreg(struct device *dev,
7116 struct ufs_vreg *vreg, bool on)
7117{
7118 int ret = 0;
7119 struct regulator *reg;
7120 const char *name;
7121 int min_uV, uA_load;
7122
7123 BUG_ON(!vreg);
7124
7125 reg = vreg->reg;
7126 name = vreg->name;
7127
7128 if (regulator_count_voltages(reg) > 0) {
7129 if (vreg->min_uV && vreg->max_uV) {
7130 min_uV = on ? vreg->min_uV : 0;
7131 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7132 if (ret) {
7133 dev_err(dev,
7134 "%s: %s set voltage failed, err=%d\n",
7135 __func__, name, ret);
7136 goto out;
7137 }
7138 }
7139
7140 uA_load = on ? vreg->max_uA : 0;
7141 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7142 if (ret)
7143 goto out;
7144 }
7145out:
7146 return ret;
7147}
7148
7149static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7150{
7151 int ret = 0;
7152
7153 if (!vreg || vreg->enabled)
7154 goto out;
7155
7156 ret = ufshcd_config_vreg(dev, vreg, true);
7157 if (!ret)
7158 ret = regulator_enable(vreg->reg);
7159
7160 if (!ret)
7161 vreg->enabled = true;
7162 else
7163 dev_err(dev, "%s: %s enable failed, err=%d\n",
7164 __func__, vreg->name, ret);
7165out:
7166 return ret;
7167}
7168
7169static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7170{
7171 int ret = 0;
7172
7173 if (!vreg || !vreg->enabled)
7174 goto out;
7175
7176 ret = regulator_disable(vreg->reg);
7177
7178 if (!ret) {
7179
7180 ufshcd_config_vreg(dev, vreg, false);
7181 vreg->enabled = false;
7182 } else {
7183 dev_err(dev, "%s: %s disable failed, err=%d\n",
7184 __func__, vreg->name, ret);
7185 }
7186out:
7187 return ret;
7188}
7189
7190static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7191{
7192 int ret = 0;
7193 struct device *dev = hba->dev;
7194 struct ufs_vreg_info *info = &hba->vreg_info;
7195
7196 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7197 if (ret)
7198 goto out;
7199
7200 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7201 if (ret)
7202 goto out;
7203
7204 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7205 if (ret)
7206 goto out;
7207
7208out:
7209 if (ret) {
7210 ufshcd_toggle_vreg(dev, info->vccq2, false);
7211 ufshcd_toggle_vreg(dev, info->vccq, false);
7212 ufshcd_toggle_vreg(dev, info->vcc, false);
7213 }
7214 return ret;
7215}
7216
7217static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7218{
7219 struct ufs_vreg_info *info = &hba->vreg_info;
7220
7221 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
7222}
7223
7224static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7225{
7226 int ret = 0;
7227
7228 if (!vreg)
7229 goto out;
7230
7231 vreg->reg = devm_regulator_get(dev, vreg->name);
7232 if (IS_ERR(vreg->reg)) {
7233 ret = PTR_ERR(vreg->reg);
7234 dev_err(dev, "%s: %s get failed, err=%d\n",
7235 __func__, vreg->name, ret);
7236 }
7237out:
7238 return ret;
7239}
7240
7241static int ufshcd_init_vreg(struct ufs_hba *hba)
7242{
7243 int ret = 0;
7244 struct device *dev = hba->dev;
7245 struct ufs_vreg_info *info = &hba->vreg_info;
7246
7247 ret = ufshcd_get_vreg(dev, info->vcc);
7248 if (ret)
7249 goto out;
7250
7251 ret = ufshcd_get_vreg(dev, info->vccq);
7252 if (ret)
7253 goto out;
7254
7255 ret = ufshcd_get_vreg(dev, info->vccq2);
7256out:
7257 return ret;
7258}
7259
7260static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7261{
7262 struct ufs_vreg_info *info = &hba->vreg_info;
7263
7264 if (info)
7265 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7266
7267 return 0;
7268}
7269
7270static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7271 bool skip_ref_clk)
7272{
7273 int ret = 0;
7274 struct ufs_clk_info *clki;
7275 struct list_head *head = &hba->clk_list_head;
7276 unsigned long flags;
7277 ktime_t start = ktime_get();
7278 bool clk_state_changed = false;
7279
7280 if (list_empty(head))
7281 goto out;
7282
7283
7284
7285
7286
7287
7288 if (!on) {
7289 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7290 if (ret)
7291 return ret;
7292 }
7293
7294 list_for_each_entry(clki, head, list) {
7295 if (!IS_ERR_OR_NULL(clki->clk)) {
7296 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7297 continue;
7298
7299 clk_state_changed = on ^ clki->enabled;
7300 if (on && !clki->enabled) {
7301 ret = clk_prepare_enable(clki->clk);
7302 if (ret) {
7303 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7304 __func__, clki->name, ret);
7305 goto out;
7306 }
7307 } else if (!on && clki->enabled) {
7308 clk_disable_unprepare(clki->clk);
7309 }
7310 clki->enabled = on;
7311 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7312 clki->name, on ? "en" : "dis");
7313 }
7314 }
7315
7316
7317
7318
7319
7320
7321 if (on) {
7322 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7323 if (ret)
7324 return ret;
7325 }
7326
7327out:
7328 if (ret) {
7329 list_for_each_entry(clki, head, list) {
7330 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7331 clk_disable_unprepare(clki->clk);
7332 }
7333 } else if (!ret && on) {
7334 spin_lock_irqsave(hba->host->host_lock, flags);
7335 hba->clk_gating.state = CLKS_ON;
7336 trace_ufshcd_clk_gating(dev_name(hba->dev),
7337 hba->clk_gating.state);
7338 spin_unlock_irqrestore(hba->host->host_lock, flags);
7339 }
7340
7341 if (clk_state_changed)
7342 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7343 (on ? "on" : "off"),
7344 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
7345 return ret;
7346}
7347
7348static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7349{
7350 return __ufshcd_setup_clocks(hba, on, false);
7351}
7352
7353static int ufshcd_init_clocks(struct ufs_hba *hba)
7354{
7355 int ret = 0;
7356 struct ufs_clk_info *clki;
7357 struct device *dev = hba->dev;
7358 struct list_head *head = &hba->clk_list_head;
7359
7360 if (list_empty(head))
7361 goto out;
7362
7363 list_for_each_entry(clki, head, list) {
7364 if (!clki->name)
7365 continue;
7366
7367 clki->clk = devm_clk_get(dev, clki->name);
7368 if (IS_ERR(clki->clk)) {
7369 ret = PTR_ERR(clki->clk);
7370 dev_err(dev, "%s: %s clk get failed, %d\n",
7371 __func__, clki->name, ret);
7372 goto out;
7373 }
7374
7375
7376
7377
7378
7379
7380 if (!strcmp(clki->name, "ref_clk"))
7381 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
7382
7383 if (clki->max_freq) {
7384 ret = clk_set_rate(clki->clk, clki->max_freq);
7385 if (ret) {
7386 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7387 __func__, clki->name,
7388 clki->max_freq, ret);
7389 goto out;
7390 }
7391 clki->curr_freq = clki->max_freq;
7392 }
7393 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7394 clki->name, clk_get_rate(clki->clk));
7395 }
7396out:
7397 return ret;
7398}
7399
7400static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7401{
7402 int err = 0;
7403
7404 if (!hba->vops)
7405 goto out;
7406
7407 err = ufshcd_vops_init(hba);
7408 if (err)
7409 goto out;
7410
7411 err = ufshcd_vops_setup_regulators(hba, true);
7412 if (err)
7413 goto out_exit;
7414
7415 goto out;
7416
7417out_exit:
7418 ufshcd_vops_exit(hba);
7419out:
7420 if (err)
7421 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
7422 __func__, ufshcd_get_var_name(hba), err);
7423 return err;
7424}
7425
7426static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7427{
7428 if (!hba->vops)
7429 return;
7430
7431 ufshcd_vops_setup_regulators(hba, false);
7432
7433 ufshcd_vops_exit(hba);
7434}
7435
7436static int ufshcd_hba_init(struct ufs_hba *hba)
7437{
7438 int err;
7439
7440
7441
7442
7443
7444
7445
7446
7447 err = ufshcd_init_hba_vreg(hba);
7448 if (err)
7449 goto out;
7450
7451 err = ufshcd_setup_hba_vreg(hba, true);
7452 if (err)
7453 goto out;
7454
7455 err = ufshcd_init_clocks(hba);
7456 if (err)
7457 goto out_disable_hba_vreg;
7458
7459 err = ufshcd_setup_clocks(hba, true);
7460 if (err)
7461 goto out_disable_hba_vreg;
7462
7463 err = ufshcd_init_vreg(hba);
7464 if (err)
7465 goto out_disable_clks;
7466
7467 err = ufshcd_setup_vreg(hba, true);
7468 if (err)
7469 goto out_disable_clks;
7470
7471 err = ufshcd_variant_hba_init(hba);
7472 if (err)
7473 goto out_disable_vreg;
7474
7475 hba->is_powered = true;
7476 goto out;
7477
7478out_disable_vreg:
7479 ufshcd_setup_vreg(hba, false);
7480out_disable_clks:
7481 ufshcd_setup_clocks(hba, false);
7482out_disable_hba_vreg:
7483 ufshcd_setup_hba_vreg(hba, false);
7484out:
7485 return err;
7486}
7487
7488static void ufshcd_hba_exit(struct ufs_hba *hba)
7489{
7490 if (hba->is_powered) {
7491 ufshcd_variant_hba_exit(hba);
7492 ufshcd_setup_vreg(hba, false);
7493 ufshcd_suspend_clkscaling(hba);
7494 if (ufshcd_is_clkscaling_supported(hba))
7495 if (hba->devfreq)
7496 ufshcd_suspend_clkscaling(hba);
7497 ufshcd_setup_clocks(hba, false);
7498 ufshcd_setup_hba_vreg(hba, false);
7499 hba->is_powered = false;
7500 }
7501}
7502
7503static int
7504ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7505{
7506 unsigned char cmd[6] = {REQUEST_SENSE,
7507 0,
7508 0,
7509 0,
7510 UFS_SENSE_SIZE,
7511 0};
7512 char *buffer;
7513 int ret;
7514
7515 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
7516 if (!buffer) {
7517 ret = -ENOMEM;
7518 goto out;
7519 }
7520
7521 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7522 UFS_SENSE_SIZE, NULL, NULL,
7523 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
7524 if (ret)
7525 pr_err("%s: failed with err %d\n", __func__, ret);
7526
7527 kfree(buffer);
7528out:
7529 return ret;
7530}
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7542 enum ufs_dev_pwr_mode pwr_mode)
7543{
7544 unsigned char cmd[6] = { START_STOP };
7545 struct scsi_sense_hdr sshdr;
7546 struct scsi_device *sdp;
7547 unsigned long flags;
7548 int ret;
7549
7550 spin_lock_irqsave(hba->host->host_lock, flags);
7551 sdp = hba->sdev_ufs_device;
7552 if (sdp) {
7553 ret = scsi_device_get(sdp);
7554 if (!ret && !scsi_device_online(sdp)) {
7555 ret = -ENODEV;
7556 scsi_device_put(sdp);
7557 }
7558 } else {
7559 ret = -ENODEV;
7560 }
7561 spin_unlock_irqrestore(hba->host->host_lock, flags);
7562
7563 if (ret)
7564 return ret;
7565
7566
7567
7568
7569
7570
7571
7572 hba->host->eh_noresume = 1;
7573 if (hba->wlun_dev_clr_ua) {
7574 ret = ufshcd_send_request_sense(hba, sdp);
7575 if (ret)
7576 goto out;
7577
7578 hba->wlun_dev_clr_ua = false;
7579 }
7580
7581 cmd[4] = pwr_mode << 4;
7582
7583
7584
7585
7586
7587
7588 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7589 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
7590 if (ret) {
7591 sdev_printk(KERN_WARNING, sdp,
7592 "START_STOP failed for power mode: %d, result %x\n",
7593 pwr_mode, ret);
7594 if (driver_byte(ret) == DRIVER_SENSE)
7595 scsi_print_sense_hdr(sdp, NULL, &sshdr);
7596 }
7597
7598 if (!ret)
7599 hba->curr_dev_pwr_mode = pwr_mode;
7600out:
7601 scsi_device_put(sdp);
7602 hba->host->eh_noresume = 0;
7603 return ret;
7604}
7605
7606static int ufshcd_link_state_transition(struct ufs_hba *hba,
7607 enum uic_link_state req_link_state,
7608 int check_for_bkops)
7609{
7610 int ret = 0;
7611
7612 if (req_link_state == hba->uic_link_state)
7613 return 0;
7614
7615 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7616 ret = ufshcd_uic_hibern8_enter(hba);
7617 if (!ret)
7618 ufshcd_set_link_hibern8(hba);
7619 else
7620 goto out;
7621 }
7622
7623
7624
7625
7626 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7627 (!check_for_bkops || (check_for_bkops &&
7628 !hba->auto_bkops_enabled))) {
7629
7630
7631
7632
7633
7634
7635
7636 ret = ufshcd_uic_hibern8_enter(hba);
7637 if (ret)
7638 goto out;
7639
7640
7641
7642
7643 ufshcd_hba_stop(hba, true);
7644
7645
7646
7647
7648 ufshcd_set_link_off(hba);
7649 }
7650
7651out:
7652 return ret;
7653}
7654
7655static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7656{
7657
7658
7659
7660
7661
7662
7663 if (!ufshcd_is_link_active(hba) &&
7664 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7665 usleep_range(2000, 2100);
7666
7667
7668
7669
7670
7671
7672
7673
7674
7675
7676
7677
7678
7679 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7680 !hba->dev_info.is_lu_power_on_wp) {
7681 ufshcd_setup_vreg(hba, false);
7682 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7683 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7684 if (!ufshcd_is_link_active(hba)) {
7685 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7686 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7687 }
7688 }
7689}
7690
7691static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7692{
7693 int ret = 0;
7694
7695 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7696 !hba->dev_info.is_lu_power_on_wp) {
7697 ret = ufshcd_setup_vreg(hba, true);
7698 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7699 if (!ret && !ufshcd_is_link_active(hba)) {
7700 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7701 if (ret)
7702 goto vcc_disable;
7703 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7704 if (ret)
7705 goto vccq_lpm;
7706 }
7707 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
7708 }
7709 goto out;
7710
7711vccq_lpm:
7712 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7713vcc_disable:
7714 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7715out:
7716 return ret;
7717}
7718
7719static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7720{
7721 if (ufshcd_is_link_off(hba))
7722 ufshcd_setup_hba_vreg(hba, false);
7723}
7724
7725static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7726{
7727 if (ufshcd_is_link_off(hba))
7728 ufshcd_setup_hba_vreg(hba, true);
7729}
7730
7731
7732
7733
7734
7735
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745
7746
7747static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7748{
7749 int ret = 0;
7750 enum ufs_pm_level pm_lvl;
7751 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7752 enum uic_link_state req_link_state;
7753
7754 hba->pm_op_in_progress = 1;
7755 if (!ufshcd_is_shutdown_pm(pm_op)) {
7756 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7757 hba->rpm_lvl : hba->spm_lvl;
7758 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7759 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7760 } else {
7761 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7762 req_link_state = UIC_LINK_OFF_STATE;
7763 }
7764
7765
7766
7767
7768
7769 ufshcd_hold(hba, false);
7770 hba->clk_gating.is_suspended = true;
7771
7772 if (hba->clk_scaling.is_allowed) {
7773 cancel_work_sync(&hba->clk_scaling.suspend_work);
7774 cancel_work_sync(&hba->clk_scaling.resume_work);
7775 ufshcd_suspend_clkscaling(hba);
7776 }
7777
7778 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7779 req_link_state == UIC_LINK_ACTIVE_STATE) {
7780 goto disable_clks;
7781 }
7782
7783 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7784 (req_link_state == hba->uic_link_state))
7785 goto enable_gating;
7786
7787
7788 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7789 ret = -EINVAL;
7790 goto enable_gating;
7791 }
7792
7793 if (ufshcd_is_runtime_pm(pm_op)) {
7794 if (ufshcd_can_autobkops_during_suspend(hba)) {
7795
7796
7797
7798
7799
7800 ret = ufshcd_urgent_bkops(hba);
7801 if (ret)
7802 goto enable_gating;
7803 } else {
7804
7805 ufshcd_disable_auto_bkops(hba);
7806 }
7807 }
7808
7809 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7810 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7811 !ufshcd_is_runtime_pm(pm_op))) {
7812
7813 ufshcd_disable_auto_bkops(hba);
7814 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7815 if (ret)
7816 goto enable_gating;
7817 }
7818
7819 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7820 if (ret)
7821 goto set_dev_active;
7822
7823 ufshcd_vreg_set_lpm(hba);
7824
7825disable_clks:
7826
7827
7828
7829
7830
7831 ret = ufshcd_vops_suspend(hba, pm_op);
7832 if (ret)
7833 goto set_link_active;
7834
7835 if (!ufshcd_is_link_active(hba))
7836 ufshcd_setup_clocks(hba, false);
7837 else
7838
7839 __ufshcd_setup_clocks(hba, false, true);
7840
7841 hba->clk_gating.state = CLKS_OFF;
7842 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
7843
7844
7845
7846
7847 ufshcd_disable_irq(hba);
7848
7849 ufshcd_hba_vreg_set_lpm(hba);
7850 goto out;
7851
7852set_link_active:
7853 if (hba->clk_scaling.is_allowed)
7854 ufshcd_resume_clkscaling(hba);
7855 ufshcd_vreg_set_hpm(hba);
7856 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7857 ufshcd_set_link_active(hba);
7858 else if (ufshcd_is_link_off(hba))
7859 ufshcd_host_reset_and_restore(hba);
7860set_dev_active:
7861 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7862 ufshcd_disable_auto_bkops(hba);
7863enable_gating:
7864 if (hba->clk_scaling.is_allowed)
7865 ufshcd_resume_clkscaling(hba);
7866 hba->clk_gating.is_suspended = false;
7867 ufshcd_release(hba);
7868out:
7869 hba->pm_op_in_progress = 0;
7870 if (ret)
7871 ufshcd_update_reg_hist(&hba->ufs_stats.suspend_err, (u32)ret);
7872 return ret;
7873}
7874
7875
7876
7877
7878
7879
7880
7881
7882
7883
7884
7885static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7886{
7887 int ret;
7888 enum uic_link_state old_link_state;
7889
7890 hba->pm_op_in_progress = 1;
7891 old_link_state = hba->uic_link_state;
7892
7893 ufshcd_hba_vreg_set_hpm(hba);
7894
7895 ret = ufshcd_setup_clocks(hba, true);
7896 if (ret)
7897 goto out;
7898
7899
7900 ret = ufshcd_enable_irq(hba);
7901 if (ret)
7902 goto disable_irq_and_vops_clks;
7903
7904 ret = ufshcd_vreg_set_hpm(hba);
7905 if (ret)
7906 goto disable_irq_and_vops_clks;
7907
7908
7909
7910
7911
7912
7913 ret = ufshcd_vops_resume(hba, pm_op);
7914 if (ret)
7915 goto disable_vreg;
7916
7917 if (ufshcd_is_link_hibern8(hba)) {
7918 ret = ufshcd_uic_hibern8_exit(hba);
7919 if (!ret)
7920 ufshcd_set_link_active(hba);
7921 else
7922 goto vendor_suspend;
7923 } else if (ufshcd_is_link_off(hba)) {
7924 ret = ufshcd_host_reset_and_restore(hba);
7925
7926
7927
7928
7929 if (ret || !ufshcd_is_link_active(hba))
7930 goto vendor_suspend;
7931 }
7932
7933 if (!ufshcd_is_ufs_dev_active(hba)) {
7934 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7935 if (ret)
7936 goto set_old_link_state;
7937 }
7938
7939 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7940 ufshcd_enable_auto_bkops(hba);
7941 else
7942
7943
7944
7945
7946 ufshcd_urgent_bkops(hba);
7947
7948 hba->clk_gating.is_suspended = false;
7949
7950 if (hba->clk_scaling.is_allowed)
7951 ufshcd_resume_clkscaling(hba);
7952
7953
7954 ufshcd_release(hba);
7955
7956
7957 ufshcd_auto_hibern8_enable(hba);
7958
7959 goto out;
7960
7961set_old_link_state:
7962 ufshcd_link_state_transition(hba, old_link_state, 0);
7963vendor_suspend:
7964 ufshcd_vops_suspend(hba, pm_op);
7965disable_vreg:
7966 ufshcd_vreg_set_lpm(hba);
7967disable_irq_and_vops_clks:
7968 ufshcd_disable_irq(hba);
7969 if (hba->clk_scaling.is_allowed)
7970 ufshcd_suspend_clkscaling(hba);
7971 ufshcd_setup_clocks(hba, false);
7972out:
7973 hba->pm_op_in_progress = 0;
7974 if (ret)
7975 ufshcd_update_reg_hist(&hba->ufs_stats.resume_err, (u32)ret);
7976 return ret;
7977}
7978
7979
7980
7981
7982
7983
7984
7985
7986
7987int ufshcd_system_suspend(struct ufs_hba *hba)
7988{
7989 int ret = 0;
7990 ktime_t start = ktime_get();
7991
7992 if (!hba || !hba->is_powered)
7993 return 0;
7994
7995 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7996 hba->curr_dev_pwr_mode) &&
7997 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7998 hba->uic_link_state))
7999 goto out;
8000
8001 if (pm_runtime_suspended(hba->dev)) {
8002
8003
8004
8005
8006
8007
8008
8009
8010 ret = ufshcd_runtime_resume(hba);
8011 if (ret)
8012 goto out;
8013 }
8014
8015 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8016out:
8017 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8018 ktime_to_us(ktime_sub(ktime_get(), start)),
8019 hba->curr_dev_pwr_mode, hba->uic_link_state);
8020 if (!ret)
8021 hba->is_sys_suspended = true;
8022 return ret;
8023}
8024EXPORT_SYMBOL(ufshcd_system_suspend);
8025
8026
8027
8028
8029
8030
8031
8032
8033int ufshcd_system_resume(struct ufs_hba *hba)
8034{
8035 int ret = 0;
8036 ktime_t start = ktime_get();
8037
8038 if (!hba)
8039 return -EINVAL;
8040
8041 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
8042
8043
8044
8045
8046 goto out;
8047 else
8048 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8049out:
8050 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8051 ktime_to_us(ktime_sub(ktime_get(), start)),
8052 hba->curr_dev_pwr_mode, hba->uic_link_state);
8053 if (!ret)
8054 hba->is_sys_suspended = false;
8055 return ret;
8056}
8057EXPORT_SYMBOL(ufshcd_system_resume);
8058
8059
8060
8061
8062
8063
8064
8065
8066
8067int ufshcd_runtime_suspend(struct ufs_hba *hba)
8068{
8069 int ret = 0;
8070 ktime_t start = ktime_get();
8071
8072 if (!hba)
8073 return -EINVAL;
8074
8075 if (!hba->is_powered)
8076 goto out;
8077 else
8078 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8079out:
8080 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8081 ktime_to_us(ktime_sub(ktime_get(), start)),
8082 hba->curr_dev_pwr_mode, hba->uic_link_state);
8083 return ret;
8084}
8085EXPORT_SYMBOL(ufshcd_runtime_suspend);
8086
8087
8088
8089
8090
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101
8102
8103
8104
8105
8106
8107
8108int ufshcd_runtime_resume(struct ufs_hba *hba)
8109{
8110 int ret = 0;
8111 ktime_t start = ktime_get();
8112
8113 if (!hba)
8114 return -EINVAL;
8115
8116 if (!hba->is_powered)
8117 goto out;
8118 else
8119 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8120out:
8121 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8122 ktime_to_us(ktime_sub(ktime_get(), start)),
8123 hba->curr_dev_pwr_mode, hba->uic_link_state);
8124 return ret;
8125}
8126EXPORT_SYMBOL(ufshcd_runtime_resume);
8127
8128int ufshcd_runtime_idle(struct ufs_hba *hba)
8129{
8130 return 0;
8131}
8132EXPORT_SYMBOL(ufshcd_runtime_idle);
8133
8134
8135
8136
8137
8138
8139
8140
8141
8142int ufshcd_shutdown(struct ufs_hba *hba)
8143{
8144 int ret = 0;
8145
8146 if (!hba->is_powered)
8147 goto out;
8148
8149 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8150 goto out;
8151
8152 if (pm_runtime_suspended(hba->dev)) {
8153 ret = ufshcd_runtime_resume(hba);
8154 if (ret)
8155 goto out;
8156 }
8157
8158 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8159out:
8160 if (ret)
8161 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8162
8163 return 0;
8164}
8165EXPORT_SYMBOL(ufshcd_shutdown);
8166
8167
8168
8169
8170
8171
8172void ufshcd_remove(struct ufs_hba *hba)
8173{
8174 ufs_bsg_remove(hba);
8175 ufs_sysfs_remove_nodes(hba->dev);
8176 scsi_remove_host(hba->host);
8177
8178 ufshcd_disable_intr(hba, hba->intr_mask);
8179 ufshcd_hba_stop(hba, true);
8180
8181 ufshcd_exit_clk_scaling(hba);
8182 ufshcd_exit_clk_gating(hba);
8183 if (ufshcd_is_clkscaling_supported(hba))
8184 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
8185 ufshcd_hba_exit(hba);
8186}
8187EXPORT_SYMBOL_GPL(ufshcd_remove);
8188
8189
8190
8191
8192
8193void ufshcd_dealloc_host(struct ufs_hba *hba)
8194{
8195 scsi_host_put(hba->host);
8196}
8197EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8198
8199
8200
8201
8202
8203
8204
8205
8206static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8207{
8208 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8209 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8210 return 0;
8211 }
8212 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8213}
8214
8215
8216
8217
8218
8219
8220
8221int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
8222{
8223 struct Scsi_Host *host;
8224 struct ufs_hba *hba;
8225 int err = 0;
8226
8227 if (!dev) {
8228 dev_err(dev,
8229 "Invalid memory reference for dev is NULL\n");
8230 err = -ENODEV;
8231 goto out_error;
8232 }
8233
8234 host = scsi_host_alloc(&ufshcd_driver_template,
8235 sizeof(struct ufs_hba));
8236 if (!host) {
8237 dev_err(dev, "scsi_host_alloc failed\n");
8238 err = -ENOMEM;
8239 goto out_error;
8240 }
8241 hba = shost_priv(host);
8242 hba->host = host;
8243 hba->dev = dev;
8244 *hba_handle = hba;
8245 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
8246
8247 INIT_LIST_HEAD(&hba->clk_list_head);
8248
8249out_error:
8250 return err;
8251}
8252EXPORT_SYMBOL(ufshcd_alloc_host);
8253
8254
8255
8256
8257
8258
8259
8260
8261int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8262{
8263 int err;
8264 struct Scsi_Host *host = hba->host;
8265 struct device *dev = hba->dev;
8266
8267 if (!mmio_base) {
8268 dev_err(hba->dev,
8269 "Invalid memory reference for mmio_base is NULL\n");
8270 err = -ENODEV;
8271 goto out_error;
8272 }
8273
8274 hba->mmio_base = mmio_base;
8275 hba->irq = irq;
8276
8277
8278 ufshcd_def_desc_sizes(hba);
8279
8280 err = ufshcd_hba_init(hba);
8281 if (err)
8282 goto out_error;
8283
8284
8285 ufshcd_hba_capabilities(hba);
8286
8287
8288 hba->ufs_version = ufshcd_get_ufs_version(hba);
8289
8290 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8291 (hba->ufs_version != UFSHCI_VERSION_11) &&
8292 (hba->ufs_version != UFSHCI_VERSION_20) &&
8293 (hba->ufs_version != UFSHCI_VERSION_21))
8294 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8295 hba->ufs_version);
8296
8297
8298 hba->intr_mask = ufshcd_get_intr_mask(hba);
8299
8300 err = ufshcd_set_dma_mask(hba);
8301 if (err) {
8302 dev_err(hba->dev, "set dma mask failed\n");
8303 goto out_disable;
8304 }
8305
8306
8307 err = ufshcd_memory_alloc(hba);
8308 if (err) {
8309 dev_err(hba->dev, "Memory allocation failed\n");
8310 goto out_disable;
8311 }
8312
8313
8314 ufshcd_host_memory_configure(hba);
8315
8316 host->can_queue = hba->nutrs;
8317 host->cmd_per_lun = hba->nutrs;
8318 host->max_id = UFSHCD_MAX_ID;
8319 host->max_lun = UFS_MAX_LUNS;
8320 host->max_channel = UFSHCD_MAX_CHANNEL;
8321 host->unique_id = host->host_no;
8322 host->max_cmd_len = UFS_CDB_SIZE;
8323
8324 hba->max_pwr_info.is_valid = false;
8325
8326
8327 init_waitqueue_head(&hba->tm_wq);
8328 init_waitqueue_head(&hba->tm_tag_wq);
8329
8330
8331 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
8332 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
8333
8334
8335 mutex_init(&hba->uic_cmd_mutex);
8336
8337
8338 mutex_init(&hba->dev_cmd.lock);
8339
8340 init_rwsem(&hba->clk_scaling_lock);
8341
8342
8343 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8344
8345 ufshcd_init_clk_gating(hba);
8346
8347 ufshcd_init_clk_scaling(hba);
8348
8349
8350
8351
8352
8353
8354 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8355 REG_INTERRUPT_STATUS);
8356 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8357
8358
8359
8360
8361 mb();
8362
8363
8364 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
8365 if (err) {
8366 dev_err(hba->dev, "request irq failed\n");
8367 goto exit_gating;
8368 } else {
8369 hba->is_irq_enabled = true;
8370 }
8371
8372 err = scsi_add_host(host, hba->dev);
8373 if (err) {
8374 dev_err(hba->dev, "scsi_add_host failed\n");
8375 goto exit_gating;
8376 }
8377
8378
8379 ufshcd_vops_device_reset(hba);
8380
8381
8382 err = ufshcd_hba_enable(hba);
8383 if (err) {
8384 dev_err(hba->dev, "Host controller enable failed\n");
8385 ufshcd_print_host_regs(hba);
8386 ufshcd_print_host_state(hba);
8387 goto out_remove_scsi_host;
8388 }
8389
8390
8391
8392
8393
8394
8395 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8396 UFS_SLEEP_PWR_MODE,
8397 UIC_LINK_HIBERN8_STATE);
8398 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8399 UFS_SLEEP_PWR_MODE,
8400 UIC_LINK_HIBERN8_STATE);
8401
8402
8403 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
8404 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8405 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8406 }
8407
8408
8409 pm_runtime_get_sync(dev);
8410 atomic_set(&hba->scsi_block_reqs_cnt, 0);
8411
8412
8413
8414
8415
8416
8417 ufshcd_set_ufs_dev_active(hba);
8418
8419 async_schedule(ufshcd_async_scan, hba);
8420 ufs_sysfs_add_nodes(hba->dev);
8421
8422 return 0;
8423
8424out_remove_scsi_host:
8425 scsi_remove_host(hba->host);
8426exit_gating:
8427 ufshcd_exit_clk_scaling(hba);
8428 ufshcd_exit_clk_gating(hba);
8429out_disable:
8430 hba->is_irq_enabled = false;
8431 ufshcd_hba_exit(hba);
8432out_error:
8433 return err;
8434}
8435EXPORT_SYMBOL_GPL(ufshcd_init);
8436
8437MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8438MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
8439MODULE_DESCRIPTION("Generic UFS host controller driver Core");
8440MODULE_LICENSE("GPL");
8441MODULE_VERSION(UFSHCD_DRIVER_VERSION);
8442