linux/drivers/staging/media/imx/imx7-mipi-csis.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
   4 *
   5 * Copyright (C) 2019 Linaro Ltd
   6 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
   7 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
   8 *
   9 */
  10
  11#include <linux/clk.h>
  12#include <linux/debugfs.h>
  13#include <linux/delay.h>
  14#include <linux/errno.h>
  15#include <linux/interrupt.h>
  16#include <linux/io.h>
  17#include <linux/irq.h>
  18#include <linux/kernel.h>
  19#include <linux/mfd/syscon.h>
  20#include <linux/module.h>
  21#include <linux/of_graph.h>
  22#include <linux/platform_device.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/reset.h>
  25#include <linux/regulator/consumer.h>
  26#include <linux/spinlock.h>
  27
  28#include <media/v4l2-device.h>
  29#include <media/v4l2-fwnode.h>
  30#include <media/v4l2-subdev.h>
  31
  32#include "imx-media.h"
  33
  34#define CSIS_DRIVER_NAME        "imx7-mipi-csis"
  35#define CSIS_SUBDEV_NAME        CSIS_DRIVER_NAME
  36
  37#define CSIS_PAD_SINK           0
  38#define CSIS_PAD_SOURCE         1
  39#define CSIS_PADS_NUM           2
  40
  41#define MIPI_CSIS_DEF_PIX_WIDTH         640
  42#define MIPI_CSIS_DEF_PIX_HEIGHT        480
  43
  44/* Register map definition */
  45
  46/* CSIS common control */
  47#define MIPI_CSIS_CMN_CTRL                      0x04
  48#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW        BIT(16)
  49#define MIPI_CSIS_CMN_CTRL_INTER_MODE           BIT(10)
  50#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL   BIT(2)
  51#define MIPI_CSIS_CMN_CTRL_RESET                BIT(1)
  52#define MIPI_CSIS_CMN_CTRL_ENABLE               BIT(0)
  53
  54#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET       8
  55#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK         (3 << 8)
  56
  57/* CSIS clock control */
  58#define MIPI_CSIS_CLK_CTRL                      0x08
  59#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
  60#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
  61#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
  62#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
  63#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK       (0xf << 4)
  64#define MIPI_CSIS_CLK_CTRL_WCLK_SRC             BIT(0)
  65
  66/* CSIS Interrupt mask */
  67#define MIPI_CSIS_INTMSK                0x10
  68#define MIPI_CSIS_INTMSK_EVEN_BEFORE    BIT(31)
  69#define MIPI_CSIS_INTMSK_EVEN_AFTER     BIT(30)
  70#define MIPI_CSIS_INTMSK_ODD_BEFORE     BIT(29)
  71#define MIPI_CSIS_INTMSK_ODD_AFTER      BIT(28)
  72#define MIPI_CSIS_INTMSK_FRAME_START    BIT(24)
  73#define MIPI_CSIS_INTMSK_FRAME_END      BIT(20)
  74#define MIPI_CSIS_INTMSK_ERR_SOT_HS     BIT(16)
  75#define MIPI_CSIS_INTMSK_ERR_LOST_FS    BIT(12)
  76#define MIPI_CSIS_INTMSK_ERR_LOST_FE    BIT(8)
  77#define MIPI_CSIS_INTMSK_ERR_OVER       BIT(4)
  78#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG  BIT(3)
  79#define MIPI_CSIS_INTMSK_ERR_ECC        BIT(2)
  80#define MIPI_CSIS_INTMSK_ERR_CRC        BIT(1)
  81#define MIPI_CSIS_INTMSK_ERR_UNKNOWN    BIT(0)
  82
  83/* CSIS Interrupt source */
  84#define MIPI_CSIS_INTSRC                0x14
  85#define MIPI_CSIS_INTSRC_EVEN_BEFORE    BIT(31)
  86#define MIPI_CSIS_INTSRC_EVEN_AFTER     BIT(30)
  87#define MIPI_CSIS_INTSRC_EVEN           BIT(30)
  88#define MIPI_CSIS_INTSRC_ODD_BEFORE     BIT(29)
  89#define MIPI_CSIS_INTSRC_ODD_AFTER      BIT(28)
  90#define MIPI_CSIS_INTSRC_ODD            (0x3 << 28)
  91#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
  92#define MIPI_CSIS_INTSRC_FRAME_START    BIT(24)
  93#define MIPI_CSIS_INTSRC_FRAME_END      BIT(20)
  94#define MIPI_CSIS_INTSRC_ERR_SOT_HS     BIT(16)
  95#define MIPI_CSIS_INTSRC_ERR_LOST_FS    BIT(12)
  96#define MIPI_CSIS_INTSRC_ERR_LOST_FE    BIT(8)
  97#define MIPI_CSIS_INTSRC_ERR_OVER       BIT(4)
  98#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG  BIT(3)
  99#define MIPI_CSIS_INTSRC_ERR_ECC        BIT(2)
 100#define MIPI_CSIS_INTSRC_ERR_CRC        BIT(1)
 101#define MIPI_CSIS_INTSRC_ERR_UNKNOWN    BIT(0)
 102#define MIPI_CSIS_INTSRC_ERRORS         0xfffff
 103
 104/* D-PHY status control */
 105#define MIPI_CSIS_DPHYSTATUS                    0x20
 106#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT           BIT(8)
 107#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT      BIT(4)
 108#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK           BIT(1)
 109#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK      BIT(0)
 110
 111/* D-PHY common control */
 112#define MIPI_CSIS_DPHYCTRL                      0x24
 113#define MIPI_CSIS_DPHYCTRL_HSS_MASK             (0xff << 24)
 114#define MIPI_CSIS_DPHYCTRL_HSS_OFFSET           24
 115#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK           (0x3 << 22)
 116#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET         22
 117#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK        BIT(6)
 118#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT        BIT(5)
 119#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT           BIT(1)
 120#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK           BIT(0)
 121#define MIPI_CSIS_DPHYCTRL_ENABLE               (0x1f << 0)
 122
 123/* D-PHY Master and Slave Control register Low */
 124#define MIPI_CSIS_DPHYBCTRL_L           0x30
 125/* D-PHY Master and Slave Control register High */
 126#define MIPI_CSIS_DPHYBCTRL_H           0x34
 127/* D-PHY Slave Control register Low */
 128#define MIPI_CSIS_DPHYSCTRL_L           0x38
 129/* D-PHY Slave Control register High */
 130#define MIPI_CSIS_DPHYSCTRL_H           0x3c
 131
 132/* ISP Configuration register */
 133#define MIPI_CSIS_ISPCONFIG_CH0         0x40
 134#define MIPI_CSIS_ISPCONFIG_CH1         0x50
 135#define MIPI_CSIS_ISPCONFIG_CH2         0x60
 136#define MIPI_CSIS_ISPCONFIG_CH3         0x70
 137
 138#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK       (0xff << 24)
 139#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)        ((x) << 24)
 140#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT           BIT(12)
 141#define MIPI_CSIS_ISPCFG_ALIGN_32BIT            BIT(11)
 142#define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT      (0x1e << 2)
 143#define MIPI_CSIS_ISPCFG_FMT_RAW8               (0x2a << 2)
 144#define MIPI_CSIS_ISPCFG_FMT_RAW10              (0x2b << 2)
 145#define MIPI_CSIS_ISPCFG_FMT_RAW12              (0x2c << 2)
 146
 147/* User defined formats, x = 1...4 */
 148#define MIPI_CSIS_ISPCFG_FMT_USER(x)    ((0x30 + (x) - 1) << 2)
 149#define MIPI_CSIS_ISPCFG_FMT_MASK       (0x3f << 2)
 150
 151/* ISP Image Resolution register */
 152#define MIPI_CSIS_ISPRESOL_CH0          0x44
 153#define MIPI_CSIS_ISPRESOL_CH1          0x54
 154#define MIPI_CSIS_ISPRESOL_CH2          0x64
 155#define MIPI_CSIS_ISPRESOL_CH3          0x74
 156#define CSIS_MAX_PIX_WIDTH              0xffff
 157#define CSIS_MAX_PIX_HEIGHT             0xffff
 158
 159/* ISP SYNC register */
 160#define MIPI_CSIS_ISPSYNC_CH0           0x48
 161#define MIPI_CSIS_ISPSYNC_CH1           0x58
 162#define MIPI_CSIS_ISPSYNC_CH2           0x68
 163#define MIPI_CSIS_ISPSYNC_CH3           0x78
 164
 165#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET    18
 166#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET    12
 167#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET    0
 168
 169/* Non-image packet data buffers */
 170#define MIPI_CSIS_PKTDATA_ODD           0x2000
 171#define MIPI_CSIS_PKTDATA_EVEN          0x3000
 172#define MIPI_CSIS_PKTDATA_SIZE          SZ_4K
 173
 174#define DEFAULT_SCLK_CSIS_FREQ          166000000UL
 175
 176enum {
 177        ST_POWERED      = 1,
 178        ST_STREAMING    = 2,
 179        ST_SUSPENDED    = 4,
 180};
 181
 182struct mipi_csis_event {
 183        u32 mask;
 184        const char * const name;
 185        unsigned int counter;
 186};
 187
 188static const struct mipi_csis_event mipi_csis_events[] = {
 189        /* Errors */
 190        { MIPI_CSIS_INTSRC_ERR_SOT_HS,  "SOT Error" },
 191        { MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
 192        { MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
 193        { MIPI_CSIS_INTSRC_ERR_OVER,    "FIFO Overflow Error" },
 194        { MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
 195        { MIPI_CSIS_INTSRC_ERR_ECC,     "ECC Error" },
 196        { MIPI_CSIS_INTSRC_ERR_CRC,     "CRC Error" },
 197        { MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
 198        /* Non-image data receive events */
 199        { MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
 200        { MIPI_CSIS_INTSRC_EVEN_AFTER,  "Non-image data after even frame" },
 201        { MIPI_CSIS_INTSRC_ODD_BEFORE,  "Non-image data before odd frame" },
 202        { MIPI_CSIS_INTSRC_ODD_AFTER,   "Non-image data after odd frame" },
 203        /* Frame start/end */
 204        { MIPI_CSIS_INTSRC_FRAME_START, "Frame Start" },
 205        { MIPI_CSIS_INTSRC_FRAME_END,   "Frame End" },
 206};
 207
 208#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
 209
 210static const char * const mipi_csis_clk_id[] = {"pclk", "wrap", "phy"};
 211
 212struct csis_hw_reset {
 213        struct regmap *src;
 214        u8 req_src;
 215        u8 rst_bit;
 216};
 217
 218struct csi_state {
 219        /* lock elements below */
 220        struct mutex lock;
 221        /* lock for event handler */
 222        spinlock_t slock;
 223        struct device *dev;
 224        struct media_pad pads[CSIS_PADS_NUM];
 225        struct v4l2_subdev mipi_sd;
 226        struct v4l2_subdev *src_sd;
 227
 228        u8 index;
 229        struct platform_device *pdev;
 230        struct phy *phy;
 231        void __iomem *regs;
 232        struct clk *wrap_clk;
 233        int irq;
 234        u32 flags;
 235
 236        struct dentry *debugfs_root;
 237        bool debug;
 238
 239        int num_clks;
 240        struct clk_bulk_data *clks;
 241
 242        u32 clk_frequency;
 243        u32 hs_settle;
 244
 245        struct reset_control *mrst;
 246
 247        const struct csis_pix_format *csis_fmt;
 248        struct v4l2_mbus_framefmt format_mbus;
 249
 250        struct v4l2_fwnode_bus_mipi_csi2 bus;
 251
 252        struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
 253
 254        struct v4l2_async_notifier subdev_notifier;
 255
 256        struct csis_hw_reset hw_reset;
 257        struct regulator *mipi_phy_regulator;
 258        bool sink_linked;
 259};
 260
 261struct csis_pix_format {
 262        unsigned int pix_width_alignment;
 263        u32 code;
 264        u32 fmt_reg;
 265        u8 data_alignment;
 266};
 267
 268static const struct csis_pix_format mipi_csis_formats[] = {
 269        {
 270                .code = MEDIA_BUS_FMT_SBGGR10_1X10,
 271                .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
 272                .data_alignment = 16,
 273        }, {
 274                .code = MEDIA_BUS_FMT_VYUY8_2X8,
 275                .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
 276                .data_alignment = 16,
 277        }, {
 278                .code = MEDIA_BUS_FMT_SBGGR8_1X8,
 279                .fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
 280                .data_alignment = 8,
 281        }, {
 282                .code = MEDIA_BUS_FMT_YUYV8_2X8,
 283                .fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
 284                .data_alignment = 16,
 285        }
 286};
 287
 288#define mipi_csis_write(__csis, __r, __v) writel(__v, (__csis)->regs + (__r))
 289#define mipi_csis_read(__csis, __r) readl((__csis)->regs + (__r))
 290
 291static int mipi_csis_dump_regs(struct csi_state *state)
 292{
 293        struct device *dev = &state->pdev->dev;
 294        unsigned int i;
 295        u32 cfg;
 296        struct {
 297                u32 offset;
 298                const char * const name;
 299        } registers[] = {
 300                { 0x04, "CTRL" },
 301                { 0x24, "DPHYCTRL" },
 302                { 0x08, "CLKCTRL" },
 303                { 0x20, "DPHYSTS" },
 304                { 0x10, "INTMSK" },
 305                { 0x40, "CONFIG_CH0" },
 306                { 0xC0, "DBG_CONFIG" },
 307                { 0x38, "DPHYSLAVE_L" },
 308                { 0x3C, "DPHYSLAVE_H" },
 309        };
 310
 311        dev_info(dev, "--- REGISTERS ---\n");
 312
 313        for (i = 0; i < ARRAY_SIZE(registers); i++) {
 314                cfg = mipi_csis_read(state, registers[i].offset);
 315                dev_info(dev, "%12s: 0x%08x\n", registers[i].name, cfg);
 316        }
 317
 318        return 0;
 319}
 320
 321static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
 322{
 323        return container_of(sdev, struct csi_state, mipi_sd);
 324}
 325
 326static const struct csis_pix_format *find_csis_format(u32 code)
 327{
 328        unsigned int i;
 329
 330        for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
 331                if (code == mipi_csis_formats[i].code)
 332                        return &mipi_csis_formats[i];
 333        return NULL;
 334}
 335
 336static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
 337{
 338        mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0);
 339}
 340
 341static void mipi_csis_sw_reset(struct csi_state *state)
 342{
 343        u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 344
 345        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
 346                        val | MIPI_CSIS_CMN_CTRL_RESET);
 347        usleep_range(10, 20);
 348}
 349
 350static int mipi_csis_phy_init(struct csi_state *state)
 351{
 352        state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
 353
 354        return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
 355                                     1000000);
 356}
 357
 358static void mipi_csis_phy_reset(struct csi_state *state)
 359{
 360        reset_control_assert(state->mrst);
 361
 362        msleep(20);
 363
 364        reset_control_deassert(state->mrst);
 365}
 366
 367static void mipi_csis_system_enable(struct csi_state *state, int on)
 368{
 369        u32 val, mask;
 370
 371        val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 372        if (on)
 373                val |= MIPI_CSIS_CMN_CTRL_ENABLE;
 374        else
 375                val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
 376        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
 377
 378        val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
 379        val &= ~MIPI_CSIS_DPHYCTRL_ENABLE;
 380        if (on) {
 381                mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
 382                val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE);
 383        }
 384        mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
 385}
 386
 387/* Called with the state.lock mutex held */
 388static void __mipi_csis_set_format(struct csi_state *state)
 389{
 390        struct v4l2_mbus_framefmt *mf = &state->format_mbus;
 391        u32 val;
 392
 393        /* Color format */
 394        val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
 395        val = (val & ~MIPI_CSIS_ISPCFG_FMT_MASK) | state->csis_fmt->fmt_reg;
 396        mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
 397
 398        /* Pixel resolution */
 399        val = mf->width | (mf->height << 16);
 400        mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
 401}
 402
 403static void mipi_csis_set_hsync_settle(struct csi_state *state, int hs_settle)
 404{
 405        u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
 406
 407        val = ((val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (hs_settle << 24));
 408
 409        mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
 410}
 411
 412static void mipi_csis_set_params(struct csi_state *state)
 413{
 414        int lanes = state->bus.num_data_lanes;
 415        u32 val;
 416
 417        val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 418        val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
 419        val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
 420        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
 421
 422        __mipi_csis_set_format(state);
 423
 424        mipi_csis_set_hsync_settle(state, state->hs_settle);
 425
 426        val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
 427        if (state->csis_fmt->data_alignment == 32)
 428                val |= MIPI_CSIS_ISPCFG_ALIGN_32BIT;
 429        else
 430                val &= ~MIPI_CSIS_ISPCFG_ALIGN_32BIT;
 431        mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
 432
 433        val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
 434                (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
 435                (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
 436        mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val);
 437
 438        val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
 439        val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
 440        if (state->wrap_clk)
 441                val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
 442        else
 443                val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
 444
 445        val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
 446        val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
 447        mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
 448
 449        mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4);
 450        mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0);
 451
 452        /* Update the shadow register. */
 453        val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 454        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
 455                        val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
 456                        MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 457}
 458
 459static int mipi_csis_clk_enable(struct csi_state *state)
 460{
 461        return clk_bulk_prepare_enable(state->num_clks, state->clks);
 462}
 463
 464static void mipi_csis_clk_disable(struct csi_state *state)
 465{
 466        clk_bulk_disable_unprepare(state->num_clks, state->clks);
 467}
 468
 469static int mipi_csis_clk_get(struct csi_state *state)
 470{
 471        struct device *dev = &state->pdev->dev;
 472        unsigned int i;
 473        int ret;
 474
 475        state->num_clks = ARRAY_SIZE(mipi_csis_clk_id);
 476        state->clks = devm_kcalloc(dev, state->num_clks, sizeof(*state->clks),
 477                                   GFP_KERNEL);
 478
 479        if (!state->clks)
 480                return -ENOMEM;
 481
 482        for (i = 0; i < state->num_clks; i++)
 483                state->clks[i].id = mipi_csis_clk_id[i];
 484
 485        ret = devm_clk_bulk_get(dev, state->num_clks, state->clks);
 486        if (ret < 0)
 487                return ret;
 488
 489        state->wrap_clk = devm_clk_get(dev, "wrap");
 490        if (IS_ERR(state->wrap_clk))
 491                return PTR_ERR(state->wrap_clk);
 492
 493        /* Set clock rate */
 494        ret = clk_set_rate(state->wrap_clk, state->clk_frequency);
 495        if (ret < 0)
 496                dev_err(dev, "set rate=%d failed: %d\n", state->clk_frequency,
 497                        ret);
 498
 499        return ret;
 500}
 501
 502static void mipi_csis_start_stream(struct csi_state *state)
 503{
 504        mipi_csis_sw_reset(state);
 505        mipi_csis_set_params(state);
 506        mipi_csis_system_enable(state, true);
 507        mipi_csis_enable_interrupts(state, true);
 508}
 509
 510static void mipi_csis_stop_stream(struct csi_state *state)
 511{
 512        mipi_csis_enable_interrupts(state, false);
 513        mipi_csis_system_enable(state, false);
 514}
 515
 516static void mipi_csis_clear_counters(struct csi_state *state)
 517{
 518        unsigned long flags;
 519        unsigned int i;
 520
 521        spin_lock_irqsave(&state->slock, flags);
 522        for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
 523                state->events[i].counter = 0;
 524        spin_unlock_irqrestore(&state->slock, flags);
 525}
 526
 527static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
 528{
 529        int i = non_errors ? MIPI_CSIS_NUM_EVENTS : MIPI_CSIS_NUM_EVENTS - 4;
 530        struct device *dev = &state->pdev->dev;
 531        unsigned long flags;
 532
 533        spin_lock_irqsave(&state->slock, flags);
 534
 535        for (i--; i >= 0; i--) {
 536                if (state->events[i].counter > 0 || state->debug)
 537                        dev_info(dev, "%s events: %d\n", state->events[i].name,
 538                                 state->events[i].counter);
 539        }
 540        spin_unlock_irqrestore(&state->slock, flags);
 541}
 542
 543/*
 544 * V4L2 subdev operations
 545 */
 546static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable)
 547{
 548        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 549        int ret = 0;
 550
 551        if (enable) {
 552                mipi_csis_clear_counters(state);
 553                ret = pm_runtime_get_sync(&state->pdev->dev);
 554                if (ret < 0) {
 555                        pm_runtime_put_noidle(&state->pdev->dev);
 556                        return ret;
 557                }
 558                ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
 559                if (ret < 0)
 560                        return ret;
 561        }
 562
 563        mutex_lock(&state->lock);
 564        if (enable) {
 565                if (state->flags & ST_SUSPENDED) {
 566                        ret = -EBUSY;
 567                        goto unlock;
 568                }
 569
 570                mipi_csis_start_stream(state);
 571                ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
 572                if (ret < 0)
 573                        goto unlock;
 574
 575                mipi_csis_log_counters(state, true);
 576
 577                state->flags |= ST_STREAMING;
 578        } else {
 579                v4l2_subdev_call(state->src_sd, video, s_stream, 0);
 580                ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
 581                mipi_csis_stop_stream(state);
 582                state->flags &= ~ST_STREAMING;
 583                if (state->debug)
 584                        mipi_csis_log_counters(state, true);
 585        }
 586
 587unlock:
 588        mutex_unlock(&state->lock);
 589        if (!enable)
 590                pm_runtime_put(&state->pdev->dev);
 591
 592        return ret;
 593}
 594
 595static int mipi_csis_link_setup(struct media_entity *entity,
 596                                const struct media_pad *local_pad,
 597                                const struct media_pad *remote_pad, u32 flags)
 598{
 599        struct v4l2_subdev *mipi_sd = media_entity_to_v4l2_subdev(entity);
 600        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 601        struct v4l2_subdev *remote_sd;
 602        int ret = 0;
 603
 604        dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
 605                local_pad->entity->name);
 606
 607        remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
 608
 609        mutex_lock(&state->lock);
 610
 611        if (local_pad->flags & MEDIA_PAD_FL_SOURCE) {
 612                if (flags & MEDIA_LNK_FL_ENABLED) {
 613                        if (state->sink_linked) {
 614                                ret = -EBUSY;
 615                                goto out;
 616                        }
 617                        state->sink_linked = true;
 618                } else {
 619                        state->sink_linked = false;
 620                }
 621        } else {
 622                if (flags & MEDIA_LNK_FL_ENABLED) {
 623                        if (state->src_sd) {
 624                                ret = -EBUSY;
 625                                goto out;
 626                        }
 627                        state->src_sd = remote_sd;
 628                } else {
 629                        state->src_sd = NULL;
 630                }
 631        }
 632
 633out:
 634        mutex_unlock(&state->lock);
 635        return ret;
 636}
 637
 638static int mipi_csis_init_cfg(struct v4l2_subdev *mipi_sd,
 639                              struct v4l2_subdev_pad_config *cfg)
 640{
 641        struct v4l2_mbus_framefmt *mf;
 642        unsigned int i;
 643        int ret;
 644
 645        for (i = 0; i < CSIS_PADS_NUM; i++) {
 646                mf = v4l2_subdev_get_try_format(mipi_sd, cfg, i);
 647
 648                ret = imx_media_init_mbus_fmt(mf, MIPI_CSIS_DEF_PIX_HEIGHT,
 649                                              MIPI_CSIS_DEF_PIX_WIDTH, 0,
 650                                              V4L2_FIELD_NONE, NULL);
 651                if (ret < 0)
 652                        return ret;
 653        }
 654
 655        return 0;
 656}
 657
 658static struct csis_pix_format const *
 659mipi_csis_try_format(struct v4l2_subdev *mipi_sd, struct v4l2_mbus_framefmt *mf)
 660{
 661        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 662        struct csis_pix_format const *csis_fmt;
 663
 664        csis_fmt = find_csis_format(mf->code);
 665        if (!csis_fmt)
 666                csis_fmt = &mipi_csis_formats[0];
 667
 668        v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
 669                              csis_fmt->pix_width_alignment,
 670                              &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
 671                              0);
 672
 673        state->format_mbus.code = csis_fmt->code;
 674        state->format_mbus.width = mf->width;
 675        state->format_mbus.height = mf->height;
 676
 677        return csis_fmt;
 678}
 679
 680static struct v4l2_mbus_framefmt *
 681mipi_csis_get_format(struct csi_state *state,
 682                     struct v4l2_subdev_pad_config *cfg,
 683                     enum v4l2_subdev_format_whence which,
 684                     unsigned int pad)
 685{
 686        if (which == V4L2_SUBDEV_FORMAT_TRY)
 687                return v4l2_subdev_get_try_format(&state->mipi_sd, cfg, pad);
 688
 689        return &state->format_mbus;
 690}
 691
 692static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd,
 693                             struct v4l2_subdev_pad_config *cfg,
 694                             struct v4l2_subdev_format *sdformat)
 695{
 696        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 697        struct csis_pix_format const *csis_fmt;
 698        struct v4l2_mbus_framefmt *fmt;
 699
 700        if (sdformat->pad >= CSIS_PADS_NUM)
 701                return -EINVAL;
 702
 703        fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
 704
 705        mutex_lock(&state->lock);
 706        if (sdformat->pad == CSIS_PAD_SOURCE) {
 707                sdformat->format = *fmt;
 708                goto unlock;
 709        }
 710
 711        csis_fmt = mipi_csis_try_format(mipi_sd, &sdformat->format);
 712
 713        sdformat->format = *fmt;
 714
 715        if (csis_fmt && sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
 716                state->csis_fmt = csis_fmt;
 717        else
 718                cfg->try_fmt = sdformat->format;
 719
 720unlock:
 721        mutex_unlock(&state->lock);
 722
 723        return 0;
 724}
 725
 726static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd,
 727                             struct v4l2_subdev_pad_config *cfg,
 728                             struct v4l2_subdev_format *sdformat)
 729{
 730        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 731        struct v4l2_mbus_framefmt *fmt;
 732
 733        mutex_lock(&state->lock);
 734
 735        fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
 736
 737        sdformat->format = *fmt;
 738
 739        mutex_unlock(&state->lock);
 740
 741        return 0;
 742}
 743
 744static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd)
 745{
 746        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 747
 748        mutex_lock(&state->lock);
 749        mipi_csis_log_counters(state, true);
 750        if (state->debug && (state->flags & ST_POWERED))
 751                mipi_csis_dump_regs(state);
 752        mutex_unlock(&state->lock);
 753
 754        return 0;
 755}
 756
 757static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 758{
 759        struct csi_state *state = dev_id;
 760        unsigned long flags;
 761        unsigned int i;
 762        u32 status;
 763
 764        status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
 765
 766        spin_lock_irqsave(&state->slock, flags);
 767
 768        /* Update the event/error counters */
 769        if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) {
 770                for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
 771                        if (!(status & state->events[i].mask))
 772                                continue;
 773                        state->events[i].counter++;
 774                }
 775        }
 776        spin_unlock_irqrestore(&state->slock, flags);
 777
 778        mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
 779
 780        return IRQ_HANDLED;
 781}
 782
 783static int mipi_csis_registered(struct v4l2_subdev *mipi_sd)
 784{
 785        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 786
 787        state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
 788        state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
 789
 790        return media_entity_pads_init(&state->mipi_sd.entity, CSIS_PADS_NUM,
 791                                      state->pads);
 792}
 793
 794static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
 795        .log_status     = mipi_csis_log_status,
 796};
 797
 798static const struct media_entity_operations mipi_csis_entity_ops = {
 799        .link_setup     = mipi_csis_link_setup,
 800        .link_validate  = v4l2_subdev_link_validate,
 801};
 802
 803static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
 804        .s_stream       = mipi_csis_s_stream,
 805};
 806
 807static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
 808        .init_cfg               = mipi_csis_init_cfg,
 809        .get_fmt                = mipi_csis_get_fmt,
 810        .set_fmt                = mipi_csis_set_fmt,
 811};
 812
 813static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
 814        .core   = &mipi_csis_core_ops,
 815        .video  = &mipi_csis_video_ops,
 816        .pad    = &mipi_csis_pad_ops,
 817};
 818
 819static const struct v4l2_subdev_internal_ops mipi_csis_internal_ops = {
 820        .registered = mipi_csis_registered,
 821};
 822
 823static int mipi_csis_parse_dt(struct platform_device *pdev,
 824                              struct csi_state *state)
 825{
 826        struct device_node *node = pdev->dev.of_node;
 827
 828        if (of_property_read_u32(node, "clock-frequency",
 829                                 &state->clk_frequency))
 830                state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
 831
 832        /* Get MIPI PHY resets */
 833        state->mrst = devm_reset_control_get_exclusive(&pdev->dev, "mrst");
 834        if (IS_ERR(state->mrst))
 835                return PTR_ERR(state->mrst);
 836
 837        /* Get MIPI CSI-2 bus configuration from the endpoint node. */
 838        of_property_read_u32(node, "fsl,csis-hs-settle", &state->hs_settle);
 839
 840        return 0;
 841}
 842
 843static int mipi_csis_pm_resume(struct device *dev, bool runtime);
 844
 845static int mipi_csis_parse_endpoint(struct device *dev,
 846                                    struct v4l2_fwnode_endpoint *ep,
 847                                    struct v4l2_async_subdev *asd)
 848{
 849        struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
 850        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 851
 852        if (ep->bus_type != V4L2_MBUS_CSI2_DPHY) {
 853                dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
 854                return -EINVAL;
 855        }
 856
 857        state->bus = ep->bus.mipi_csi2;
 858
 859        dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
 860        dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
 861
 862        return 0;
 863}
 864
 865static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd,
 866                                 struct platform_device *pdev,
 867                                 const struct v4l2_subdev_ops *ops)
 868{
 869        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
 870        unsigned int sink_port = 0;
 871        int ret;
 872
 873        v4l2_subdev_init(mipi_sd, ops);
 874        mipi_sd->owner = THIS_MODULE;
 875        snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d",
 876                 CSIS_SUBDEV_NAME, state->index);
 877
 878        mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
 879        mipi_sd->ctrl_handler = NULL;
 880
 881        mipi_sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
 882        mipi_sd->entity.ops = &mipi_csis_entity_ops;
 883        mipi_sd->internal_ops = &mipi_csis_internal_ops;
 884
 885        mipi_sd->dev = &pdev->dev;
 886
 887        state->csis_fmt = &mipi_csis_formats[0];
 888        state->format_mbus.code = mipi_csis_formats[0].code;
 889        state->format_mbus.width = MIPI_CSIS_DEF_PIX_WIDTH;
 890        state->format_mbus.height = MIPI_CSIS_DEF_PIX_HEIGHT;
 891        state->format_mbus.field = V4L2_FIELD_NONE;
 892
 893        v4l2_set_subdevdata(mipi_sd, &pdev->dev);
 894
 895        ret = v4l2_async_register_fwnode_subdev(mipi_sd,
 896                                                sizeof(struct v4l2_async_subdev),
 897                                                &sink_port, 1,
 898                                                mipi_csis_parse_endpoint);
 899        if (ret < 0)
 900                dev_err(&pdev->dev, "async fwnode register failed: %d\n", ret);
 901
 902        return ret;
 903}
 904
 905static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
 906{
 907        struct csi_state *state = m->private;
 908
 909        return mipi_csis_dump_regs(state);
 910}
 911DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
 912
 913static int mipi_csis_debugfs_init(struct csi_state *state)
 914{
 915        struct dentry *d;
 916
 917        if (!debugfs_initialized())
 918                return -ENODEV;
 919
 920        state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
 921        if (!state->debugfs_root)
 922                return -ENOMEM;
 923
 924        d = debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
 925                                &state->debug);
 926        if (!d)
 927                goto remove_debugfs;
 928
 929        d = debugfs_create_file("dump_regs", 0600, state->debugfs_root,
 930                                state, &mipi_csis_dump_regs_fops);
 931        if (!d)
 932                goto remove_debugfs;
 933
 934        return 0;
 935
 936remove_debugfs:
 937        debugfs_remove_recursive(state->debugfs_root);
 938
 939        return -ENOMEM;
 940}
 941
 942static void mipi_csis_debugfs_exit(struct csi_state *state)
 943{
 944        debugfs_remove_recursive(state->debugfs_root);
 945}
 946
 947static int mipi_csis_probe(struct platform_device *pdev)
 948{
 949        struct device *dev = &pdev->dev;
 950        struct resource *mem_res;
 951        struct csi_state *state;
 952        int ret;
 953
 954        state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
 955        if (!state)
 956                return -ENOMEM;
 957
 958        spin_lock_init(&state->slock);
 959
 960        state->pdev = pdev;
 961        state->dev = dev;
 962
 963        ret = mipi_csis_parse_dt(pdev, state);
 964        if (ret < 0) {
 965                dev_err(dev, "Failed to parse device tree: %d\n", ret);
 966                return ret;
 967        }
 968
 969        mipi_csis_phy_init(state);
 970        mipi_csis_phy_reset(state);
 971
 972        mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 973        state->regs = devm_ioremap_resource(dev, mem_res);
 974        if (IS_ERR(state->regs))
 975                return PTR_ERR(state->regs);
 976
 977        state->irq = platform_get_irq(pdev, 0);
 978        if (state->irq < 0)
 979                return state->irq;
 980
 981        ret = mipi_csis_clk_get(state);
 982        if (ret < 0)
 983                return ret;
 984
 985        ret = mipi_csis_clk_enable(state);
 986        if (ret < 0) {
 987                dev_err(state->dev, "failed to enable clocks: %d\n", ret);
 988                return ret;
 989        }
 990
 991        ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler,
 992                               0, dev_name(dev), state);
 993        if (ret) {
 994                dev_err(dev, "Interrupt request failed\n");
 995                goto disable_clock;
 996        }
 997
 998        platform_set_drvdata(pdev, &state->mipi_sd);
 999
1000        mutex_init(&state->lock);
1001        ret = mipi_csis_subdev_init(&state->mipi_sd, pdev,
1002                                    &mipi_csis_subdev_ops);
1003        if (ret < 0)
1004                goto disable_clock;
1005
1006        memcpy(state->events, mipi_csis_events, sizeof(state->events));
1007
1008        mipi_csis_debugfs_init(state);
1009        pm_runtime_enable(dev);
1010        if (!pm_runtime_enabled(dev)) {
1011                ret = mipi_csis_pm_resume(dev, true);
1012                if (ret < 0)
1013                        goto unregister_all;
1014        }
1015
1016        dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
1017                 state->bus.num_data_lanes, state->hs_settle,
1018                 state->wrap_clk ? 1 : 0, state->clk_frequency);
1019
1020        return 0;
1021
1022unregister_all:
1023        mipi_csis_debugfs_exit(state);
1024        media_entity_cleanup(&state->mipi_sd.entity);
1025        v4l2_async_unregister_subdev(&state->mipi_sd);
1026disable_clock:
1027        mipi_csis_clk_disable(state);
1028        mutex_destroy(&state->lock);
1029
1030        return ret;
1031}
1032
1033static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1034{
1035        struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1036        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1037        int ret = 0;
1038
1039        mutex_lock(&state->lock);
1040        if (state->flags & ST_POWERED) {
1041                mipi_csis_stop_stream(state);
1042                ret = regulator_disable(state->mipi_phy_regulator);
1043                if (ret)
1044                        goto unlock;
1045                mipi_csis_clk_disable(state);
1046                state->flags &= ~ST_POWERED;
1047                if (!runtime)
1048                        state->flags |= ST_SUSPENDED;
1049        }
1050
1051unlock:
1052        mutex_unlock(&state->lock);
1053
1054        return ret ? -EAGAIN : 0;
1055}
1056
1057static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1058{
1059        struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
1060        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1061        int ret = 0;
1062
1063        mutex_lock(&state->lock);
1064        if (!runtime && !(state->flags & ST_SUSPENDED))
1065                goto unlock;
1066
1067        if (!(state->flags & ST_POWERED)) {
1068                ret = regulator_enable(state->mipi_phy_regulator);
1069                if (ret)
1070                        goto unlock;
1071
1072                state->flags |= ST_POWERED;
1073                mipi_csis_clk_enable(state);
1074        }
1075        if (state->flags & ST_STREAMING)
1076                mipi_csis_start_stream(state);
1077
1078        state->flags &= ~ST_SUSPENDED;
1079
1080unlock:
1081        mutex_unlock(&state->lock);
1082
1083        return ret ? -EAGAIN : 0;
1084}
1085
1086static int __maybe_unused mipi_csis_suspend(struct device *dev)
1087{
1088        return mipi_csis_pm_suspend(dev, false);
1089}
1090
1091static int __maybe_unused mipi_csis_resume(struct device *dev)
1092{
1093        return mipi_csis_pm_resume(dev, false);
1094}
1095
1096static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1097{
1098        return mipi_csis_pm_suspend(dev, true);
1099}
1100
1101static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1102{
1103        return mipi_csis_pm_resume(dev, true);
1104}
1105
1106static int mipi_csis_remove(struct platform_device *pdev)
1107{
1108        struct v4l2_subdev *mipi_sd = platform_get_drvdata(pdev);
1109        struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
1110
1111        mipi_csis_debugfs_exit(state);
1112        v4l2_async_unregister_subdev(&state->mipi_sd);
1113        v4l2_async_notifier_unregister(&state->subdev_notifier);
1114
1115        pm_runtime_disable(&pdev->dev);
1116        mipi_csis_pm_suspend(&pdev->dev, true);
1117        mipi_csis_clk_disable(state);
1118        media_entity_cleanup(&state->mipi_sd.entity);
1119        mutex_destroy(&state->lock);
1120        pm_runtime_set_suspended(&pdev->dev);
1121
1122        return 0;
1123}
1124
1125static const struct dev_pm_ops mipi_csis_pm_ops = {
1126        SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1127                           NULL)
1128        SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1129};
1130
1131static const struct of_device_id mipi_csis_of_match[] = {
1132        { .compatible = "fsl,imx7-mipi-csi2", },
1133        { /* sentinel */ },
1134};
1135MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1136
1137static struct platform_driver mipi_csis_driver = {
1138        .probe          = mipi_csis_probe,
1139        .remove         = mipi_csis_remove,
1140        .driver         = {
1141                .of_match_table = mipi_csis_of_match,
1142                .name           = CSIS_DRIVER_NAME,
1143                .pm             = &mipi_csis_pm_ops,
1144        },
1145};
1146
1147module_platform_driver(mipi_csis_driver);
1148
1149MODULE_DESCRIPTION("i.MX7 MIPI CSI-2 Receiver driver");
1150MODULE_LICENSE("GPL v2");
1151MODULE_ALIAS("platform:imx7-mipi-csi2");
1152