LXR linux/include/drm/i915

   1/*
   2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the
  14 * next paragraph) shall be included in all copies or substantial portions
  15 * of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24 *
  25 */
  26#ifndef _I915_DRM_H_
  27#define _I915_DRM_H_
  28
  29#include <drm/i915_pciids.h>
  30#include <uapi/drm/i915_drm.h>
  31
  32/* For use by IPS driver */
  33unsigned long i915_read_mch_val(void);
  34bool i915_gpu_raise(void);
  35bool i915_gpu_lower(void);
  36bool i915_gpu_busy(void);
  37bool i915_gpu_turbo_disable(void);
  38
  39/* Exported from arch/x86/kernel/early-quirks.c */
  40extern struct resource intel_graphics_stolen_res;
  41
  42/*
  43 * The Bridge device's PCI config space has information about the
  44 * fb aperture size and the amount of pre-reserved memory.
  45 * This is all handled in the intel-gtt.ko module. i915.ko only
  46 * cares about the vga bit for the vga rbiter.
  47 */
  48#define INTEL_GMCH_CTRL         0x52
  49#define INTEL_GMCH_VGA_DISABLE  (1 << 1)
  50#define SNB_GMCH_CTRL           0x50
  51#define    SNB_GMCH_GGMS_SHIFT  8 /* GTT Graphics Memory Size */
  52#define    SNB_GMCH_GGMS_MASK   0x3
  53#define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
  54#define    SNB_GMCH_GMS_MASK    0x1f
  55#define    BDW_GMCH_GGMS_SHIFT  6
  56#define    BDW_GMCH_GGMS_MASK   0x3
  57#define    BDW_GMCH_GMS_SHIFT   8
  58#define    BDW_GMCH_GMS_MASK    0xff
  59
  60#define I830_GMCH_CTRL                  0x52
  61
  62#define I830_GMCH_GMS_MASK              0x70
  63#define I830_GMCH_GMS_LOCAL             0x10
  64#define I830_GMCH_GMS_STOLEN_512        0x20
  65#define I830_GMCH_GMS_STOLEN_1024       0x30
  66#define I830_GMCH_GMS_STOLEN_8192       0x40
  67
  68#define I855_GMCH_GMS_MASK              0xF0
  69#define I855_GMCH_GMS_STOLEN_0M         0x0
  70#define I855_GMCH_GMS_STOLEN_1M         (0x1 << 4)
  71#define I855_GMCH_GMS_STOLEN_4M         (0x2 << 4)
  72#define I855_GMCH_GMS_STOLEN_8M         (0x3 << 4)
  73#define I855_GMCH_GMS_STOLEN_16M        (0x4 << 4)
  74#define I855_GMCH_GMS_STOLEN_32M        (0x5 << 4)
  75#define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  76#define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  77#define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
  78#define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
  79#define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
  80#define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
  81#define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
  82#define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
  83
  84#define I830_DRB3               0x63
  85#define I85X_DRB3               0x43
  86#define I865_TOUD               0xc4
  87
  88#define I830_ESMRAMC            0x91
  89#define I845_ESMRAMC            0x9e
  90#define I85X_ESMRAMC            0x61
  91#define    TSEG_ENABLE          (1 << 0)
  92#define    I830_TSEG_SIZE_512K  (0 << 1)
  93#define    I830_TSEG_SIZE_1M    (1 << 1)
  94#define    I845_TSEG_SIZE_MASK  (3 << 1)
  95#define    I845_TSEG_SIZE_512K  (2 << 1)
  96#define    I845_TSEG_SIZE_1M    (3 << 1)
  97
  98#define INTEL_BSM               0x5c
  99#define INTEL_GEN11_BSM_DW0     0xc0
 100#define INTEL_GEN11_BSM_DW1     0xc4
 101#define   INTEL_BSM_MASK        (-(1u << 20))
 102
 103enum port {
 104        PORT_NONE = -1,
 105
 106        PORT_A = 0,
 107        PORT_B,
 108        PORT_C,
 109        PORT_D,
 110        PORT_E,
 111        PORT_F,
 112        PORT_G,
 113        PORT_H,
 114        PORT_I,
 115
 116        I915_MAX_PORTS
 117};
 118
 119#define port_name(p) ((p) + 'A')
 120
 121#endif                          /* _I915_DRM_H_ */
 122