1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos4 clock controller. 7 */ 8 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 10#define _DT_BINDINGS_CLOCK_EXYNOS_4_H 11 12/* core clocks */ 13#define CLK_XXTI 1 14#define CLK_XUSBXTI 2 15#define CLK_FIN_PLL 3 16#define CLK_FOUT_APLL 4 17#define CLK_FOUT_MPLL 5 18#define CLK_FOUT_EPLL 6 19#define CLK_FOUT_VPLL 7 20#define CLK_SCLK_APLL 8 21#define CLK_SCLK_MPLL 9 22#define CLK_SCLK_EPLL 10 23#define CLK_SCLK_VPLL 11 24#define CLK_ARM_CLK 12 25#define CLK_ACLK200 13 26#define CLK_ACLK100 14 27#define CLK_ACLK160 15 28#define CLK_ACLK133 16 29#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 30#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 31#define CLK_MOUT_CORE 19 32#define CLK_MOUT_APLL 20 33#define CLK_SCLK_HDMIPHY 22 34#define CLK_OUT_DMC 23 35#define CLK_OUT_TOP 24 36#define CLK_OUT_LEFTBUS 25 37#define CLK_OUT_RIGHTBUS 26 38#define CLK_OUT_CPU 27 39 40/* gate for special clocks (sclk) */ 41#define CLK_SCLK_FIMC0 128 42#define CLK_SCLK_FIMC1 129 43#define CLK_SCLK_FIMC2 130 44#define CLK_SCLK_FIMC3 131 45#define CLK_SCLK_CAM0 132 46#define CLK_SCLK_CAM1 133 47#define CLK_SCLK_CSIS0 134 48#define CLK_SCLK_CSIS1 135 49#define CLK_SCLK_HDMI 136 50#define CLK_SCLK_MIXER 137 51#define CLK_SCLK_DAC 138 52#define CLK_SCLK_PIXEL 139 53#define CLK_SCLK_FIMD0 140 54#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 55#define CLK_SCLK_MDNIE_PWM0 142 56#define CLK_SCLK_MIPI0 143 57#define CLK_SCLK_AUDIO0 144 58#define CLK_SCLK_MMC0 145 59#define CLK_SCLK_MMC1 146 60#define CLK_SCLK_MMC2 147 61#define CLK_SCLK_MMC3 148 62#define CLK_SCLK_MMC4 149 63#define CLK_SCLK_SATA 150 /* Exynos4210 only */ 64#define CLK_SCLK_UART0 151 65#define CLK_SCLK_UART1 152 66#define CLK_SCLK_UART2 153 67#define CLK_SCLK_UART3 154 68#define CLK_SCLK_UART4 155 69#define CLK_SCLK_AUDIO1 156 70#define CLK_SCLK_AUDIO2 157 71#define CLK_SCLK_SPDIF 158 72#define CLK_SCLK_SPI0 159 73#define CLK_SCLK_SPI1 160 74#define CLK_SCLK_SPI2 161 75#define CLK_SCLK_SLIMBUS 162 76#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 77#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 78#define CLK_SCLK_PCM1 165 79#define CLK_SCLK_PCM2 166 80#define CLK_SCLK_I2S1 167 81#define CLK_SCLK_I2S2 168 82#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 83#define CLK_SCLK_MFC 170 84#define CLK_SCLK_PCM0 171 85#define CLK_SCLK_G3D 172 86#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 87#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 88#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 89#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 90#define CLK_SCLK_FIMG2D 177 91 92/* gate clocks */ 93#define CLK_SSS 255 94#define CLK_FIMC0 256 95#define CLK_FIMC1 257 96#define CLK_FIMC2 258 97#define CLK_FIMC3 259 98#define CLK_CSIS0 260 99#define CLK_CSIS1 261 100#define CLK_JPEG 262 101#define CLK_SMMU_FIMC0 263 102#define CLK_SMMU_FIMC1 264 103#define CLK_SMMU_FIMC2 265 104#define CLK_SMMU_FIMC3 266 105#define CLK_SMMU_JPEG 267 106#define CLK_VP 268 107#define CLK_MIXER 269 108#define CLK_TVENC 270 /* Exynos4210 only */ 109#define CLK_HDMI 271 110#define CLK_SMMU_TV 272 111#define CLK_MFC 273 112#define CLK_SMMU_MFCL 274 113#define CLK_SMMU_MFCR 275 114#define CLK_G3D 276 115#define CLK_G2D 277 116#define CLK_ROTATOR 278 117#define CLK_MDMA 279 118#define CLK_SMMU_G2D 280 119#define CLK_SMMU_ROTATOR 281 120#define CLK_SMMU_MDMA 282 121#define CLK_FIMD0 283 122#define CLK_MIE0 284 123#define CLK_MDNIE0 285 /* Exynos4412 only */ 124#define CLK_DSIM0 286 125#define CLK_SMMU_FIMD0 287 126#define CLK_FIMD1 288 /* Exynos4210 only */ 127#define CLK_MIE1 289 /* Exynos4210 only */ 128#define CLK_DSIM1 290 /* Exynos4210 only */ 129#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 130#define CLK_PDMA0 292 131#define CLK_PDMA1 293 132#define CLK_PCIE_PHY 294 133#define CLK_SATA_PHY 295 /* Exynos4210 only */ 134#define CLK_TSI 296 135#define CLK_SDMMC0 297 136#define CLK_SDMMC1 298 137#define CLK_SDMMC2 299 138#define CLK_SDMMC3 300 139#define CLK_SDMMC4 301 140#define CLK_SATA 302 /* Exynos4210 only */ 141#define CLK_SROMC 303 142#define CLK_USB_HOST 304 143#define CLK_USB_DEVICE 305 144#define CLK_PCIE 306 145#define CLK_ONENAND 307 146#define CLK_NFCON 308 147#define CLK_SMMU_PCIE 309 148#define CLK_GPS 310 149#define CLK_SMMU_GPS 311 150#define CLK_UART0 312 151#define CLK_UART1 313 152#define CLK_UART2 314 153#define CLK_UART3 315 154#define CLK_UART4 316 155#define CLK_I2C0 317 156#define CLK_I2C1 318 157#define CLK_I2C2 319 158#define CLK_I2C3 320 159#define CLK_I2C4 321 160#define CLK_I2C5 322 161#define CLK_I2C6 323 162#define CLK_I2C7 324 163#define CLK_I2C_HDMI 325 164#define CLK_TSADC 326 165#define CLK_SPI0 327 166#define CLK_SPI1 328 167#define CLK_SPI2 329 168#define CLK_I2S1 330 169#define CLK_I2S2 331 170#define CLK_PCM0 332 171#define CLK_I2S0 333 172#define CLK_PCM1 334 173#define CLK_PCM2 335 174#define CLK_PWM 336 175#define CLK_SLIMBUS 337 176#define CLK_SPDIF 338 177#define CLK_AC97 339 178#define CLK_MODEMIF 340 179#define CLK_CHIPID 341 180#define CLK_SYSREG 342 181#define CLK_HDMI_CEC 343 182#define CLK_MCT 344 183#define CLK_WDT 345 184#define CLK_RTC 346 185#define CLK_KEYIF 347 186#define CLK_AUDSS 348 187#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 188#define CLK_PIXELASYNCM0 351 189#define CLK_PIXELASYNCM1 352 190#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ 191#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 192#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 193#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 194#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 195#define CLK_TMU_APBIF 383 196 197/* mux clocks */ 198#define CLK_MOUT_FIMC0 384 199#define CLK_MOUT_FIMC1 385 200#define CLK_MOUT_FIMC2 386 201#define CLK_MOUT_FIMC3 387 202#define CLK_MOUT_CAM0 388 203#define CLK_MOUT_CAM1 389 204#define CLK_MOUT_CSIS0 390 205#define CLK_MOUT_CSIS1 391 206#define CLK_MOUT_G3D0 392 207#define CLK_MOUT_G3D1 393 208#define CLK_MOUT_G3D 394 209#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 210#define CLK_MOUT_HDMI 396 211#define CLK_MOUT_MIXER 397 212 213/* gate clocks - ppmu */ 214#define CLK_PPMULEFT 400 215#define CLK_PPMURIGHT 401 216#define CLK_PPMUCAMIF 402 217#define CLK_PPMUTV 403 218#define CLK_PPMUMFC_L 404 219#define CLK_PPMUMFC_R 405 220#define CLK_PPMUG3D 406 221#define CLK_PPMUIMAGE 407 222#define CLK_PPMULCD0 408 223#define CLK_PPMULCD1 409 /* Exynos4210 only */ 224#define CLK_PPMUFILE 410 225#define CLK_PPMUGPS 411 226#define CLK_PPMUDMC0 412 227#define CLK_PPMUDMC1 413 228#define CLK_PPMUCPU 414 229#define CLK_PPMUACP 415 230 231/* div clocks */ 232#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 233#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 234#define CLK_DIV_ACP 456 235#define CLK_DIV_DMC 457 236#define CLK_DIV_C2C 458 /* Exynos4x12 only */ 237#define CLK_DIV_GDL 459 238#define CLK_DIV_GDR 460 239 240/* must be greater than maximal clock id */ 241#define CLK_NR_CLKS 461 242 243/* Exynos4x12 ISP clocks */ 244#define CLK_ISP_FIMC_ISP 1 245#define CLK_ISP_FIMC_DRC 2 246#define CLK_ISP_FIMC_FD 3 247#define CLK_ISP_FIMC_LITE0 4 248#define CLK_ISP_FIMC_LITE1 5 249#define CLK_ISP_MCUISP 6 250#define CLK_ISP_GICISP 7 251#define CLK_ISP_SMMU_ISP 8 252#define CLK_ISP_SMMU_DRC 9 253#define CLK_ISP_SMMU_FD 10 254#define CLK_ISP_SMMU_LITE0 11 255#define CLK_ISP_SMMU_LITE1 12 256#define CLK_ISP_PPMUISPMX 13 257#define CLK_ISP_PPMUISPX 14 258#define CLK_ISP_MCUCTL_ISP 15 259#define CLK_ISP_MPWM_ISP 16 260#define CLK_ISP_I2C0_ISP 17 261#define CLK_ISP_I2C1_ISP 18 262#define CLK_ISP_MTCADC_ISP 19 263#define CLK_ISP_PWM_ISP 20 264#define CLK_ISP_WDT_ISP 21 265#define CLK_ISP_UART_ISP 22 266#define CLK_ISP_ASYNCAXIM 23 267#define CLK_ISP_SMMU_ISPCX 24 268#define CLK_ISP_SPI0_ISP 25 269#define CLK_ISP_SPI1_ISP 26 270 271#define CLK_ISP_DIV_ISP0 27 272#define CLK_ISP_DIV_ISP1 28 273#define CLK_ISP_DIV_MCUISP0 29 274#define CLK_ISP_DIV_MCUISP1 30 275 276#define CLK_NR_ISP_CLKS 31 277 278#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 279