1
2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
5
6#include <linux/types.h>
7#include <uapi/asm/cputable.h>
8#include <asm/asm-const.h>
9
10#ifndef __ASSEMBLY__
11
12
13
14
15struct cpu_spec;
16
17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
18typedef void (*cpu_restore_t)(void);
19
20enum powerpc_oprofile_type {
21 PPC_OPROFILE_INVALID = 0,
22 PPC_OPROFILE_RS64 = 1,
23 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_G4 = 3,
25 PPC_OPROFILE_FSL_EMB = 4,
26 PPC_OPROFILE_CELL = 5,
27 PPC_OPROFILE_PA6T = 6,
28};
29
30enum powerpc_pmc_type {
31 PPC_PMC_DEFAULT = 0,
32 PPC_PMC_IBM = 1,
33 PPC_PMC_PA6T = 2,
34 PPC_PMC_G4 = 3,
35};
36
37struct pt_regs;
38
39extern int machine_check_generic(struct pt_regs *regs);
40extern int machine_check_4xx(struct pt_regs *regs);
41extern int machine_check_440A(struct pt_regs *regs);
42extern int machine_check_e500mc(struct pt_regs *regs);
43extern int machine_check_e500(struct pt_regs *regs);
44extern int machine_check_e200(struct pt_regs *regs);
45extern int machine_check_47x(struct pt_regs *regs);
46int machine_check_8xx(struct pt_regs *regs);
47int machine_check_83xx(struct pt_regs *regs);
48
49extern void cpu_down_flush_e500v2(void);
50extern void cpu_down_flush_e500mc(void);
51extern void cpu_down_flush_e5500(void);
52extern void cpu_down_flush_e6500(void);
53
54
55struct cpu_spec {
56
57 unsigned int pvr_mask;
58 unsigned int pvr_value;
59
60 char *cpu_name;
61 unsigned long cpu_features;
62 unsigned int cpu_user_features;
63 unsigned int cpu_user_features2;
64 unsigned int mmu_features;
65
66
67 unsigned int icache_bsize;
68 unsigned int dcache_bsize;
69
70
71 void (*cpu_down_flush)(void);
72
73
74 unsigned int num_pmcs;
75 enum powerpc_pmc_type pmc_type;
76
77
78
79
80 cpu_setup_t cpu_setup;
81
82 cpu_restore_t cpu_restore;
83
84
85 char *oprofile_cpu_type;
86
87
88 enum powerpc_oprofile_type oprofile_type;
89
90
91 unsigned long oprofile_mmcra_sihv;
92 unsigned long oprofile_mmcra_sipr;
93
94
95 unsigned long oprofile_mmcra_clear;
96
97
98 char *platform;
99
100
101
102
103 int (*machine_check)(struct pt_regs *regs);
104
105
106
107
108
109 long (*machine_check_early)(struct pt_regs *regs);
110};
111
112extern struct cpu_spec *cur_cpu_spec;
113
114extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
115
116extern void set_cur_cpu_spec(struct cpu_spec *s);
117extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
118extern void identify_cpu_name(unsigned int pvr);
119extern void do_feature_fixups(unsigned long value, void *fixup_start,
120 void *fixup_end);
121
122extern const char *powerpc_base_platform;
123
124#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
125extern void cpu_feature_keys_init(void);
126#else
127static inline void cpu_feature_keys_init(void) { }
128#endif
129
130#endif
131
132
133
134
135#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
136#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
137#define CPU_FTR_DBELL ASM_CONST(0x00000004)
138#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
139#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
140#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
141#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
142#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
143#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
144#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
145
146
147#ifdef CONFIG_PPC32
148#define CPU_FTR_L2CR ASM_CONST(0x00002000)
149#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
150#define CPU_FTR_TAU ASM_CONST(0x00008000)
151#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
152#define CPU_FTR_L3CR ASM_CONST(0x00040000)
153#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
154#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
155#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
156#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
157#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
159#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
160#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
161#define CPU_FTR_SPE ASM_CONST(0x10000000)
162#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
163#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
164
165#else
166
167#define CPU_FTR_PPC_LE (0)
168#endif
169
170
171
172
173
174#ifdef __powerpc64__
175#define LONG_ASM_CONST(x) ASM_CONST(x)
176#else
177#define LONG_ASM_CONST(x) 0
178#endif
179
180#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
181#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
182#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
183#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
184#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
185#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
186#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
187#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
188#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
189#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
190#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
191#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
192#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
194#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
195#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
196#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
197#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
198#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
199#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
200#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
201#define CPU_FTR_PKEY LONG_ASM_CONST(0x0000000400000000)
202#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
203#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
204#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
205#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
206#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
207#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
208#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
209#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
210#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
211#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
212#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
213#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
214#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
215
216#ifndef __ASSEMBLY__
217
218#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
219
220#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
221
222
223
224
225#ifdef CONFIG_ALTIVEC
226#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
227#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
228#else
229#define CPU_FTR_ALTIVEC_COMP 0
230#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
231#endif
232
233
234
235
236#ifdef CONFIG_VSX
237#define CPU_FTR_VSX_COMP CPU_FTR_VSX
238#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
239#else
240#define CPU_FTR_VSX_COMP 0
241#define PPC_FEATURE_HAS_VSX_COMP 0
242#endif
243
244
245
246
247#ifdef CONFIG_SPE
248#define CPU_FTR_SPE_COMP CPU_FTR_SPE
249#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
250#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
251#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
252#else
253#define CPU_FTR_SPE_COMP 0
254#define PPC_FEATURE_HAS_SPE_COMP 0
255#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
256#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
257#endif
258
259
260#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
261#define CPU_FTR_TM_COMP CPU_FTR_TM
262#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
263#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
264#else
265#define CPU_FTR_TM_COMP 0
266#define PPC_FEATURE2_HTM_COMP 0
267#define PPC_FEATURE2_HTM_NOSC_COMP 0
268#endif
269
270
271
272
273
274
275#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
276 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
277 || defined(CONFIG_PPC_MPC52xx)
278#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
279#else
280#define CPU_FTR_COMMON 0
281#endif
282
283
284
285
286#ifndef CONFIG_BDI_SWITCH
287#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
288#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
289#else
290#define CPU_FTR_MAYBE_CAN_DOZE 0
291#define CPU_FTR_MAYBE_CAN_NAP 0
292#endif
293
294#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \
295 CPU_FTR_COHERENT_ICACHE)
296#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
298#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
299#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
300 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
302#define CPU_FTRS_740 (CPU_FTR_COMMON | \
303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
304 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
305 CPU_FTR_PPC_LE)
306#define CPU_FTRS_750 (CPU_FTR_COMMON | \
307 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
308 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
309 CPU_FTR_PPC_LE)
310#define CPU_FTRS_750CL (CPU_FTRS_750)
311#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
312#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
313#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
314#define CPU_FTRS_750GX (CPU_FTRS_750FX)
315#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
316 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
317 CPU_FTR_ALTIVEC_COMP | \
318 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
319#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
320 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
321 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
323#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
324 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
325 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
326 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
327#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
330 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
331 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
332#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
333 CPU_FTR_NEED_PAIRED_STWCX | \
334 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
335 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
336 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
337#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
338 CPU_FTR_NEED_PAIRED_STWCX | \
339 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
340 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
341#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
342 CPU_FTR_NEED_PAIRED_STWCX | \
343 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
344 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
345 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
346 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
347#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
348 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
349 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
350 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
351#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
352 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
353 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
354 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
355 CPU_FTR_NEED_PAIRED_STWCX)
356#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
357 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
358 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
359 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
360#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
361 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
362 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
363 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
364#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
365 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
366 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
367 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
368#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
369#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
370 CPU_FTR_MAYBE_CAN_NAP)
371#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
372 CPU_FTR_MAYBE_CAN_NAP | \
373 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
374#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
375 CPU_FTR_MAYBE_CAN_NAP | \
376 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
377#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
378#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
379#define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
380#define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
381#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
382 CPU_FTR_INDEXED_DCR)
383#define CPU_FTRS_47X (CPU_FTRS_440x6)
384#define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
385 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
386 CPU_FTR_NOEXECUTE | \
387 CPU_FTR_DEBUG_LVL_EXC)
388#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
389 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
390 CPU_FTR_NOEXECUTE)
391#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
392 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
393 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
394#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
395 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
396 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
397
398
399
400
401#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
402 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
403 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
404 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
405#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
406 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
407 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
408 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
409 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
410#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
411
412
413#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
414 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
415 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
416 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
417 CPU_FTR_HVMODE | CPU_FTR_DABRX)
418#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
419 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
420 CPU_FTR_MMCRA | CPU_FTR_SMT | \
421 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
422 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
423#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
424 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
425 CPU_FTR_MMCRA | CPU_FTR_SMT | \
426 CPU_FTR_COHERENT_ICACHE | \
427 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
428 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
429 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
430 CPU_FTR_DABRX)
431#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
432 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
433 CPU_FTR_MMCRA | CPU_FTR_SMT | \
434 CPU_FTR_COHERENT_ICACHE | \
435 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
436 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
437 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
438 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
439 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)
440#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
441 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
442 CPU_FTR_MMCRA | CPU_FTR_SMT | \
443 CPU_FTR_COHERENT_ICACHE | \
444 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
445 CPU_FTR_DSCR | CPU_FTR_SAO | \
446 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
447 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
448 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
449 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)
450#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
451#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
452 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
453 CPU_FTR_MMCRA | CPU_FTR_SMT | \
454 CPU_FTR_COHERENT_ICACHE | \
455 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
456 CPU_FTR_DSCR | CPU_FTR_SAO | \
457 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
458 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
459 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
460 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
461 CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
462#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
463#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
464#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
465 CPU_FTR_P9_TM_HV_ASSIST | \
466 CPU_FTR_P9_TM_XER_SO_BUG)
467#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
468 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
469 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
470 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
471 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
472#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
473 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
474 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
475#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
476
477#ifdef __powerpc64__
478#ifdef CONFIG_PPC_BOOK3E
479#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
480#else
481#ifdef CONFIG_CPU_LITTLE_ENDIAN
482#define CPU_FTRS_POSSIBLE \
483 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
484 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
485 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
486#else
487#define CPU_FTRS_POSSIBLE \
488 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
489 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
490 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
491 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
492 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
493#endif
494#endif
495#else
496enum {
497 CPU_FTRS_POSSIBLE =
498#ifdef CONFIG_PPC_BOOK3S_601
499 CPU_FTRS_PPC601 |
500#elif defined(CONFIG_PPC_BOOK3S_32)
501 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
502 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
503 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
504 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
505 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
506 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
507 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
508 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
509 CPU_FTRS_CLASSIC32 |
510#else
511 CPU_FTRS_GENERIC_32 |
512#endif
513#ifdef CONFIG_PPC_8xx
514 CPU_FTRS_8XX |
515#endif
516#ifdef CONFIG_40x
517 CPU_FTRS_40X |
518#endif
519#ifdef CONFIG_44x
520 CPU_FTRS_44X | CPU_FTRS_440x6 |
521#endif
522#ifdef CONFIG_PPC_47x
523 CPU_FTRS_47X | CPU_FTR_476_DD2 |
524#endif
525#ifdef CONFIG_E200
526 CPU_FTRS_E200 |
527#endif
528#ifdef CONFIG_E500
529 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
530#endif
531#ifdef CONFIG_PPC_E500MC
532 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
533#endif
534 0,
535};
536#endif
537
538#ifdef __powerpc64__
539#ifdef CONFIG_PPC_BOOK3E
540#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
541#else
542
543#ifdef CONFIG_PPC_DT_CPU_FTRS
544#define CPU_FTRS_DT_CPU_BASE \
545 (CPU_FTR_LWSYNC | \
546 CPU_FTR_FPU_UNAVAILABLE | \
547 CPU_FTR_NODSISRALIGN | \
548 CPU_FTR_NOEXECUTE | \
549 CPU_FTR_COHERENT_ICACHE | \
550 CPU_FTR_STCX_CHECKS_ADDRESS | \
551 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
552 CPU_FTR_DAWR | \
553 CPU_FTR_ARCH_206 | \
554 CPU_FTR_ARCH_207S)
555#else
556#define CPU_FTRS_DT_CPU_BASE (~0ul)
557#endif
558
559#ifdef CONFIG_CPU_LITTLE_ENDIAN
560#define CPU_FTRS_ALWAYS \
561 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
562 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
563 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
564#else
565#define CPU_FTRS_ALWAYS \
566 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
567 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
568 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
569 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
570 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
571#endif
572#endif
573#else
574enum {
575 CPU_FTRS_ALWAYS =
576#ifdef CONFIG_PPC_BOOK3S_601
577 CPU_FTRS_PPC601 &
578#elif defined(CONFIG_PPC_BOOK3S_32)
579 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
580 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
581 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
582 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
583 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
584 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
585 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
586 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
587 CPU_FTRS_CLASSIC32 &
588#else
589 CPU_FTRS_GENERIC_32 &
590#endif
591#ifdef CONFIG_PPC_8xx
592 CPU_FTRS_8XX &
593#endif
594#ifdef CONFIG_40x
595 CPU_FTRS_40X &
596#endif
597#ifdef CONFIG_44x
598 CPU_FTRS_44X & CPU_FTRS_440x6 &
599#endif
600#ifdef CONFIG_E200
601 CPU_FTRS_E200 &
602#endif
603#ifdef CONFIG_E500
604 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
605#endif
606#ifdef CONFIG_PPC_E500MC
607 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
608#endif
609 ~CPU_FTR_EMB_HV &
610 CPU_FTRS_POSSIBLE,
611};
612#endif
613
614#define HBP_NUM 1
615
616#endif
617
618#endif
619
