LXR linux/arch/powerpc/include/asm/xive.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright 2016,2017 IBM Corporation.
   4 */
   5#ifndef _ASM_POWERPC_XIVE_H
   6#define _ASM_POWERPC_XIVE_H
   7
   8#define XIVE_INVALID_VP 0xffffffff
   9
  10#ifdef CONFIG_PPC_XIVE
  11
  12/*
  13 * Thread Interrupt Management Area (TIMA)
  14 *
  15 * This is a global MMIO region divided in 4 pages of varying access
  16 * permissions, providing access to per-cpu interrupt management
  17 * functions. It always identifies the CPU doing the access based
  18 * on the PowerBus initiator ID, thus we always access via the
  19 * same offset regardless of where the code is executing
  20 */
  21extern void __iomem *xive_tima;
  22extern unsigned long xive_tima_os;
  23
  24/*
  25 * Offset in the TM area of our current execution level (provided by
  26 * the backend)
  27 */
  28extern u32 xive_tima_offset;
  29
  30/*
  31 * Per-irq data (irq_get_handler_data for normal IRQs), IPIs
  32 * have it stored in the xive_cpu structure. We also cache
  33 * for normal interrupts the current target CPU.
  34 *
  35 * This structure is setup by the backend for each interrupt.
  36 */
  37struct xive_irq_data {
  38        u64 flags;
  39        u64 eoi_page;
  40        void __iomem *eoi_mmio;
  41        u64 trig_page;
  42        void __iomem *trig_mmio;
  43        u32 esb_shift;
  44        int src_chip;
  45        u32 hw_irq;
  46
  47        /* Setup/used by frontend */
  48        int target;
  49        /*
  50         * saved_p means that there is a queue entry for this interrupt
  51         * in some CPU's queue (not including guest vcpu queues), even
  52         * if P is not set in the source ESB.
  53         * stale_p means that there is no queue entry for this interrupt
  54         * in some CPU's queue, even if P is set in the source ESB.
  55         */
  56        bool saved_p;
  57        bool stale_p;
  58};
  59#define XIVE_IRQ_FLAG_STORE_EOI 0x01
  60#define XIVE_IRQ_FLAG_LSI       0x02
  61#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
  62#define XIVE_IRQ_FLAG_MASK_FW   0x08
  63#define XIVE_IRQ_FLAG_EOI_FW    0x10
  64#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
  65
  66/* Special flag set by KVM for excalation interrupts */
  67#define XIVE_IRQ_NO_EOI         0x80
  68
  69#define XIVE_INVALID_CHIP_ID    -1
  70
  71/* A queue tracking structure in a CPU */
  72struct xive_q {
  73        __be32                  *qpage;
  74        u32                     msk;
  75        u32                     idx;
  76        u32                     toggle;
  77        u64                     eoi_phys;
  78        u32                     esc_irq;
  79        atomic_t                count;
  80        atomic_t                pending_count;
  81        u64                     guest_qaddr;
  82        u32                     guest_qshift;
  83};
  84
  85/* Global enable flags for the XIVE support */
  86extern bool __xive_enabled;
  87
  88static inline bool xive_enabled(void) { return __xive_enabled; }
  89
  90extern bool xive_spapr_init(void);
  91extern bool xive_native_init(void);
  92extern void xive_smp_probe(void);
  93extern int  xive_smp_prepare_cpu(unsigned int cpu);
  94extern void xive_smp_setup_cpu(void);
  95extern void xive_smp_disable_cpu(void);
  96extern void xive_teardown_cpu(void);
  97extern void xive_shutdown(void);
  98extern void xive_flush_interrupt(void);
  99
 100/* xmon hook */
 101extern void xmon_xive_do_dump(int cpu);
 102extern int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d);
 103
 104/* APIs used by KVM */
 105extern u32 xive_native_default_eq_shift(void);
 106extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
 107extern void xive_native_free_vp_block(u32 vp_base);
 108extern int xive_native_populate_irq_data(u32 hw_irq,
 109                                         struct xive_irq_data *data);
 110extern void xive_cleanup_irq_data(struct xive_irq_data *xd);
 111extern u32 xive_native_alloc_irq(void);
 112extern void xive_native_free_irq(u32 irq);
 113extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
 114
 115extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
 116                                       __be32 *qpage, u32 order, bool can_escalate);
 117extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
 118
 119extern void xive_native_sync_source(u32 hw_irq);
 120extern void xive_native_sync_queue(u32 hw_irq);
 121extern bool is_xive_irq(struct irq_chip *chip);
 122extern int xive_native_enable_vp(u32 vp_id, bool single_escalation);
 123extern int xive_native_disable_vp(u32 vp_id);
 124extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
 125extern bool xive_native_has_single_escalation(void);
 126
 127extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
 128                                      u64 *out_qpage,
 129                                      u64 *out_qsize,
 130                                      u64 *out_qeoi_page,
 131                                      u32 *out_escalate_irq,
 132                                      u64 *out_qflags);
 133
 134extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
 135                                       u32 *qindex);
 136extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
 137                                       u32 qindex);
 138extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
 139extern bool xive_native_has_queue_state_support(void);
 140
 141#else
 142
 143static inline bool xive_enabled(void) { return false; }
 144
 145static inline bool xive_spapr_init(void) { return false; }
 146static inline bool xive_native_init(void) { return false; }
 147static inline void xive_smp_probe(void) { }
 148static inline int  xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
 149static inline void xive_smp_setup_cpu(void) { }
 150static inline void xive_smp_disable_cpu(void) { }
 151static inline void xive_kexec_teardown_cpu(int secondary) { }
 152static inline void xive_shutdown(void) { }
 153static inline void xive_flush_interrupt(void) { }
 154
 155static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
 156static inline void xive_native_free_vp_block(u32 vp_base) { }
 157
 158#endif
 159
 160#endif /* _ASM_POWERPC_XIVE_H */
 161