linux/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * SH7203 and SH7263 Setup
   4 *
   5 *  Copyright (C) 2007 - 2009  Paul Mundt
   6 */
   7#include <linux/platform_device.h>
   8#include <linux/init.h>
   9#include <linux/serial.h>
  10#include <linux/serial_sci.h>
  11#include <linux/sh_timer.h>
  12#include <linux/io.h>
  13
  14enum {
  15        UNUSED = 0,
  16
  17        /* interrupt sources */
  18        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  19        PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  20        DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
  21        USB, LCDC, CMT0, CMT1, BSC, WDT,
  22
  23        MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
  24        MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
  25
  26        ADC_ADI,
  27
  28        IIC30, IIC31, IIC32, IIC33,
  29        SCIF0, SCIF1, SCIF2, SCIF3,
  30
  31        SSU0, SSU1,
  32
  33        SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
  34
  35        /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
  36        ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
  37        SRC, IEBI,
  38
  39        /* interrupt groups */
  40        PINT,
  41};
  42
  43static struct intc_vect vectors[] __initdata = {
  44        INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  45        INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  46        INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  47        INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  48        INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  49        INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  50        INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  51        INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  52        INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
  53        INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
  54        INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
  55        INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
  56        INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
  57        INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
  58        INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
  59        INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
  60        INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
  61        INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
  62        INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
  63        INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
  64        INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
  65        INTC_IRQ(MTU0_VEF, 150),
  66        INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
  67        INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
  68        INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
  69        INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
  70        INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
  71        INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
  72        INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
  73        INTC_IRQ(MTU2_TCI3V, 165),
  74        INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
  75        INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
  76        INTC_IRQ(MTU2_TCI4V, 170),
  77        INTC_IRQ(ADC_ADI, 171),
  78        INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
  79        INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
  80        INTC_IRQ(IIC30, 176),
  81        INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
  82        INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
  83        INTC_IRQ(IIC31, 181),
  84        INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
  85        INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
  86        INTC_IRQ(IIC32, 186),
  87        INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
  88        INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
  89        INTC_IRQ(IIC33, 191),
  90        INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
  91        INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
  92        INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
  93        INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
  94        INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
  95        INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
  96        INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
  97        INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
  98        INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
  99        INTC_IRQ(SSU0, 210),
 100        INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
 101        INTC_IRQ(SSU1, 213),
 102        INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
 103        INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
 104        INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
 105        INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
 106        INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
 107        INTC_IRQ(RTC, 233),
 108        INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
 109        INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
 110        INTC_IRQ(RCAN0, 238),
 111        INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
 112        INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
 113        INTC_IRQ(RCAN1, 243),
 114
 115        /* SH7263-specific trash */
 116#ifdef CONFIG_CPU_SUBTYPE_SH7263
 117        INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
 118        INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
 119        INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
 120
 121        INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
 122        INTC_IRQ(SDHI, 230),
 123
 124        INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
 125        INTC_IRQ(SRC, 246),
 126
 127        INTC_IRQ(IEBI, 247),
 128#endif
 129};
 130
 131static struct intc_group groups[] __initdata = {
 132        INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 133                   PINT4, PINT5, PINT6, PINT7),
 134};
 135
 136static struct intc_prio_reg prio_registers[] __initdata = {
 137        { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 138        { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 139        { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
 140        { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
 141        { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
 142        { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
 143        { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
 144        { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
 145                                              MTU2_VU } },
 146        { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
 147                                              MTU2_TCI4V } },
 148        { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
 149        { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
 150        { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
 151#ifdef CONFIG_CPU_SUBTYPE_SH7203
 152        { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
 153                                              SSI3_SSII, 0 } },
 154        { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
 155        { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
 156#else
 157        { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
 158                                              SSI3_SSII, ROMDEC } },
 159        { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
 160        { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
 161#endif
 162};
 163
 164static struct intc_mask_reg mask_registers[] __initdata = {
 165        { 0xfffe0808, 0, 16, /* PINTER */
 166          { 0, 0, 0, 0, 0, 0, 0, 0,
 167            PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 168};
 169
 170static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
 171                         mask_registers, prio_registers, NULL);
 172
 173static struct plat_sci_port scif0_platform_data = {
 174        .scscr          = SCSCR_REIE,
 175        .type           = PORT_SCIF,
 176        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 177};
 178
 179static struct resource scif0_resources[] = {
 180        DEFINE_RES_MEM(0xfffe8000, 0x100),
 181        DEFINE_RES_IRQ(192),
 182};
 183
 184static struct platform_device scif0_device = {
 185        .name           = "sh-sci",
 186        .id             = 0,
 187        .resource       = scif0_resources,
 188        .num_resources  = ARRAY_SIZE(scif0_resources),
 189        .dev            = {
 190                .platform_data  = &scif0_platform_data,
 191        },
 192};
 193
 194static struct plat_sci_port scif1_platform_data = {
 195        .scscr          = SCSCR_REIE,
 196        .type           = PORT_SCIF,
 197        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 198};
 199
 200static struct resource scif1_resources[] = {
 201        DEFINE_RES_MEM(0xfffe8800, 0x100),
 202        DEFINE_RES_IRQ(196),
 203};
 204
 205static struct platform_device scif1_device = {
 206        .name           = "sh-sci",
 207        .id             = 1,
 208        .resource       = scif1_resources,
 209        .num_resources  = ARRAY_SIZE(scif1_resources),
 210        .dev            = {
 211                .platform_data  = &scif1_platform_data,
 212        },
 213};
 214
 215static struct plat_sci_port scif2_platform_data = {
 216        .scscr          = SCSCR_REIE,
 217        .type           = PORT_SCIF,
 218        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 219};
 220
 221static struct resource scif2_resources[] = {
 222        DEFINE_RES_MEM(0xfffe9000, 0x100),
 223        DEFINE_RES_IRQ(200),
 224};
 225
 226static struct platform_device scif2_device = {
 227        .name           = "sh-sci",
 228        .id             = 2,
 229        .resource       = scif2_resources,
 230        .num_resources  = ARRAY_SIZE(scif2_resources),
 231        .dev            = {
 232                .platform_data  = &scif2_platform_data,
 233        },
 234};
 235
 236static struct plat_sci_port scif3_platform_data = {
 237        .scscr          = SCSCR_REIE,
 238        .type           = PORT_SCIF,
 239        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
 240};
 241
 242static struct resource scif3_resources[] = {
 243        DEFINE_RES_MEM(0xfffe9800, 0x100),
 244        DEFINE_RES_IRQ(204),
 245};
 246
 247static struct platform_device scif3_device = {
 248        .name           = "sh-sci",
 249        .id             = 3,
 250        .resource       = scif3_resources,
 251        .num_resources  = ARRAY_SIZE(scif3_resources),
 252        .dev            = {
 253                .platform_data  = &scif3_platform_data,
 254        },
 255};
 256
 257static struct sh_timer_config cmt_platform_data = {
 258        .channels_mask = 3,
 259};
 260
 261static struct resource cmt_resources[] = {
 262        DEFINE_RES_MEM(0xfffec000, 0x10),
 263        DEFINE_RES_IRQ(142),
 264        DEFINE_RES_IRQ(143),
 265};
 266
 267static struct platform_device cmt_device = {
 268        .name           = "sh-cmt-16",
 269        .id             = 0,
 270        .dev = {
 271                .platform_data  = &cmt_platform_data,
 272        },
 273        .resource       = cmt_resources,
 274        .num_resources  = ARRAY_SIZE(cmt_resources),
 275};
 276
 277static struct resource mtu2_resources[] = {
 278        DEFINE_RES_MEM(0xfffe4000, 0x400),
 279        DEFINE_RES_IRQ_NAMED(146, "tgi0a"),
 280        DEFINE_RES_IRQ_NAMED(153, "tgi1a"),
 281};
 282
 283static struct platform_device mtu2_device = {
 284        .name           = "sh-mtu2",
 285        .id             = -1,
 286        .resource       = mtu2_resources,
 287        .num_resources  = ARRAY_SIZE(mtu2_resources),
 288};
 289
 290static struct resource rtc_resources[] = {
 291        [0] = {
 292                .start  = 0xffff2000,
 293                .end    = 0xffff2000 + 0x58 - 1,
 294                .flags  = IORESOURCE_IO,
 295        },
 296        [1] = {
 297                /* Shared Period/Carry/Alarm IRQ */
 298                .start  = 231,
 299                .flags  = IORESOURCE_IRQ,
 300        },
 301};
 302
 303static struct platform_device rtc_device = {
 304        .name           = "sh-rtc",
 305        .id             = -1,
 306        .num_resources  = ARRAY_SIZE(rtc_resources),
 307        .resource       = rtc_resources,
 308};
 309
 310static struct platform_device *sh7203_devices[] __initdata = {
 311        &scif0_device,
 312        &scif1_device,
 313        &scif2_device,
 314        &scif3_device,
 315        &cmt_device,
 316        &mtu2_device,
 317        &rtc_device,
 318};
 319
 320static int __init sh7203_devices_setup(void)
 321{
 322        return platform_add_devices(sh7203_devices,
 323                                    ARRAY_SIZE(sh7203_devices));
 324}
 325arch_initcall(sh7203_devices_setup);
 326
 327void __init plat_irq_setup(void)
 328{
 329        register_intc_controller(&intc_desc);
 330}
 331
 332static struct platform_device *sh7203_early_devices[] __initdata = {
 333        &scif0_device,
 334        &scif1_device,
 335        &scif2_device,
 336        &scif3_device,
 337        &cmt_device,
 338        &mtu2_device,
 339};
 340
 341#define STBCR3 0xfffe0408
 342#define STBCR4 0xfffe040c
 343
 344void __init plat_early_device_setup(void)
 345{
 346        /* enable CMT clock */
 347        __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
 348
 349        /* enable MTU2 clock */
 350        __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
 351
 352        early_platform_add_devices(sh7203_early_devices,
 353                                   ARRAY_SIZE(sh7203_early_devices));
 354}
 355