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7#include <linux/platform_device.h>
8#include <linux/init.h>
9#include <linux/serial.h>
10#include <linux/sh_timer.h>
11#include <linux/sh_intc.h>
12#include <linux/serial_sci.h>
13#include <linux/io.h>
14
15enum {
16 UNUSED = 0,
17
18
19 IRL0, IRL1, IRL2, IRL3,
20 HUDI, GPIOI, DMAC,
21 IRQ4, IRQ5, IRQ6, IRQ7,
22 HCAN20, HCAN21,
23 SSI0, SSI1,
24 HAC0, HAC1,
25 I2C0, I2C1,
26 USB, LCDC,
27 DMABRG0, DMABRG1, DMABRG2,
28 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
29 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
30 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
31 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
32 HSPI,
33 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
34 MFI, ADC, CMT,
35 TMU0, TMU1, TMU2,
36 WDT, REF,
37
38
39 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
40};
41
42static struct intc_vect vectors[] __initdata = {
43 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
44 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
45 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
46 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
47 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
48 INTC_VECT(DMAC, 0x6c0),
49 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
50 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
51 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
52 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
53 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
54 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
55 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
56 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
57 INTC_VECT(DMABRG2, 0xac0),
58 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
59 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
60 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
61 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
62 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
63 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
64 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
65 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
66 INTC_VECT(HSPI, 0xc80),
67 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
68 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
69 INTC_VECT(MFI, 0xe80),
70 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
71 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
72 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
73 INTC_VECT(WDT, 0x560),
74 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
75};
76
77static struct intc_group groups[] __initdata = {
78 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
79 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
80 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
81 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
82 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
83 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
84};
85
86static struct intc_mask_reg mask_registers[] __initdata = {
87 { 0xfe080040, 0xfe080060, 32,
88 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
89 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
90 0, DMABRG0, DMABRG1, DMABRG2,
91 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
92 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
93 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
94 { 0xfe080044, 0xfe080064, 32,
95 { 0, 0, 0, 0, 0, 0, 0, 0,
96 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
97 HSPI, MMCIF0, MMCIF1, MMCIF2,
98 MMCIF3, 0, 0, 0, 0, 0, 0, 0,
99 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
100};
101
102static struct intc_prio_reg prio_registers[] __initdata = {
103 { 0xffd00004, 0, 16, 4, { TMU0, TMU1, TMU2 } },
104 { 0xffd00008, 0, 16, 4, { WDT, REF, 0, 0 } },
105 { 0xffd0000c, 0, 16, 4, { GPIOI, DMAC, 0, HUDI } },
106 { 0xffd00010, 0, 16, 4, { IRL0, IRL1, IRL2, IRL3 } },
107 { 0xfe080000, 0, 32, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
108 { 0xfe080004, 0, 32, 4, { HCAN20, HCAN21, SSI0, SSI1,
109 HAC0, HAC1, I2C0, I2C1 } },
110 { 0xfe080008, 0, 32, 4, { USB, LCDC, DMABRG, SCIF0,
111 SCIF1, SCIF2, SIM, HSPI } },
112 { 0xfe08000c, 0, 32, 4, { 0, 0, MMCIF, 0,
113 MFI, 0, ADC, CMT } },
114};
115
116static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
117 mask_registers, prio_registers, NULL);
118
119static struct intc_vect vectors_irq[] __initdata = {
120 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
121 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
122};
123
124static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
125 mask_registers, prio_registers, NULL);
126
127static struct plat_sci_port scif0_platform_data = {
128 .scscr = SCSCR_REIE,
129 .type = PORT_SCIF,
130 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
131};
132
133static struct resource scif0_resources[] = {
134 DEFINE_RES_MEM(0xfe600000, 0x100),
135 DEFINE_RES_IRQ(evt2irq(0x880)),
136 DEFINE_RES_IRQ(evt2irq(0x8a0)),
137 DEFINE_RES_IRQ(evt2irq(0x8e0)),
138 DEFINE_RES_IRQ(evt2irq(0x8c0)),
139};
140
141static struct platform_device scif0_device = {
142 .name = "sh-sci",
143 .id = 0,
144 .resource = scif0_resources,
145 .num_resources = ARRAY_SIZE(scif0_resources),
146 .dev = {
147 .platform_data = &scif0_platform_data,
148 },
149};
150
151static struct plat_sci_port scif1_platform_data = {
152 .type = PORT_SCIF,
153 .scscr = SCSCR_REIE,
154 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
155};
156
157static struct resource scif1_resources[] = {
158 DEFINE_RES_MEM(0xfe610000, 0x100),
159 DEFINE_RES_IRQ(evt2irq(0xb00)),
160 DEFINE_RES_IRQ(evt2irq(0xb20)),
161 DEFINE_RES_IRQ(evt2irq(0xb60)),
162 DEFINE_RES_IRQ(evt2irq(0xb40)),
163};
164
165static struct platform_device scif1_device = {
166 .name = "sh-sci",
167 .id = 1,
168 .resource = scif1_resources,
169 .num_resources = ARRAY_SIZE(scif1_resources),
170 .dev = {
171 .platform_data = &scif1_platform_data,
172 },
173};
174
175static struct plat_sci_port scif2_platform_data = {
176 .scscr = SCSCR_REIE,
177 .type = PORT_SCIF,
178 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
179};
180
181static struct resource scif2_resources[] = {
182 DEFINE_RES_MEM(0xfe620000, 0x100),
183 DEFINE_RES_IRQ(evt2irq(0xb80)),
184 DEFINE_RES_IRQ(evt2irq(0xba0)),
185 DEFINE_RES_IRQ(evt2irq(0xbe0)),
186 DEFINE_RES_IRQ(evt2irq(0xbc0)),
187};
188
189static struct platform_device scif2_device = {
190 .name = "sh-sci",
191 .id = 2,
192 .resource = scif2_resources,
193 .num_resources = ARRAY_SIZE(scif2_resources),
194 .dev = {
195 .platform_data = &scif2_platform_data,
196 },
197};
198
199static struct plat_sci_port scif3_platform_data = {
200
201
202
203
204
205
206
207 .type = PORT_SCI,
208};
209
210static struct resource scif3_resources[] = {
211 DEFINE_RES_MEM(0xfe480000, 0x10),
212 DEFINE_RES_IRQ(evt2irq(0xc00)),
213 DEFINE_RES_IRQ(evt2irq(0xc20)),
214 DEFINE_RES_IRQ(evt2irq(0xc40)),
215};
216
217static struct platform_device scif3_device = {
218 .name = "sh-sci",
219 .id = 3,
220 .resource = scif3_resources,
221 .num_resources = ARRAY_SIZE(scif3_resources),
222 .dev = {
223 .platform_data = &scif3_platform_data,
224 },
225};
226
227static struct sh_timer_config tmu0_platform_data = {
228 .channels_mask = 7,
229};
230
231static struct resource tmu0_resources[] = {
232 DEFINE_RES_MEM(0xffd80000, 0x30),
233 DEFINE_RES_IRQ(evt2irq(0x400)),
234 DEFINE_RES_IRQ(evt2irq(0x420)),
235 DEFINE_RES_IRQ(evt2irq(0x440)),
236};
237
238static struct platform_device tmu0_device = {
239 .name = "sh-tmu",
240 .id = 0,
241 .dev = {
242 .platform_data = &tmu0_platform_data,
243 },
244 .resource = tmu0_resources,
245 .num_resources = ARRAY_SIZE(tmu0_resources),
246};
247
248
249static struct platform_device *sh7760_devices[] __initdata = {
250 &scif0_device,
251 &scif1_device,
252 &scif2_device,
253 &scif3_device,
254 &tmu0_device,
255};
256
257static int __init sh7760_devices_setup(void)
258{
259 return platform_add_devices(sh7760_devices,
260 ARRAY_SIZE(sh7760_devices));
261}
262arch_initcall(sh7760_devices_setup);
263
264static struct platform_device *sh7760_early_devices[] __initdata = {
265 &scif0_device,
266 &scif1_device,
267 &scif2_device,
268 &scif3_device,
269 &tmu0_device,
270};
271
272void __init plat_early_device_setup(void)
273{
274 early_platform_add_devices(sh7760_early_devices,
275 ARRAY_SIZE(sh7760_early_devices));
276}
277
278#define INTC_ICR 0xffd00000UL
279#define INTC_ICR_IRLM (1 << 7)
280
281void __init plat_irq_setup_pins(int mode)
282{
283 switch (mode) {
284 case IRQ_MODE_IRQ:
285 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
286 register_intc_controller(&intc_desc_irq);
287 break;
288 default:
289 BUG();
290 }
291}
292
293void __init plat_irq_setup(void)
294{
295 register_intc_controller(&intc_desc);
296}
297
