1
2menu "Memory management options"
3
4config MMU
5 bool "Support for memory management hardware"
6 depends on !CPU_SH2
7 default y
8 help
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
10 boot on these systems, this option must not be set.
11
12 On other systems (such as the SH-3 and 4) where an MMU exists,
13 turning this off will boot the kernel on these machines with the
14 MMU implicitly switched off.
15
16config PAGE_OFFSET
17 hex
18 default "0x80000000" if MMU && SUPERH32
19 default "0x20000000" if MMU && SUPERH64
20 default "0x00000000"
21
22config FORCE_MAX_ZONEORDER
23 int "Maximum zone order"
24 range 9 64 if PAGE_SIZE_16KB
25 default "9" if PAGE_SIZE_16KB
26 range 7 64 if PAGE_SIZE_64KB
27 default "7" if PAGE_SIZE_64KB
28 range 11 64
29 default "14" if !MMU
30 default "11"
31 help
32 The kernel memory allocator divides physically contiguous memory
33 blocks into "zones", where each zone is a power of two number of
34 pages. This option selects the largest power of two that the kernel
35 keeps in the memory allocator. If you need to allocate very large
36 blocks of physically contiguous memory, then you may need to
37 increase this value.
38
39 This config option is actually maximum order plus one. For example,
40 a value of 11 means that the largest free memory block is 2^10 pages.
41
42 The page size is not necessarily 4KB. Keep this in mind when
43 choosing a value for this option.
44
45config MEMORY_START
46 hex "Physical memory start address"
47 default "0x08000000"
48 ---help---
49 Computers built with Hitachi SuperH processors always
50 map the ROM starting at address zero. But the processor
51 does not specify the range that RAM takes.
52
53 The physical memory (RAM) start address will be automatically
54 set to 08000000. Other platforms, such as the Solution Engine
55 boards typically map RAM at 0C000000.
56
57 Tweak this only when porting to a new machine which does not
58 already have a defconfig. Changing it from the known correct
59 value on any of the known systems will only lead to disaster.
60
61config MEMORY_SIZE
62 hex "Physical memory size"
63 default "0x04000000"
64 help
65 This sets the default memory size assumed by your SH kernel. It can
66 be overridden as normal by the 'mem=' argument on the kernel command
67 line. If unsure, consult your board specifications or just leave it
68 as 0x04000000 which was the default value before this became
69 configurable.
70
71
72
73config 29BIT
74 def_bool !32BIT
75 depends on SUPERH32
76 select UNCACHED_MAPPING
77
78config 32BIT
79 bool
80 default y if CPU_SH5 || !MMU
81
82config PMB
83 bool "Support 32-bit physical addressing through PMB"
84 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
85 select 32BIT
86 select UNCACHED_MAPPING
87 help
88 If you say Y here, physical addressing will be extended to
89 32-bits through the SH-4A PMB. If this is not set, legacy
90 29-bit physical addressing will be used.
91
92config X2TLB
93 def_bool y
94 depends on (CPU_SHX2 || CPU_SHX3) && MMU
95
96config VSYSCALL
97 bool "Support vsyscall page"
98 depends on MMU && (CPU_SH3 || CPU_SH4)
99 default y
100 help
101 This will enable support for the kernel mapping a vDSO page
102 in process space, and subsequently handing down the entry point
103 to the libc through the ELF auxiliary vector.
104
105 From the kernel side this is used for the signal trampoline.
106 For systems with an MMU that can afford to give up a page,
107 (the default value) say Y.
108
109config NUMA
110 bool "Non Uniform Memory Access (NUMA) Support"
111 depends on MMU && SYS_SUPPORTS_NUMA
112 select ARCH_WANT_NUMA_VARIABLE_LOCALITY
113 default n
114 help
115 Some SH systems have many various memories scattered around
116 the address space, each with varying latencies. This enables
117 support for these blocks by binding them to nodes and allowing
118 memory policies to be used for prioritizing and controlling
119 allocation behaviour.
120
121config NODES_SHIFT
122 int
123 default "3" if CPU_SUBTYPE_SHX3
124 default "1"
125 depends on NEED_MULTIPLE_NODES
126
127config ARCH_FLATMEM_ENABLE
128 def_bool y
129 depends on !NUMA
130
131config ARCH_SPARSEMEM_ENABLE
132 def_bool y
133 select SPARSEMEM_STATIC
134
135config ARCH_SPARSEMEM_DEFAULT
136 def_bool y
137
138config ARCH_SELECT_MEMORY_MODEL
139 def_bool y
140
141config ARCH_ENABLE_MEMORY_HOTPLUG
142 def_bool y
143 depends on SPARSEMEM && MMU
144
145config ARCH_ENABLE_MEMORY_HOTREMOVE
146 def_bool y
147 depends on SPARSEMEM && MMU
148
149config ARCH_MEMORY_PROBE
150 def_bool y
151 depends on MEMORY_HOTPLUG
152
153config IOREMAP_FIXED
154 def_bool y
155 depends on X2TLB || SUPERH64
156
157config UNCACHED_MAPPING
158 bool
159
160config HAVE_SRAM_POOL
161 bool
162 select GENERIC_ALLOCATOR
163
164choice
165 prompt "Kernel page size"
166 default PAGE_SIZE_4KB
167
168config PAGE_SIZE_4KB
169 bool "4kB"
170 help
171 This is the default page size used by all SuperH CPUs.
172
173config PAGE_SIZE_8KB
174 bool "8kB"
175 depends on !MMU || X2TLB
176 help
177 This enables 8kB pages as supported by SH-X2 and later MMUs.
178
179config PAGE_SIZE_16KB
180 bool "16kB"
181 depends on !MMU
182 help
183 This enables 16kB pages on MMU-less SH systems.
184
185config PAGE_SIZE_64KB
186 bool "64kB"
187 depends on !MMU || CPU_SH4 || CPU_SH5
188 help
189 This enables support for 64kB pages, possible on all SH-4
190 CPUs and later.
191
192endchoice
193
194choice
195 prompt "HugeTLB page size"
196 depends on HUGETLB_PAGE
197 default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
198 default HUGETLB_PAGE_SIZE_64K
199
200config HUGETLB_PAGE_SIZE_64K
201 bool "64kB"
202 depends on !PAGE_SIZE_64KB
203
204config HUGETLB_PAGE_SIZE_256K
205 bool "256kB"
206 depends on X2TLB
207
208config HUGETLB_PAGE_SIZE_1MB
209 bool "1MB"
210
211config HUGETLB_PAGE_SIZE_4MB
212 bool "4MB"
213 depends on X2TLB
214
215config HUGETLB_PAGE_SIZE_64MB
216 bool "64MB"
217 depends on X2TLB
218
219config HUGETLB_PAGE_SIZE_512MB
220 bool "512MB"
221 depends on CPU_SH5
222
223endchoice
224
225config SCHED_MC
226 bool "Multi-core scheduler support"
227 depends on SMP
228 default y
229 help
230 Multi-core scheduler support improves the CPU scheduler's decision
231 making when dealing with multi-core CPU chips at a cost of slightly
232 increased overhead in some places. If unsure say N here.
233
234endmenu
235
236menu "Cache configuration"
237
238config SH7705_CACHE_32KB
239 bool "Enable 32KB cache size for SH7705"
240 depends on CPU_SUBTYPE_SH7705
241 default y
242
243choice
244 prompt "Cache mode"
245 default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
246 default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
247
248config CACHE_WRITEBACK
249 bool "Write-back"
250
251config CACHE_WRITETHROUGH
252 bool "Write-through"
253 help
254 Selecting this option will configure the caches in write-through
255 mode, as opposed to the default write-back configuration.
256
257 Since there's sill some aliasing issues on SH-4, this option will
258 unfortunately still require the majority of flushing functions to
259 be implemented to deal with aliasing.
260
261 If unsure, say N.
262
263config CACHE_OFF
264 bool "Off"
265
266endchoice
267
268endmenu
269
